Storing and restoring critical data to a storage device

Abstract

Device comprising: a memory array (102, 202), wherein the memory array (102, 202) comprises a plurality of addressable memory cells; a temperature sensor (110, 210) positioned at a first location with respect to the memory array (102, 202), the temperature sensor (110, 210) being configured to record an average temperature of the memory array (102, 202); and a controller (108, 208), wherein the controller (108, 208) is positioned at a second location with respect to the memory array (102, 202), wherein the controller (108, 208) is configured for the following: Receiving (302, 402A, 402B) an operation from a host processor (218), wherein the operation contains data and accesses one or more of the memory cells of the memory array, Determine whether the operation is critical or non-critical, based on one or more of the following characteristics: a identifier contained in the process, an address of the data of the process, or a data format of the process, If the operation is identified as a non-critical operation, process (406A, 406B) the operation in the usual manner, and If the operation is identified as a critical operation, retrieve (304) a temperature value from the memory array (102, 202) from the temperature sensor (110, 210) and conditionally process (306) the critical operation based on the temperature value.

Description

FIELD OF TECHNOLOGY

[0001] At least some of the embodiments disclosed herein relate generally to semiconductor devices and, more particularly, to improving the memory integrity of flash memory devices. STATE OF THE ART

[0002] Due to the design of flash memory cells, the bit error rate during data read operations increases when such read operations are performed in significantly different temperature environments compared to the temperature at which the data was written. For example, data written at warmer temperatures and read at cooler temperatures may experience an increase in the bit error rate, and vice versa. This increase in the bit error rate occurs in single-level cell (SLC) flash cells, but is most pronounced in multi-level cell (MLC) flash memory cells.

[0003] Generally, small fluctuations (e.g., a few degrees Celsius) typically don't significantly increase the bit error rate, but storing and reading data at different temperatures can increase the probability of data errors and reduce the data retention time of the flash device. In extreme scenarios, the data may contain significant errors and be unusable.

[0004] For example, in automotive applications, data may be stored at temperatures as high as 125°C (e.g., when the car is running) or as low as -40°C (e.g., when the car is turned off in winter conditions). If data stored under such conditions is read at room temperature (e.g., 25°C), additional errors may be introduced due to the extended range between read and write temperatures. Furthermore, the data retention time of flash memory may be significantly reduced.

[0005] While these effects can cause inconvenience in many scenarios, in others they can cause critical and, in some cases, life-threatening errors. Critical applications such as black box recorders in vehicle and avionics systems can produce erroneous data during operation when such reads occur. Furthermore, data from black boxes is often written at extreme temperatures and almost always read at approximately room temperature.

[0006] Current flash memory does not take temperature into account when performing read and write operations and therefore cannot solve these and other problems.

[0007] US 2020 / 0143847 A1 relates to a flash memory device in which each memory cube includes a temperature sensor. The controller of the flash memory device is configured to control the writing of data based on the probability that the data to be written will be changed again and the temperature of the memory cube. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram illustrating a flash memory chip according to some embodiments of the disclosure. Fig. 2 is a block diagram of a memory device according to some embodiments of the disclosure. Fig. 3 is a flowchart illustrating a method for mediating access to a memory array based on temperature data, according to some embodiments of the disclosure. Fig. 4A is a flowchart illustrating a method for processing a write operation based on temperature data, according to some embodiments of the disclosure. Fig. 4B is a flowchart illustrating a method for processing a read based on temperature data, according to some embodiments of the disclosure. Fig. 5 is a block diagram illustrating a memory system according to some embodiments of the disclosure. Fig. 6 is a block diagram illustrating a computing device showing an example embodiment of a computing device used in the various embodiments of the disclosure. DETAILED DESCRIPTION

[0008] The disclosed embodiments solve the aforementioned problems and other problems in the prior art. The disclosed embodiments use a temperature sensor in a memory device to monitor the average temperature of the device. This temperature is redundantly stored in a separate memory area when critical data is written and used when the same data is read to determine whether the temperature change affects the integrity of the read data.

[0009] Fig. 1 is a diagram illustrating a flash memory chip according to some embodiments of the disclosure. Fig. 1 provides a top view (100a) and a side view (100b) of a flash memory chip.

[0010] In the illustrated embodiment, the chip includes a memory array portion (102). The array (102) may include a plurality of flash memory cells. In one embodiment, the array (102) includes a plurality of SLC or MLC cells. In some embodiments, the array (102) is homogeneous (i.e., contains only SLC or MLC cells). In other embodiments, the array (102) may include multiple cell types (i.e., a mix of SLC and MLC cells). Although reference is made to MLCs, other types of flash memory cells may be used, such as triple-level cells (TLC), quad-level cells (QLC), penta-level cells (PLC), etc. In some embodiments, the cells may be pseudo-SLC (pSLC) cells. A pSLC cell includes an MLC cell, which may be configured to store a single bit of information and thus function as an SLC cell.The array (102) may comprise a planar, two-dimensional (2D) array of memory cells. Alternatively, the array (102) may comprise a three-dimensional (3D) array of memory cells. The specific arrangement and type of cells in the array (102) should not be considered unreasonable.

[0011] In the illustrated embodiment, the array (102) extends across both axes of the flash chip. In other embodiments, the array (102) may extend across only a portion of the total chip area. For example, the array (102) may be "L-shaped," with the controller (108) "filling" the remainder of the chip. In such an embodiment, the array (102) and the controller (108) may be coplanar. However, in the illustrated embodiment, the controller (108) is located above the memory array (102), as shown in the side view (100b).

[0012] In the illustrated embodiment, the controller (108) and a temperature sensor (110) are located above the memory array (102). The controller (108) is communicatively coupled to the array (102) via a plurality of conductive traces (not shown) or fabricated traces (not shown). Likewise, the temperature sensor (110) may be connected to the controller (108) via one or more conductive traces (not shown) or fabricated traces (not shown).

[0013] In the illustrated embodiment, the controller (108) mediates access to the underlying memory array (102). The controller (108) receives requests from a host processor and responds to those requests by accessing the memory array (102). The controller (108) may implement any techniques for accessing a flash memory array, and details of routine or standard operations are not repeated in detail herein. However, as will be discussed, the controller (108) may implement additional operations not found in existing controllers.

[0014] In particular, the controller (108) may modify conventional read and write operations to use temperature values ​​recorded by the temperature sensor (110). In one embodiment, the sensor (110) may be a complementary metal-oxide-semiconductor (CMOS) sensor that monitors the temperature of the array (102) or the entire die package of the array (102). In the illustrated embodiment, the sensor (110) is located in the center of the array (102) or die. However, the specific placement of the sensor (110) is not intended to be limiting. That is, in some embodiments, the placement of the sensor (110) may be chosen based on the dimensions of the underlying memory array (102).In the illustrated embodiment, the storage array (102) is rectangular, and thus the sensor (110) is placed in the center of the array (102) to capture a homogeneous temperature value across the entire array (102). In some embodiments, the sensor (110) can be positioned as far away from the controller (108) as possible while still reading an average temperature of the array (102).

[0015] In the illustrated embodiment, the temperature of the array (102) includes a hot region (106) and a cooler region (104). These regions (104, 106) are for illustrative purposes only, and there may be no physical distinction within the memory array (102). In the illustrated embodiment, the hot region (106) includes a region around the controller (108). In some embodiments, regions around a controller have higher temperatures due to the power consumption of the controller, which is additively coupled to the power consumption of the memory cells. Thus, the region (106) generally has a higher temperature than the region (104) farther from the controller (108). Thus, the temperature of the cells within the memory array (102) varies depending on whether a given cell is in the hot region (106) or the cooler region (104).

[0016] In the illustrated embodiment, the sensor (110) measures the average temperature of the entire memory array (102) due to its placement in the center of the array (102) or generally at a position that captures both hot and cooler regions (104, 106). As will be described in more detail herein, this temperature is used to modify read and write operations to account for temperature changes of the memory array.

[0017] Fig. 2 is a block diagram of a memory device according to some embodiments of the disclosure.

[0018] In the illustrated embodiment, a flash chip (200) includes a memory array (202), a controller (208), and a temperature sensor (210). The chip (200) can Fig. 1 and accordingly, the array (202), the controller (208) and the temperature sensor (210) correspond to the array (102), the controller (108) and the sensor (110) of Fig. 1. The description of the details of these components is not repeated here, and the focus is on the interaction between the components (202, 208, 210).

[0019] In the illustrated embodiment, the sensor (210) periodically reports temperature readings to the controller (210), and in particular to a temperature processor (214). In one embodiment, the sensor (210) transmits the temperature data of the chip (202) to the temperature processor (214) at regular intervals (e.g., every 10 microseconds). Alternatively, or in conjunction with the above, the temperature processor (214) may poll the sensor (210) at regular intervals. In this alternative, the temperature processor (214) may be configured to adjust the polling interval. In one embodiment, the polling interval may be a function of the last read temperature. For example, the temperature processor (214) may increase the polling frequency if the last read temperature exceeds a threshold (e.g.,a high or low critical temperature), and decrease the polling interval when the temperature is in a medium range. For example, if the last read temperature is between -30°C and 120°C, the temperature processor (214) can poll the sensor (210) at a first polling rate (e.g., 30 microseconds). If the last read temperature exceeds -30°C or 120°C, the temperature processor (214) can increase the polling rate to a second rate (e.g., every 10 microseconds). When the temperature is again between -30°C and 120°C, the temperature processor (214) can return to the first polling rate. In this way, the power consumption of the temperature processor (214) and thus of the controller (208) is reduced when the chip (202) is operating within an acceptable temperature range. Thus, in some embodiments, the temperature processor (214) receives a stream of real-time temperature data from the sensor (210).In an alternative embodiment, the temperature processor (214) may be configured to read temperature data from the sensor (210) in response to read or write commands received from the read / write logic (216).

[0020] In the illustrated embodiment, the controller (208) receives write commands via the read / write logic (216). The write commands include instructions to write data to the addresses of cells in the underlying memory array (202). As described in more detail in Fig. 4A, some of this data to be written may include critical data. In response to receiving critical data, the read / write logic (216) identifies a location to which the data should be written by querying a critical access table (212). This table (212) stores locations located in a cooler area (e.g., 104) of the chip (202). In the illustrated embodiment, the table (212) stores physical addresses of such locations and is used as part of the logical block address (LBA) to physical block address (PBA) mapping performed by the read / write logic (216). This LBA / PBA mapping may be performed by a flash translation layer according to various known techniques and may be modified by the processes described herein, where the table (212) is used to identify the PBA as part of the translation.In some embodiments, the table (212) additionally stores addresses of temperature read locations associated with a given PBA. Therefore, for each address to which the controller (208) writes critical data, the table (212) stores one or more addresses of PBAs of the array (202) to which temperature data is also written.

[0021] When writing critical data and after identifying a PBA from the table (212), the temperature processor (214) reads the current temperature of the chip (202) from the sensor (210). The read / write logic (216) then receives or retrieves the temperature from the temperature processor (214) and writes the temperature value along with the critical data to the memory array (202). In one embodiment, the controller (208) may store the temperature values ​​in the critical access table (212). Details on writing data are described in the description of Fig. 4A and are not repeated here.

[0022] The read / write logic (216) also receives requests to read data, including critical data. When reading critical data, the read / write logic (216) accesses the table (212) to identify the corresponding temperature values. The read / write logic (216) then uses the temperature values ​​to determine whether to continue reading the critical data from the corresponding PBA stored in the table (212). Details on the read data are described in the description of Fig. 4B and are not repeated here.

[0023] Fig. 3 is a flowchart illustrating a method for mediating access to a memory array based on temperature data, according to some embodiments of the disclosure.

[0024] In step 302, the method receives an operation. In one embodiment, the operation comprises a read or write operation. In one embodiment, the operation includes a data address. In one embodiment, the address includes an LBA. In one embodiment, the address is included in both the read and write operations. For a write operation, the operation further includes data to be written to the location. In some embodiments, the write operation may further include a tag or other identifier that signals that the data is critical data. In other embodiments, the method may determine that the data is critical data based on the data or the address of the data. For example, the method may analyze the data format to determine if the data is critical data.In other embodiments, all writes to certain locations may be considered critical data writes. As used herein, a read that reads critical data is referred to as a critical read, and a write that writes critical data is referred to as a critical write. Critical reads and critical writes are collectively referred to as critical operations.

[0025] In some embodiments, the method may conditionally process operations. In these embodiments, the method determines whether the operations are critical operations. If not, the method may typically process the operations in any manner executable by a storage device, such as a flash memory device. Alternatively, if the operations are critical operations, the method proceeds to step 304.

[0026] Although described in the context of read and write operations, any operation that accesses or affects critical data can also be processed as follows.

[0027] In step 304, the method processes temperature data. In one embodiment, the operation of step 304 may vary depending on the type of operation.

[0028] If the operation is a critical write, the method may retrieve a current temperature value in step 304. As described above, the method may query a temperature sensor to retrieve the current temperature of the storage array when the critical write is received.

[0029] If the operation is a critical read, the method may read previously stored or historical temperature data that was written when the address last accessed by the read was written. The method may also query a temperature sensor to obtain the current temperature of the storage array when the critical read is received. In some embodiments, the method may read multiple historical temperature data values ​​as part of critical read step 304. Thus, the critical read method obtains a current temperature value and one or more historical temperature values.

[0030] In step 306, the method processes the operation based on the temperature data. As described above, for a critical operation, the method uses the temperature data retrieved in step 304 to modify the normal reading, writing, or accessing of critical data.

[0031] For critical writes, the method writes the temperature data to multiple locations in the memory array along with writing the critical data to the memory array. The method also updates a table that maps critical data addresses to the addresses where temperature data is written. In one embodiment, the method writes the temperature data to an SLC or pSLC portion of the memory array, while the critical data can be written to any portion of the memory array. In one embodiment, the method writes the same temperature reading three times for redundancy.

[0032] For critical reads, the method queries the table that maps critical data addresses to the addresses where temperature data is written, and retrieves the addresses where historical temperature data associated with the critical data address is stored. The method will then read these temperatures and determine which of the values ​​to use, in one embodiment based on a majority vote function. The method then compares the selected temperature value to the current temperature read in step 304. Based on this comparison, the method can determine whether to read the critical data or raise an error.

[0033] The above embodiments are described for both read and write operations, but, as mentioned, can be applied more generally to any access to a memory array. Details specific to write and read operations are discussed in more detail in the Fig. 4A and below 4B.

[0034] Fig. 4A is a flowchart illustrating a method for processing a write operation based on temperature data, according to some embodiments of the disclosure.

[0035] In step 402a, the method receives a write operation. In one embodiment, the write operation may include a critical write operation or a non-critical write operation. Generally, a write operation includes at least a write address and data to be written. In one embodiment, the write address includes an LBA. In some embodiments, the write operation may include a flag indicating that the data is critical data. As mentioned, a controller of a memory device receives the write operation from a host processor.

[0036] In step 404a, the method determines whether the write operation is a critical write operation.

[0037] In one embodiment, the write operation includes a flag indicating that the data is critical data. This flag may comprise a single bit (e.g., an active-high bit). In this scenario, the method analyzes the write operation to determine if the flag is set. If so, the method determines that the write operation is a critical write operation.

[0038] In another embodiment, the method may determine that the write operation is a critical write based on the data or the write address. In the former case, the method may analyze the data to be written to determine whether the data contains critical data based on one or more preconfigured patterns of the data to be written. In the latter case, the method may determine whether the write address is intended to store critical data. If either determination is made, the method determines that the write operation is a critical write.

[0039] In another embodiment, the method may support two separate write commands: one for critical data and one for non-critical data. In this embodiment, the method determines whether the write operation code matches a critical write operation code, and if so, determines that the write operation is a critical write operation.

[0040] If the method determines that the write operation is not a critical write operation, the method processes the write operation normally in step 406a. As used herein, processing an operation typically refers to using known techniques for writing to an underlying storage medium. For example, the method may perform an LBA-to-PBA mapping on the write command and proceed to write the data in the operation to the associated PBA. Various other operations may be performed by the controller when a standard write is performed, and these operations are not described here.

[0041] Alternatively, if the method determines that the write operation is a critical write operation, the method continues to step 408a to process the write operation based on temperature data.

[0042] In step 408a, the method identifies a critical address location where the critical data will be stored. In one embodiment, the method queries a critical address table (e.g., 212) to identify one or more PBAs for storing the critical data. In this context, step 408a overrides a conventional LBA-to-PBA mapping by using a set of PBAs used for critical data. The critical addresses are generally located farther from the controller in a cooler area (e.g., 104) of the memory chip. In some embodiments, the method may cause an error if no critical addresses remain.

[0043] In step 410a, the method stores the critical data at the critical address location. In one embodiment, the method performs a program or write operation to write the data to the critical address location in the critical write operation. Details of programming a PBA or similar address are not described in detail herein, and any techniques for writing data to a memory address may be used.

[0044] In step 412a, the method reads a temperature reading. In one embodiment, the method queries a temperature sensor of the storage device to obtain the temperature reading. The temperature reading read in step 412a is the current temperature of the storage device when the write was performed in step 410a. In some embodiments, the temperature reading includes the average temperature of the storage device due to the placement of the temperature sensor, as previously mentioned.

[0045] In step 414a, the method redundantly stores the temperature readout value.

[0046] In the illustrated embodiment, the method stores multiple copies of the temperature reading read in step 412a. For example, in some embodiments, the method may write the temperature reading to three separate locations in the storage device. In some embodiments, the locations storing the temperature readings are located in a cooler area of ​​the storage device. In some embodiments, the temperature readings are stored in SLC or pSLC locations of the underlying storage array. In general, any location that provides improved read accuracy may be used, and SLC and pSLC are provided merely as examples.

[0047] In some embodiments, the method may further store the addresses to which temperature readings are written to memory, such as in the critical address table. In these embodiments, the method links the critical address written to at 410a with the multiple addresses written to at 414a. Thus, during subsequent reads to the critical address location, the controller may look up the temperature reading addresses associated with the critical address location.

[0048] In another embodiment, the addresses used to store temperature data may be deterministically calculated based on the critical data address. Thus, storing the addresses used to store temperature data may not be required.

[0049] After writing the critical data in step 410a and writing the redundant temperature readings in step 414a, the method returns a response to the host processor, which issues the write operation. Details of the response are not limiting, and any mechanism for returning a response to a write operation may be used.

[0050] Fig. 4B is a flowchart illustrating a method for processing a read based on temperature data, according to some embodiments of the disclosure.

[0051] In step 402b, the method receives a read operation. In one embodiment, the read operation may include a critical read operation or a non-critical read operation. Generally, a read operation includes at least a read address. In one embodiment, the read address includes an LBA. In some embodiments, the read operation may include a flag indicating that read data is critical data. As previously mentioned, a controller of a memory device receives the read operation from a host processor.

[0052] In step 404b, the method determines whether the read is a critical read.

[0053] In one embodiment, the read operation includes a flag indicating that the read data is critical data. This flag may comprise a single bit (e.g., an active high bit). In this scenario, the method analyzes the read operation to determine if the flag is set. If so, the method determines that the read operation is a critical read operation.

[0054] In another embodiment, the method may determine that the read operation is a critical read based on the read address. In this embodiment, the method may determine whether the read address is intended to store critical data. If either determination is made, the method determines that the read operation is a critical read.

[0055] In another embodiment, the method may support two separate read commands: one for critical data and one for non-critical data. In this embodiment, the method determines whether the operation code of the read operation matches a critical read operation code, and if so, determines that the read operation is a critical read.

[0056] If the method determines that the read operation is not a critical read operation, the method processes the read operation normally in step 406b. As used herein, processing an operation typically refers to using known techniques for writing to an underlying storage medium. For example, the method may perform an LBA-to-PBA mapping for the read command and proceed with reading the data in the operation to the associated PBA. Various other operations may be performed by the controller when performing a standard read operation, and these operations are not described in this document.

[0057] Alternatively, if the method determines that the read is a critical read, the method may continue to step 408b to process the read based on temperature data.

[0058] In step 408b, the method reads temperature readings for a critical address corresponding to the critical read. In one embodiment, the method uses the critical read address to query a critical address table. As described above, in some embodiments, the critical address table maps critical data addresses to a plurality of addresses that store temperature readings. In another embodiment, the addresses used to store temperature data may be deterministically calculated based on the critical data address. After identifying the addresses, the method reads the temperature readings from each of the addresses.

[0059] In step 410b, the method performs a majority vote function on the readings. In one embodiment, a majority vote function includes a function that returns the temperature reading stored by a majority of the addresses storing temperature data. Thus, if two out of three addresses store the same temperature value and a third address stores a different value, the value stored by the two out of three addresses is considered the temperature value output of the majority vote function. In some embodiments, a value used in the majority vote function may have a tolerance value that allows for deviations from exact equality. Thus, the majority vote function compares temperature ranges rather than fixed values. In the illustrated embodiment, the output of the majority vote function is an agreed-upon temperature value with, in some embodiments, a tolerance.So if the addresses return (50°C, 50°C, 100°C), the majority vote function returns a value of 50°C.

[0060] In step 412b, the method analyzes the output of the majority vote function. If a majority of the values ​​read from the addresses are within the allowable range, the method reads the critical data. In the illustrated embodiment, the method may use a specified range to determine whether a read operation will be successful. This range indicates a temperature tolerance for temperature differences between write and read temperatures.

[0061] In the illustrated embodiment, the method reads the current temperature from the temperature sensor. Next, the method subtracts the output temperature from the majority vote function from the current temperature. In some embodiments, the method may calculate the absolute value of the difference. The method then compares the difference to a specified value. If the difference is less than the specified value, the method proceeds to step 414b; otherwise, the method proceeds to step 416b.

[0062] Continuing the previous example, where the output of the majority vote function is 50°C, the current temperature may be 55°C and the set value may be 20°C. In this example, the difference is 5°C, which is less than the set value of 20°C, so the method would proceed to step 414b. Alternatively, if the current temperature were 100°C (or -100°C), the difference would be 50°C, which would exceed the set value of 20°C. In this scenario, the method would proceed to step 416b.

[0063] In step 414b, the method has determined that the temperature difference is within the range and reads the critical data from memory. In the illustrated embodiment, the method may read data from memory using standard read operations as known in the art. In particular, the method may be reasonably confident that the critical data is being read correctly because the temperature change is within the range.

[0064] Alternatively, in step 416b, the method determines that the temperature difference is too extreme (i.e., exceeds the specified value) and therefore reading the critical data is unstable due to the large variation between the write and read temperatures.

[0065] In one embodiment, the method does not read the critical data from the storage device and instead returns an error code or similar structure indicating that the read operation failed. In another embodiment, the method may read the critical data but return a flag indicating that the data may be corrupted. In this embodiment, the host processor is responsible for determining whether to continue processing the critical data if an error may have occurred.

[0066] Alternatively, or in conjunction with the foregoing, the method may also include cooling or warming the device. In the illustrated embodiment, the method may first determine whether the temperature reading is above or below the current temperature and may then cool or heat the device, respectively, to reduce the temperature difference. In this embodiment, the storage device may be placed in a temperature chamber to heat or cool the device. The method may then continuously monitor the difference between the temperature in the temperature chamber and the output of the majority vote function until the difference is below the specified value. Once the difference is within the range (412b), the method may proceed to step 414b.

[0067] Fig. 5 is a block diagram illustrating a memory system according to some embodiments of the disclosure.

[0068] As in Fig. 5, a computer system (500) includes a processor (502) communicatively coupled to a memory system (506) via a bus (504). The memory system (506) includes a controller (208) communicatively coupled to one or more memory banks (508a-508n) via a bus / interface (512). As illustrated, the controller (208) includes a local cache (514), firmware (516), and an ECC module (520).

[0069] In the illustrated embodiment, the processor (502) may comprise any type of computer processor, such as a central processing unit, graphics processing unit, or other types of general-purpose or special-purpose computing devices. The processor (502) includes one or more output ports that enable the communication of address, user, and control data between the processor (502) and the memory system (506). In the illustrated embodiment, this communication is performed via the bus (504). In one embodiment, the bus (504) comprises an input / output (I / O) bus or a similar type of bus.

[0070] The memory system (506) is responsible for managing one or more memory banks (508a-508n). In one embodiment, the banks (508a-508n) comprise NAND flash chips or other non-volatile memory configurations. In one embodiment, the memory banks (508a-508n) comprise a memory array, such as the memory array (202).

[0071] The banks (508A-508N) are managed by the controller (208). In some embodiments, the controller (208) comprises a computing device configured to mediate access to and from the banks (508a-508n). In one embodiment, the controller (208) comprises an ASIC or other circuitry installed on a circuit board that houses the banks (508a-508n). In some embodiments, the controller (208) may be physically separate from the banks (508a-508n). The controller (208) communicates with the banks (508A-508N) via the interface (512). In some embodiments, this interface (512) comprises a physically wired (e.g., traced) interface. In other embodiments, the interface (512) includes a standard bus for communicating with the banks (508A-508N).

[0072] The controller (208) includes various modules (514-518). In one embodiment, the various modules (514-518) include various physically distinct modules or circuits. In other embodiments, the modules (514-518) may be implemented entirely (or partially) in software or firmware. In some embodiments, the modules (514-518) are provided in addition to the previously described temperature processor (214), critical address table (212), and read / write logic (216).

[0073] As illustrated, firmware (516) comprises the core of the controller and manages all non-operations of the controller (208). Firmware (516) may implement some or all of the methods described herein. In one embodiment, firmware (516) may implement the temperature processor (214), the critical address table (212), and the read / write logic (216) described previously.

[0074] Fig. 6 is a block diagram illustrating a computing device showing an example embodiment of a computing device used in the various embodiments of the disclosure.

[0075] The computer device (600) may have more or fewer components than those in Fig. 6. For example, a server computing device may not include audio interfaces, displays, keyboards, lights, haptic interfaces, GPS receivers, cameras, or sensors.

[0076] As shown in the figure, the device (600) includes a processing unit (CPU) (622) that communicates with a mass storage device (630) via a bus (624). The computing device (600) also includes one or more network interfaces (650), an audio interface (652), a display (654), a keyboard (656), a light (658), an input / output interface (660), a haptic interface (662), an optional global positioning system (GPS) receiver (664), and one or more cameras or other optical, thermal, or electromagnetic sensors (666). Device (600) may include one camera / sensor (666) or a plurality of cameras / sensors (666), as will be understood by those skilled in the art. The positioning of the camera(s) / sensor(s) (666) on the device (600) may vary depending on the device (600) model, device (600) capabilities, and the like, or a combination thereof.

[0077] The computing device (600) can optionally communicate with a base station (not shown) or directly with another computing device. The network interface (650) is sometimes referred to as a transceiver, transmit / receive device, or network interface card (NIC).

[0078] The audio interface (652) generates and receives audio signals, such as the sound of a human voice. For example, the audio interface (652) may be coupled to a speaker and a microphone (not shown) to enable telecommunication with others or to generate audio confirmation of an action. The display (654) may be a liquid crystal display (LCD), gas plasma display, light-emitting diode (LED), or any other type of display used with a computing device. The display (654) may also include a touch-sensitive screen arranged to receive input from an object, such as a stylus or a digit from a human hand.

[0079] The keyboard (656) may comprise any input device arranged to receive input from a user. The light (658) may provide a status indicator or provide light.

[0080] The computing device (600) also includes an input / output interface (660) for communicating with external devices using communication technologies such as USB, infrared, Bluetooth™, or the like. The haptic interface (662) provides tactile feedback to a user of the client device.

[0081] The optional GPS transceiver (664) can determine the physical coordinates of the computing device (600) on the Earth's surface, which typically output a location as latitude and longitude values. The GPS transceiver (664) can also use other geopositioning mechanisms, including but not limited to triangulation, assisted GPS (AGPS), E-OTD, CI, SAI, ETA, BSS, or the like, to further determine the physical position of the computing device (600) on the Earth's surface. However, in one embodiment, the computing device (600) can provide other information through other components that can be used to determine a physical position of the device, including, for example, a MAC address, an Internet Protocol (IP) address, or the like.

[0082] The mass storage (630) includes a RAM (632), a ROM (634), and other storage means. The mass storage (630) illustrates another example of computer storage media for storing information, such as computer-readable instructions, data structures, program modules, or other data. The mass storage (630) stores a basic input / output system (BIOS) (640) for controlling the low-level operation of the computing device (600). The mass storage also stores an operating system (641) for controlling the operation of the computing device (600).

[0083] Applications (642) may include computer-executable instructions that, when executed by the computing device (600), perform any of the methods (or portions of the methods) previously described in the description of the preceding figures. In some embodiments, the software or programs implementing the method embodiments may be read from a hard disk drive (not illustrated) and temporarily stored in RAM (632) by the CPU (622). The CPU (622) may then read the software or data from the RAM (632), process it, and store it back in the RAM (632).

[0084] The disclosure includes various apparatus that perform the methods and implement the systems described above, including data processing systems that perform these methods and computer-readable media containing instructions that, when executed on data processing systems, cause the systems to perform these methods.

[0085] The description and drawings are for illustrative purposes and are not to be interpreted as limiting. Numerous specific details are described in order to provide a thorough understanding. However, in certain instances, well-known or conventional details are not described in order not to obscure the description. References to one or more embodiments in the present disclosure are not necessarily references to the same embodiment; and such references mean at least one.

[0086] Reference in this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The uses of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described that may be shown by some embodiments and not others. Similarly, various requirements are described that may be requirements for some embodiments but not for other embodiments.

[0087] In this specification, for ease of description, various functions and acts may be described as being performed or caused by software code. However, those skilled in the art will recognize that such terms mean that the functions result from the execution of the code by one or more processors, such as a microprocessor, an application-specific integrated circuit (ASIC), a graphics processor, or a field-programmable gate array (FPGA). Alternatively, or in combination, the functions and acts may be implemented using special-purpose circuitry (e.g., logic circuitry) with or without software instructions. Embodiments may be implemented using hard-wired circuitry without software instructions or in combination with software instructions.Thus, the techniques are not limited to any particular combination of hardware circuits and software, nor to any source of the instructions executed by the computing device.

[0088] While some embodiments may be implemented in fully functional computers and computer systems, various embodiments may be distributed as a computer product in a variety of forms and may be used independent of the particular type of machine or computer-readable media used to actually implement the distribution.

[0089] At least some disclosed aspects may be embodied at least partially in software. That is, the techniques may be implemented in a computing device or other system in response to its processor, such as a microprocessor, executing instruction sequences contained in memory such as ROM, volatile RAM, non-volatile memory, cache, or a remote storage device.

[0090] Routines executed to implement the embodiments may be implemented as part of an operating system, middleware, service delivery platform, SDK (Software Development Kit) component, web services, or other specific application, component, program, object, module, or instruction sequence, referred to as "computer programs." Calling interfaces to these routines may be made available to a software development community as an API (Application Programming Interface).The computer programs typically comprise one or more instructions that are specified at various times in various storage devices in a computer and that, when read and executed by one or more processors in a computer, cause the computer to perform operations necessary to carry out elements that include the various aspects.

[0091] A machine-readable medium may be used to store software and data that, when executed by a computing device, causes the device to perform various methods. The executable software and executable data may be stored in various locations, including, for example, ROM, volatile RAM, non-volatile memory, and / or cache. Portions of this software and / or data may be stored in any of these storage devices. Further, the data and instructions may be obtained from centralized servers or peer-to-peer networks. Different portions of the data and instructions may be obtained from different centralized servers and / or peer-to-peer networks at different times and in different communication sessions, or in the same communication session. The data and instructions may be obtained in their entirety prior to execution of the applications.Alternatively, portions of the data and instructions can be obtained dynamically, just-in-time, when they are needed for execution. This eliminates the need for the data and instructions to be completely located on a machine-readable medium at any given time.

[0092] Examples of computer-readable media include, but are not limited to, writable and non-writable media such as volatile and non-volatile storage devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, magnetic disk storage media, and optical storage media (e.g., compact disk read-only memory - CD-ROMs, digital versatile disks - DVDs, etc.). The computer-readable media can store the instructions.

[0093] In general, a tangible or non-transitory machine-readable medium includes any mechanism that provides (e.g., stores) information in a form that can be accessed by a machine (e.g., a computer, a mobile device, a network device, a personal digital assistant, a manufacturing tool, any device with a set of one or more processors, etc.).

[0094] In various embodiments, hard-wired circuitry may be used in combination with software and firmware instructions to implement the techniques. Thus, the techniques are not limited to any particular combination of hardware circuitry and software, nor to any particular source of instructions executed by a computing device.

[0095] Various embodiments set forth herein may be implemented using a wide variety of different types of computing devices. As used herein, examples of a "computing device" include, but are not limited to, a server, a centralized computing platform, a system of multiple computer processors and / or components, a mobile device, a user terminal, a vehicle, a personal communications device, a portable digital device, an electronic kiosk, a general-purpose computer, an electronic document reader, a tablet, a laptop computer, a smartphone, a digital camera, a household appliance, a television, or a digital music player. Other examples of computing devices include devices that are part of the so-called "Internet of Things" (IOT).Such "things" may occasionally interact with their owners or administrators, who may monitor the things or change the settings of those things. In some cases, such owners or administrators play the role of users with respect to the "thing" devices. In some examples, a user's primary mobile device (e.g., an Apple iPhone) may be an administrator server with respect to a paired "thing" device worn by the user (e.g., an Apple Watch).

[0096] In some embodiments, the computing device may be a computer or a host system, implemented, for example, as a desktop computer, laptop computer, network server, mobile device, or other computing device that includes memory and a processing device. The host system may include or be coupled to a storage subsystem such that the host system can read data from or write data to the storage subsystem. The host system may be coupled to the storage subsystem via a physical host interface. In general, the host system may access multiple storage subsystems via a same communication link, multiple separate communication links, and / or a combination of communication links.

[0097] In some embodiments, the computing device is a system including one or more processing devices. Examples of the processing device may include a microcontroller, a central processing unit (CPU), a special-purpose logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), a system on a chip (SoC), or another suitable processor.

Claims

[1] Device comprising: a memory array (102, 202), the memory array (102, 202) comprising a plurality of addressable memory cells; a temperature sensor (110, 210) positioned at a first location relative to the memory array (102, 202), the temperature sensor (110, 210) configured to record an average temperature of the memory array (102, 202); and a controller (108, 208), the controller (108, 208) positioned at a second location relative to the memory array (102, 202), the controller (108, 208) configured to: Receiving (302, 402A, 402B) an operation from a host processor (218), the operation containing data and accessing one or more of the memory cells of the memory array, Determine whether the operation is a critical operation or a non-critical operation based on one or more of the following characteristics: an identifier contained in the process, an address of the data of the process or a data format of the process, if the operation is identified as a non-critical operation, processing (406A, 406B) the operation in the usual manner, and if the operation is identified as a critical operation, retrieving (304) a temperature value of the memory array (102, 202) from the temperature sensor (110, 210) and conditionally processing (306) the critical operation based on the temperature value. [2] The apparatus of claim 1, wherein the critical operation comprises a critical read operation, the critical read operation including an address. [3] The apparatus of claim 2, wherein the controller (108, 208) is further configured to: querying a critical access table (212) using the address, wherein the query returns a plurality of addresses; Reading (408B) temperature data from the plurality of addresses; and Processing the critical read based on the temperature data and the temperature value returned by the temperature sensor (110, 210). [4] The apparatus of any preceding claim, wherein processing the critical read operation comprises performing (410B) a majority vote function on the temperature data, the majority vote function returning a selected temperature value from the temperature data. [5] The apparatus of claim 4, wherein processing the critical read operation comprises determining (412B) that the temperature value is within a preconfigured distance from the selected temperature value, and reading (414B) data at the address included in the critical read operation. [6] The apparatus of claim 5, wherein processing the critical read comprises determining (412B) that the temperature value is not within a preconfigured distance from the selected temperature value and returning (416B) an error. [7] Apparatus according to any preceding claim, wherein the critical operation comprises a critical write operation. [8] The apparatus of claim 7, wherein conditional processing of the critical operation comprises writing the temperature value to a plurality of locations in the memory array (102, 202). [9] The apparatus of claim 8, wherein writing (414A) the temperature value at a plurality of locations in the memory array (102, 202) comprises writing the temperature value at a plurality of single-level cell (SLC) locations in the memory array (102, 202). [10] Procedure comprising: Receiving (302, 402A, 402B) an operation from a host processor (218), the operation containing data and accessing a memory array (102, 202); Determine whether the operation is a critical operation or a non-critical operation based on one or more of the following characteristics: a label contained in the operation, an address of the operation's data, or a data format of the operation, if the operation is identified as a non-critical operation, processing (406A, 406B) the operation in the usual manner; and if the operation is identified as a critical operation, retrieving (304) a temperature value of the memory array (102, 202) from the temperature sensor (110, 210) and conditionally processing (306) the critical operation based on the temperature value. [11] The method of claim 10, wherein the critical operation comprises a critical read operation, the critical read operation including an address. [12] The method of claim 11, further comprising: querying a critical access table (212) using the address, wherein the query returns a plurality of addresses; Reading (408B) temperature data from the plurality of addresses; and Processing the critical read based on the temperature data and the temperature value returned by the temperature sensor (110, 210). [13] The method of claim 12, wherein processing the critical read comprises performing (410B) a majority vote function on the temperature data, the majority vote function returning a selected temperature value from the temperature data. [14] The method of claim 13, wherein processing the critical read operation comprises determining (412B) that the temperature value is within a preconfigured distance from the selected temperature value, and reading (414B) data at the address included in the critical read operation. [15] The method of claim 14, wherein processing the critical read comprises determining (412B) that the temperature value is not within a preconfigured distance from the selected temperature value and returning (416B) an error. [16] A method according to any one of the preceding claims 10 to 15, wherein the critical operation comprises a critical write operation. [17] The method of claim 16, wherein conditionally processing the critical operation comprises writing (414A) the temperature value to a plurality of locations in the memory array (102, 202). [18] The method of claim 17, wherein writing (414A) the temperature value at a plurality of locations in the memory array (102, 202) comprises writing the temperature value at a plurality of single-level cell (SLC) locations in the memory array (102, 202). [19] The method of any one of the preceding claims 16 to 18, wherein conditionally processing the critical operation comprises writing (414A) the temperature value to a critical access table (212), the critical access storing a mapping of data addresses to locations in the memory array (102, 202). [20] A non-transitory computer-readable storage medium for tangibly storing computer program instructions executable by a computer processor, the computer program instructions defining the steps of the method of any one of claims 10 to 19.

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