Structure for a laterally diffused metal-oxide-semiconductor device and method for forming such a structure
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- GLOBALFOUNDRIES SINGAPORE PTE LTD
- Filing Date
- 2022-07-12
- Publication Date
- 2026-07-30
AI Technical Summary
Existing laterally diffused metal-oxide-semiconductor (LDMOS) devices face issues with high specific on-resistance and current crowding at the corners of the field oxide layer, which affect their ability to handle high voltages efficiently.
A structure for LDMOS devices is designed with a comb-shaped hard mask pattern and self-aligned dielectric buffer layers to reduce current crowding, featuring varying thicknesses in the dielectric buffer layers to optimize electrical properties and maintain high breakdown voltage.
The solution reduces specific on-resistance and current crowding, enhancing the device's ability to handle high voltages while maintaining a high breakdown voltage, thus improving the performance and versatility of LDMOS devices.
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Abstract
Description
background
[0001] The invention relates generally to semiconductor devices and the fabrication of integrated circuits and in particular to structures for a laterally diffused metal-oxide semiconductor device and methods for fabricating a structure for a laterally diffused metal-oxide semiconductor device.
[0002] Integrated high-voltage circuits, such as those used in microwave / RF power amplifiers, typically require specialized circuit technology capable of withstanding higher voltages. LDMOS (Laterally-Diffused Metal-Oxide-Semiconductor) devices, also known as EDMOS (Extended-Drain Metal-Oxide-Semiconductor) devices, are designed to handle such higher voltages by incorporating additional transistor characteristics, such as a drift well that provides an extended drain and enhances the ability to handle higher voltages. Laterally diffused metal-oxide-semiconductor devices can be used, for example, for switching high-voltage power supplies.
[0003] Reduced surface field (RESURF) techniques can be used to fabricate laterally diffused metal-oxide-semiconductor devices with low on-resistance and high breakdown voltage. Laterally diffused metal-oxide-semiconductor devices can incorporate a thick field oxide layer embedded in the drift well between the source and drain. The field oxide layer is designed to have a thickness corresponding to the intended operating voltage. The thickness of the field oxide layer is increased according to the intended operating voltage. In the drift well below the field oxide layer, a cover layer can be formed as an oppositely doped region to reduce the on-resistance while maintaining a high breakdown voltage.The current flowing between source and drain must flow around the field oxide layer and the cover layer in the drift trough, which can lead to current compression near the corners of the field oxide layer and the cover layer.
[0004] Improved structures for a laterally diffused metal-oxide semiconductor device and methods for fabricating a structure for a laterally diffused metal-oxide semiconductor device are required. Summary
[0005] In one embodiment, a structure for a laterally diffused metal-oxide semiconductor device is provided. The structure comprises a semiconductor substrate, a drift well in the semiconductor substrate, a source region and a drain region in the semiconductor substrate, a dielectric gate layer on the semiconductor substrate, and a dielectric buffer layer on the semiconductor substrate above the drift well. The dielectric buffer layer comprises a first side edge at the drain region, a second side edge at the dielectric gate layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge to the first side edge. The first section has a first thickness, and each of the second sections has a second thickness that is less than the first thickness.The structure further includes a gate electrode positioned laterally between the source region and the drain region. The gate electrode comprises a first section that overlaps the dielectric buffer layer and a second section that also overlaps the dielectric gate layer.
[0006] In one embodiment, a method for fabricating a structure for a laterally diffused metal-oxide semiconductor device is provided. The method comprises forming a drift well in a semiconductor substrate, forming a source region and a drain region in the semiconductor substrate, forming a dielectric gate layer on the semiconductor substrate, and forming a dielectric buffer layer on the semiconductor substrate above the drift well. The dielectric buffer layer comprises a first side edge at the drain region, a second side edge at the dielectric gate layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge to the first side edge. The first section has a first thickness, and each of the second sections has a second thickness that is less than the first thickness.The method further comprises forming a gate electrode positioned laterally between the source region and the drain region. The gate electrode includes a first section that overlaps the dielectric buffer layer and a second section that also overlaps the dielectric gate layer. List of characters
[0007] The accompanying drawings, which form part of this description, show various embodiments of the invention and, together with the general description of the invention above and the detailed description of the embodiments below, serve to describe these embodiments. The same reference numerals are used in the drawings to denote the same features in the different views. Fig. Figure 1 is a cross-sectional view of a structure in a first manufacturing phase of a process according to embodiments of the invention. Fig. 2 is a top view of the structure in a Fig. 1. The following manufacturing stage. Fig. 3 is a cross-sectional view, generally along line 3-3 in Fig. 2 proceeds. Fig. 3A is a cross-sectional view, generally along the line 3A-3A in Fig. 2 proceeds. Fig. 3B is a cross-sectional view, generally along the line 3B-3B in Fig. 2 proceeds. Fig. 4 is a top view of the structure in a Fig. 2 following manufacturing stage. Fig. 5 is a cross-sectional view, generally along line 5-5 in Fig. 4 proceeds. Fig. 5A is a cross-sectional view, generally along the line 5A-5A in Fig. 4 proceeds. Fig. 5B is a cross-sectional view, generally along the line 5B-5B in Fig. 4 proceeds. Fig. 6, Fig. 6A, Fig. 6B are cross-sectional views of the structure in a Fig. 5, Fig. 5A, Fig. 5B following manufacturing phase. Fig. 7, Fig. 7A, Fig. 7B are cross-sectional views of the structure in a [context missing] Fig. 6, Fig. 6A, Fig. 6B following manufacturing phase. Fig. Figure 8 is a top view of a structure according to alternative embodiments of the invention. Fig. Figure 9 is a top view of the structure in a diagram on Fig. 8 following manufacturing phase. Fig. 10 is a cross-sectional view, generally along the line 10-10 in Fig. 9 runs. Fig. 10A is a cross-sectional view, generally along the line 10A-10A in Fig. 9 runs. Fig. 10B is a cross-sectional view, generally along the line 10B-10B in Fig. 9 runs. Detailed description
[0008] With reference to Fig. 1 and according to embodiments of the invention, a structure 10 for a laterally diffused metal-oxide-semiconductor device comprises a substrate 12 and a shallow trench insulation region 14 arranged in the substrate 12 to surround an active device region. The substrate 12 can be formed from a semiconductor material, e.g., single-crystal silicon. In one embodiment, the substrate 12 can be lightly doped so that it exhibits p-type conductivity. The substrate 12 can have an epitaxial layer of a semiconductor material that is epitaxially grown to a certain thickness near the top surface.The shallow trench insulation area 14 can be formed by structuring shallow trenches in the substrate 12 using lithography and etching processes, depositing a dielectric material to fill the shallow trenches, and leveling and / or deepening the deposited dielectric material. The dielectric material of the shallow trench insulation area 14 can include silicon dioxide deposited by chemical vapor deposition.
[0009] A buried insulating layer 16 is formed over a specific depth range below the top surface of the substrate 12. The buried insulating layer 16 can be formed in the substrate 12 by planar ion implantation or, alternatively, by in-situ doping during the epitaxial growth of the semiconductor material of the epitaxial layer contained in the substrate 12. The buried insulating layer 16 is doped to exhibit a conductivity type opposite to that of the substrate 12. In an embodiment where the substrate 12 is p-type doped, the buried insulating layer 16 can comprise and be heavily doped with an n-type dopant, such as arsenic or phosphorus.
[0010] A deep trench insulation region 18 is formed in a deep trench extending through the shallow trench insulation region 14 and the substrate 12 between the shallow trench insulation region 14 and the buried insulation layer 16 to a shallow depth within the substrate 12 below the buried insulation layer 16. Similar to the shallow trench insulation region 14, the deep trench insulation region 18 can surround the active device area. The deep trench insulation region 18 can interact with the buried insulation layer 16 to electrically isolate the active device area from the rest of the substrate 12. The deep trench insulation region 18 can include a dielectric collar (e.g., silicon dioxide) lining the sidewalls of the deep trench and an electrically conductive core (e.g., doped polysilicon or a metal).The electrically conductive core is connected to the substrate 12 below the buried insulation layer 16 and is insulated from the substrate 12 above the buried insulation layer 16 by the dielectric collar.
[0011] A well 20 is formed above a certain depth above the buried insulating layer 16. The well 20 can be formed by introducing a dopant, e.g., by planar ion implantation under specific implantation conditions, into the substrate 12. The implantation conditions (e.g., ion types, dose, kinetic energy) can be selected to match the electrical and physical properties of the well 20. The well 20 can be formed from a semiconductor material of the substrate 12 that is doped to have a conductivity type opposite to that of the substrate 12 and the same conductivity type as the buried insulating layer 16, but with a lower dopant concentration. In an embodiment where the substrate 12 is p-doped, the well 20 can comprise a semiconductor material doped with an n-type dopant (e.g.,The well 20 is doped with phosphorus and / or arsenic to ensure n-type conductivity. It can form a high-voltage well in the finished component structure 10.
[0012] A drift well 21 is formed in a section of the active device area above the buried insulating layer 16 and the well 20. The drift well 21 can be formed by introducing a dopant, e.g., by ion implantation under specific implantation conditions, into the substrate 12. A structured implantation mask can be formed to define a selected area (e.g., location and horizontal dimensions) on the top surface of the substrate 12 that is exposed for implantation to form the drift well 21. The implantation mask can include a layer of a material, e.g., an organic photoresist, whose thickness and holding power are sufficient to block implantation of the masked areas. The implantation conditions (e.g., ion type, dose, kinetic energy) can be selected to match the electrical and physical properties of the drift well 21.The drift well 21 can be formed from the semiconductor material of the substrate 12, which is doped to exhibit a different conductivity type than the well 20. In an embodiment where the well 20 has n-type conductivity, the drift well 21 can comprise a semiconductor material lightly doped with a p-type dopant (e.g., boron) to achieve p-type conductivity. The drift well 21 can form a drift region for the extended drain in the finished structure 10.
[0013] With regard to the Fig. 2, Fig. 3, Fig. 3A, Fig. 3B, in which identical reference signs refer to identical features in Fig. In a subsequent manufacturing phase, a hard mask 22 is formed over the substrate 12. The hard mask 22 can have a pad layer made of a dielectric material, such as silicon nitride, and can be structured by lithography and etching processes to provide a structured shape. In this context, the hard mask 22 can be structured using a lithographically formed etch mask. The etch mask can comprise a layer of a photosensitive material, such as a photoresist, which is applied by a spin coating process, pre-baked, exposed with light projected through a photomask, baked after exposure, and developed with a chemical developer to define open areas with the shapes to be formed in the hard mask 22. An etching process, e.g.,a reactive ion etching process is used to remove sections exposed through the openings in the etching mask, which is subsequently stripped to form openings 28 in the hard mask 22.
[0014] Each opening 28 in the hard mask 22 has a series of notches 24 arranged along one side edge. The notches 24 alternate along the side edge of each opening 28 with sections of the hard mask 22 that define projections 26. Each projection 26 is arranged as a finger between an adjacent pair of notches 24, thus defining a comb shape. The other side edges of each opening 28 in the hard mask 22 are not notched and may therefore be smooth. The notches 24 and the projections 26 have dimensions selected by design rules used as input for the lithography process. Specifically, the notches 24 have a width W1, the projections 26 have a width W2, which defines a distance between adjacent notches 24, and the notches 24 have a depth or length L1.The numerical values of width W1, width W2 and length L1 can be used to determine the thickness variation of a subsequently formed oxide layer.
[0015] In one embodiment, the distribution of the notches 24 and projections 26 along the side edge of each opening 28 can be uniform. In the representative embodiment, the notches 24 and the projections 26 can be rectangular. In an alternative embodiment, the notches 24 and the projections 26 can be trapezoidal. In another alternative embodiment, the notches 24 can be pointed and the projections 26 can be trapezoidal.
[0016] Doped regions 34 can be formed in the drift tank 21 as cover layers, e.g., by ion implantation, with the hard mask 22 serving as the implantation mask. Consequently, the doped regions 34 are formed within the openings 28 in the hard mask 22, which define the implanted regions of the substrate 12. The hard mask 22 blocks the implantation of regions of the substrate 12 surrounding the openings 28. The implantation conditions (e.g., ion type, dose, kinetic energy) can be selected to match the electrical and physical properties of the doped regions 34. The doped regions 34 are doped to exhibit a conductivity type opposite to that of the drift tank 21. In an embodiment where the drift tank 21 contains a p-type dopant, the semiconductor material of the doped regions 34 can contain an n-type dopant (e.g.,arsenic and / or phosphorus) which provides n-type electrical conductivity.
[0017] The implanted area of each doped region 34 corresponds to the open area of the corresponding opening 28 and exhibits variations in shape that are identical to the variations in shape caused by the notches 24 and projections 26. In this respect, the doped regions 34 extending into the substrate 12 below the notches 24 of the openings 28 have a length L2, and the doped regions 34 at the locations of the projections 26 have a length L3, which is less than the length L2.
[0018] With regard to the Fig. 4, Fig. 5, Fig. 5A, Fig. 5B, in which the same reference signs refer to the same features in the Fig. 2, Fig. 3, Fig. 3A, Fig. 3B, and in a subsequent manufacturing phase, dielectric buffer layers 30 are formed by utilizing the openings 28 in the hard mask 22, and the hard mask 22 is removed after the formation of the dielectric buffer layers 30. In one embodiment, the dielectric buffer layers 30 can be formed from silicon dioxide. In another embodiment, the dielectric buffer layers 30 can be formed as a field oxide by subjecting the substrate 12 to thermal oxidation in an oxidizing atmosphere (e.g., an oxygen-containing atmosphere) using a local oxidation process for silicon (LOCOS). The oxidizing species (e.g.,Oxygen is prevented from diffusing through the thickness of the hard mask 22 during thermal oxidation, and the openings 28 in the hard mask 22 define exposed or unprotected areas that are thermally oxidized to allow the dielectric buffer layers 30 to grow. Each dielectric buffer layer 30 can grow below the projections 26 in the hard mask 22 and adjacent to the other edges of the respective openings 28 due to the lateral diffusion of the oxidizing species in the substrate 12 below the hard mask 22. In particular, the oxidizing species diffuses laterally into the substrate 12 from the notches 24 below each projection 26 from each of its side edges. The oxidizing species reacts with the semiconductor material of the substrate 12 below the projections 26.
[0019] Each dielectric buffer layer 30 comprises a side edge 32, a side edge 33 opposite side edge 32, a section 60 with thickness T1, sections 62 with thickness T2, and sections 64 forming a thickness transition between section 60 and sections 62. The sections 60 of the dielectric buffer layers 30 can form within the openings 28 in the hard mask 22, including within the spaces defined by the notches 24. The sections 62 of the dielectric buffer layers 30 can form below the projections 26 of the hard mask 22. The shape and dimensions of sections 60 and 62 of each dielectric buffer layer 30 are determined, at least in part, by the shape and dimensions of the openings 24 and the projections 26.
[0020] The thickness T2 of sections 62 is less than the thickness T1 of section 60. In one embodiment, the thickness T1 of section 60 of each dielectric buffer layer 30 can be uniform. In one embodiment, the thickness T2 of sections 62 of each dielectric buffer layer 30 can be uniform. In one embodiment, the thickness T1 of section 60 of each dielectric buffer layer 30 can be substantially uniform. In one embodiment, the thickness T2 of sections 62 of each dielectric buffer layer 30 can be substantially uniform.
[0021] The sections 64 of each dielectric buffer layer 30 taper over a range of intermediate thicknesses from thickness T1 at the intersection with section 60 to thickness T2 at the intersection with each section 62. The sections 64 are formed adjacent to the side edges of the projections 26 of the hard mask 22. Each section 64 extends over several sides of each section 62.
[0022] Sections 60 and 62 of each dielectric buffer layer 30 also include peripheral sections 66, which represent bird beaks where the dielectric material tapers to zero thickness. The side edges 32 and 33 of each dielectric buffer layer 30 are defined at the corners between section 60 and the peripheral sections 66.
[0023] The doped regions 34 are self-aligned with the section 60 of each dielectric buffer layer 30, as they are formed with the same structured hard mask 22. That is, the doped regions 34 are positioned only below the sections 60 of the dielectric buffer layers 30, forming a comb shape. In one embodiment, the doped regions 34 can be coextensive with the sections 60 of the dielectric buffer layers 30, i.e., have the same extent (i.e., share a common boundary with them). The doped regions 34 are not located below the sections 62 of the dielectric buffer layers 30. Instead, sections of the drift trough 21 are located below the sections 62 of the dielectric buffer layers 30. In one embodiment, the sections of the drift trough 21 can extend over the sections 62 of the dielectric buffer layers 30.
[0024] With regard to the Fig. 6, Fig. 6A, Fig. 6B, in which the same reference signs refer to the same features in the Fig. 5, Fig. 5A, Fig. 5B is obtained, and in a subsequent manufacturing phase, wells 36, 38, and 40 are formed in the active region of substrate 12. Wells 38 and 40 are formed from the semiconductor material of substrate 12, which is doped to exhibit a specific conductivity type. Well 36 is formed from the semiconductor material of substrate 12, which is doped to exhibit a different conductivity type than wells 38 and 40. Well 36 can be formed by introducing a dopant into substrate 12, for example, by ion implantation under specific implantation conditions. Wells 38 and 40 can be formed by introducing a different dopant of the opposite conductivity type into substrate 12, for example, by ion implantation.A structured implantation mask can be formed to define one or more selected areas on the top surface of the substrate 12 that are exposed for each individual implantation. The implantation masks cover different areas on the top surface of the substrate 12 to determine, at least partially, the location and horizontal dimensions of the troughs 36, 38, 40. Each implantation mask can comprise a layer of a material, e.g., an organic photoresist, which is applied and structured to cover and mask the different areas on the top surface of the substrate 12. Each implantation mask has sufficient thickness and holding force to block the implantation of the masked areas.
[0025] The implantation conditions (e.g., ion species, dose, kinetic energy) can be selected to match the electrical and physical properties of the well 36. A separate set of implantation conditions (e.g., ion species, dose, kinetic energy) can be selected to adjust the electrical and physical properties of the wells 38. A separate set of implantation conditions (e.g., ion species, dose, kinetic energy) can be selected to adjust the electrical and physical properties of the wells 40. The wells 40 can surround the wells 38 and have a lower dopant concentration than the wells 38. In an embodiment where the well 20 has n-type conductivity and the drift well 21 has p-type conductivity, the well 36 can comprise a semiconductor material doped with a p-type dopant (e.g.,boron) is doped to achieve p-type conductivity, and wells 38, 40 may contain semiconductor material doped with different concentrations of an n-type dopant (e.g. phosphorus and / or arsenic) to achieve n-type conductivity.
[0026] With reference to Fig. 7, Fig. 7A, Fig. 7B, in which the same reference signs refer to the same features in Fig. 6, Fig. 6A, Fig. Referring to substrate 6B, gate electrodes 42 and dielectric gate layers 44, defining a gate pair, are formed in a subsequent fabrication phase using a split-gate arrangement. Each dielectric gate layer 44 is formed from a dielectric material, such as silicon dioxide, which is produced by thermal oxidation of the semiconductor material of the substrate 12. The dielectric gate layers 44 have a thickness T3 that is less than the thickness of section 60 of the dielectric buffer layer 30 and less than the thickness of sections 62 of the dielectric buffer layer 30. Each gate electrode 42 is formed from a conductor, for example, doped polysilicon. The gate electrodes 42 and the dielectric gate layers 44 can be formed by structuring layers of their respective materials using lithography and etching techniques.
[0027] In wells 36 and 38, source regions 50, a drain region 52, and body contact regions 54 are formed for the laterally diffused metal-oxide-semiconductor device. The source regions 50 and the drain region 52 can be doped to exhibit a different conductivity type than the body contact regions 54. The source regions 50, located in wells 38, can be doped to exhibit a conductivity type opposite to that of wells 38 and can be heavily doped. The drain region 52, located in well 36, can be doped to exhibit the same conductivity type as well 36, but with a higher dopant concentration (e.g., heavily doped). The body contact areas 54, which are arranged in the tubs 38 and can be adjacent to the source areas 50, can be doped to have the same conductivity type as the tubs 38.In an embodiment in which the basin 36 has a p-type conductivity and the basins 38 have an n-type conductivity, the source regions 50 and the drain region 52 can be doped (e.g., heavily doped) with a p-type dopant (e.g., boron) to achieve a p-type conductivity, and the body contact regions 54 can be doped (e.g., heavily doped) with an n-type dopant (e.g., phosphorus and / or arsenic) to achieve an n-type conductivity.
[0028] The source regions 50 and the drain region 52 can be formed by selective implantation of ions, e.g., ions with the p-type dopant, using an implantation mask that defines the intended locations for the source regions 50 and the drain region 52 in the substrate 12. The body contact regions 54 can be formed by selective implantation of ions, e.g., ions with the n-type dopant, using a different implantation mask that defines the intended locations for the body contact regions 54 in the substrate 12.
[0029] Each dielectric gate layer 44 is located adjacent to the side edge 32 of one of the dielectric buffer layers 30 and, in one embodiment, abuts the side edge 32 of the adjacent dielectric buffer layer 30. Each gate electrode 42 comprises a section that overlaps the dielectric gate layer 44 and another section that overlaps the dielectric buffer layer 30. The section of each gate electrode 42 that overlaps the dielectric buffer layer 30 defines a field plate. In one embodiment, each gate electrode 42 completely overlaps the sections 62 of the dielectric buffer layer 30. The section 60 of each dielectric buffer layer 30 extends from the side edge 32 adjacent to the dielectric gate layer 44 to the side edge 33.The sections 62 of each dielectric buffer layer 30 extend from the side edge 32 towards the side edge 33 and therefore only partially extend over the dielectric buffer layer 30. The side edge 33 of each dielectric buffer layer 30 borders the drain region 52.
[0030] Each grouping of dielectric buffer layer 30, gate electrode 42, and dielectric gate layers 44 is arranged laterally on the substrate 12 between the drain region 52 and one of the source regions 50. The sections 62 of each dielectric buffer layer 30, which have a smaller thickness compared to the section 60, border one of the source regions 50 and are arranged away from the drain region 52. The sections 62 of each dielectric buffer layer 30 are separated from the drain region 52 by the section 60.
[0031] The middle-of-line (MOL) processing and the back-end-of-line (BEOL) processing follow, which includes the formation of a connection structure coupled to the structure 10. In particular, one or more contacts are formed that are coupled to each gate electrode 42, one or more contacts are formed that are coupled to each source region 50, one or more contacts are formed that are coupled to the drain region 52, and one or more contacts are formed that are coupled to each body contact region 54.
[0032] Structure 10 can exhibit improved performance and versatility. The doped regions 34, which are not present or are absent under sections 62 of the dielectric buffer layer 30, are slightly displaced from the corners of sections 62 of the dielectric buffer layer 30 toward the drain region 52. Displacing these corners away from the source regions 50 can help reduce current accumulation at the corners. By adjusting the structuring of the hard mask 22 to match the formation of the dielectric buffer layer 30, laterally diffused metal-oxide-semiconductor devices can be formed that exhibit different on-resistances but nominally the same footprint.
[0033] With reference to Fig. 8, in which the same reference signs refer to the same features in Fig. 2, and according to alternative embodiments of the invention, the structuring of the hard mask 22 can be modified to provide multiple openings 56, which are formed by strips 58 made of the material of the hard mask 22 instead of notches 24 ( Fig. 2) are separated.
[0034] In alternative embodiments, the strips 58 can be widened (i.e., trapezoidally expanded) and the openings 56 can be simultaneously narrowed (i.e., tapered) in the vicinity of the subsequently formed source areas 50.
[0035] With regard to the Fig. 9, Fig. 10, Fig. 10A, Fig. 10B and in one on Fig. In the following manufacturing phase, the doped regions 34 are formed in the substrate 12 at the locations of the openings 56. The strips 58 block implantation, so that the doped regions 34 are not present in the substrate 12 below the strips 58. The dielectric buffer layers 30 can be produced by thermal oxidation using the hard mask 22 ( Fig. 9) are formed and the hard mask 22 can be removed after the formation of the dielectric buffer layers 30.
[0036] Each dielectric buffer layer 30 comprises sections 70 with a thickness T3, sections 72 with a thickness T4, and sections 74 that form a transition between section 70 and sections 72. The sections 70 of the dielectric buffer layers 30 can form within the openings 56. The sections 72 of the dielectric buffer layers 30 can form beneath the strips 58. The thickness T4 of the sections 72 is less than the thickness T3 of the sections 70. The shape and dimensions of sections 70 and 72 of each dielectric buffer layer 30 are at least partially determined by the shape and dimensions of the openings 56 and the strips 58. In one embodiment, the thickness T3 of the sections 70 of each dielectric buffer layer 30 can be uniform. In another embodiment, the thickness T4 of the sections 72 of each dielectric buffer layer 30 can be uniform.In one embodiment, the thickness T3 of sections 70 of each dielectric buffer layer 30 can be substantially uniform. In another embodiment, the thickness T4 of sections 72 of each dielectric buffer layer 30 can be substantially uniform.
[0037] Sections 70 and 72 are arranged side by side and alternate along the width of each dielectric buffer layer 30. Each section 72 is positioned laterally between an adjacent pair of sections 70. The sections 74 of each dielectric buffer layer 30 taper over a range of intermediate thicknesses from thickness T3 at the intersections with sections 70 to thickness T4 at the intersection with sections 72. The sections 70 and 72 of each dielectric buffer layer 30 also have peripheral sections 76, representing bird beaks, where the dielectric material tapers to zero thickness.
[0038] The gate electrode 42 only partially overlaps the sections 72 of the dielectric buffer layer 30, which extend from side edge 32 to side edge 33 of the dielectric buffer layer 30. The doped regions 34 are located only below the sections 70 of the dielectric buffer layer 30. In one embodiment, the doped regions 34 can be coextensive with the sections 70 of the dielectric buffer layers 30. The doped regions 34 are not located below the sections 72 of the dielectric buffer layers 30. Instead, parts of the drift trough 21 are located below the sections 72 of the dielectric buffer layers 30. In one embodiment, the sections of the drift trough 21 can extend over the sections 72 of the dielectric buffer layers 30.
[0039] The process will continue to complete structure 10 as previously described.
[0040] The processes described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (e.g., a single wafer containing multiple unpackaged chips), as bare chips, or in packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product can be any product that incorporates integrated circuit chips, such as computer products with a central processing unit or smartphones.
[0041] References in this document to terms modified by imprecise terms such as "approximately," "about," and "essentially" are not to be limited to the exact value. The imprecise value may correspond to the accuracy of an instrument used to measure the value and, unless otherwise specified depending on the accuracy of the instrument, may be + / - 10% of the stated value(s).
[0042] References to terms such as "vertical," "horizontal," etc., are used here only as examples and not to restrict the scope of the discussion, in order to establish a frame of reference. The term "horizontal" as used here is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal plane just defined. The term "lateral" refers to a direction within the horizontal plane.
[0043] A feature that is "connected" or "coupled" to another feature can be directly connected or coupled to the other feature, or one or more intervening features can be present. A feature can be "directly connected" or "directly coupled" to another feature if no intervening features are present. A feature can be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature that is "on" or "in contact" with another feature can be directly on or in direct contact with the other feature, or one or more intervening features can be present. A feature can be "directly on" or in "direct contact" with another feature if no intervening features are present.A feature can be "indirectly on" another feature or in "indirect contact" with it if at least one intervening feature is present. Different features can "overlap" if one feature extends over another and covers part of it.
[0044] The descriptions of the various embodiments of the present invention serve for illustrative purposes and are intended to be either exhaustive or limited to the embodiments described. Many modifications and alterations are apparent to those skilled in the art without altering the scope and essence of the described embodiments. The terminology used herein has been chosen to explain, as clearly as possible, the principles of the embodiments, their practical application, or the technical improvements compared to technologies available on the market, or to enable those other than those skilled in the art to understand the embodiments described herein.
Claims
[1] Structure for a side-diffused metal-oxide-semiconductor device, the structure comprising a semiconductor substrate; a drift well in the semiconductor substrate; a source region and a drain region in the semiconductor substrate; a dielectric gate layer on the semiconductor substrate; a dielectric buffer layer on the semiconductor substrate over the drift well, the dielectric buffer layer comprising a first side edge at the drain region, a second side edge at the gate dielectric layer, a first portion extending from the second side edge to the first side edge, and a plurality of second portions extending from the second side edge to the first side edge, the first portion having a first thickness and each of the second portions having a second thickness less than the first thickness; and a gate electrode laterally disposed between the source region and the drain region, the gate electrode having a first portion overlapping the buffer dielectric layer and a second portion overlapping the gate dielectric layer. [2] The structure of claim 1, wherein the gate electrode completely overlaps with the second portions of the dielectric buffer layer. [3] The structure of claim 1, wherein the gate electrode partially overlaps with the second portions of the dielectric buffer layer. [4] The structure of claim 1, wherein the second portions extend from the second side edge to the first side edge. [5] The structure of claim 4, wherein the first portion of the dielectric buffer layer is formed in a plurality of first portions of the dielectric buffer layer having the first thickness, and each of the second portions is laterally disposed between an adjacent pair of the first portions. [6] The structure of claim 1, wherein each of the second portions is connected to the first portion of the dielectric buffer layer by a third portion, and the third portion has a third thickness tapered from the first thickness to the second thickness. [7] The structure of claim 1, wherein the gate dielectric layer has a third thickness that is less than the first thickness and less than the second thickness. [8] The structure of claim 1, wherein the first portion separates the second portions from the drain region. [9] The structure of claim 1, further comprising: a doped region in the drift well, the doped region being arranged under the first portion of the dielectric buffer layer, wherein the drift well is doped to have a first conductivity type, and the doped region is doped to have a second conductivity type different from the first conductivity type. [10] The structure of claim 9, wherein the doped region is coextensive with the first portion of the dielectric buffer layer. [11] The structure of claim 9, wherein the drift well is coextensive with the second portion of the dielectric buffer layer. [12] The structure of claim 9, wherein the doped region is not present below the second portions of the dielectric buffer layer. [13] The structure of claim 1, wherein the second side edge of the buffer dielectric layer is adjacent to the gate dielectric layer. [14] The structure of claim 13, wherein the gate dielectric layer is disposed between the second side edge of the buffer dielectric layer and the source region. [15] A method of forming a structure for a laterally diffused metal-oxide-semiconductor device, the method comprising: forming a drift well in a semiconductor substrate; forming a source region and a drain region in the semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a dielectric buffer layer on the semiconductor substrate over the drift well, the dielectric buffer layer comprising a first side edge at the drain region, a second side edge at the gate dielectric layer, a first portion extending from the second side edge to the first side edge, and a plurality of second portions extending from the second side edge to the first side edge, the first portion having a first thickness and each of the second portions having a second thickness less than the first thickness; and forming a gate electrode laterally disposed between the source region and the drain region, the gate electrode having a first portion overlapping the buffer dielectric layer and a second portion overlapping the gate dielectric layer. [16] The method of claim 15, wherein forming the dielectric buffer layer disposed on the semiconductor substrate over the drift well comprises: forming a hard mask on the semiconductor substrate having an opening configured to provide the first portion and the second portion, wherein the dielectric buffer layer is formed by a thermal oxidation process with the hard mask on the semiconductor substrate. [17] The method of claim 16, wherein the hard mask includes a plurality of notches alternating with a plurality of protrusions along a side edge, and the notches and protrusions have dimensions selected to form the second thickness of the second portions. [18] The method of claim 16, further comprising: forming a doped region in the drift well disposed beneath the first portion of the dielectric buffer layer, wherein the drift well is doped to have a first conductivity type, the doped region is doped to have a second conductivity type different from the first conductivity type, the doped region is coextensive with the first portion of the dielectric buffer layer, and the drift well is coextensive with the second portions of the dielectric buffer layer. [19] The structure of claim 18, wherein the doped region is not present below the second portions of the dielectric buffer layer. [20] The method of claim 15, wherein the gate electrode completely overlaps with the second portions of the dielectric buffer layer.