Dual-path subcapacitor power converter

Abstract

A power converter (100) configured to convert electrical power at an input voltage (VIN) at an input of the power converter (100) into electrical power at an output voltage (VOUT) at an output of the power converter (100); wherein the power converter (100) has, - a first upper capacitor (C1A) and a first lower capacitor (C1B) coupled to each other via a first central node; - a second upper capacitor (C2A) and a second lower capacitor (C2B) that are coupled to each other via a second central node; - an inductor (L1, L2); - a set of circuit breakers (S1-S15); and - a control unit (120) configured to control the set of circuit breakers (S1-S15) such that during an operating cycle the power transformer (100) is operated in a first main state (D1) and in a second main state (D2) in a mutually exclusive manner; wherein in the first main state (D1) the power transformer (100) - a first current path (101) from ground through the first lower capacitor (C1B), through the inductor (L1, L2) to the output; and - a second current path (102) with - a subpath from the input through the second upper capacitor (C2A), through the second lower capacitor (C2B) to the output, and - a subpath from ground through the first lower capacitor (C1B), through the first upper capacitor (C1A), through the second lower capacitor (C2B) to the output; and wherein in the second main state (D2) the power converter (100) has - a first current path (101) from ground through the second lower capacitor (C2B) through the inductor (L1, L2) to the output; and - a second current path (102) with - a subpath from the input through the first upper capacitor (C1A), through the first lower capacitor (C1B) to the output, and - a subpath from ground through the second lower capacitor (C2B), through the second upper capacitor (C2A), through the first lower capacitor (C1B) to the output.

Description

Technical area

[0001] This document relates to a DC-DC power converter, in particular a voltage regulator optimized for a conversion ratio of 3-to-1 or 4-to-1 or 2-to-1. background

[0002] For many years, the Intermediate Bus Architecture (IBA) has been widely used in data centers and telecommunications systems to convert the 48V backplane to a 12V bus (4-to-1 conversion ratio). The 4-to-1 conversion ratio can also be used in charger applications, e.g., to convert an input voltage of VIN = 16V to an output voltage of VOUT = 4V.

[0003] One way to improve the efficiency of a switched-mode power supply (SMPS) with a voltage regulator is to reduce the power loss associated with the inductor. This can be achieved by reducing the current ripple and / or the average current. In a single-phase step-down SMPS, the average inductor current is equal to the load current. The ripple current is a function of the conversion ratio (CR) and is minimized (or "zeroed") when CR = 0 or 1. "Zeroing" means that the voltage across the inductor is so small that the inductor current becomes non-linear. Non-linear inductor current is a property of resonant or quasi-resonant operation. Multilevel converters (MLCs) provide inductor ripple nulling at additional values ​​of CR.For example, a three-stage converter (3LC) has an additional ripple current zero at CR = 0.5. In other words, the 3LC essentially operates in resonant or quasi-resonant mode when CR = 0.5.

[0004] The present document concerns the technical problem of providing a power converter, in particular a voltage regulator, which enables accurate voltage regulation over a wide operating range, i.e. over a wide CR range, and which is particularly power efficient at a conversion ratio of 3-to-1 or 4-to-1 or 2-to-1.

[0005] DE 10 2016 225 795 A describes a power converter that has higher power efficiency and provides a higher maximum output current.

[0006] DE 10 2019 214 978 A1 describes a hybrid multi-level power converter with bypass by an inductive component.

[0007] DE 10 2020 213 004 A1 describes a power converter that can be operated with a small output-to-input voltage conversion ratio. Summary

[0008] According to one aspect, a power converter, in particular a voltage regulator, is configured to convert electrical power at a (DC) input voltage at an input of the power converter into electrical power at a (DC) output voltage at an output of the power converter.

[0009] The power converter includes a first upper capacitor and a first lower capacitor coupled together via a first center node, and a second upper capacitor and a second lower capacitor coupled together via a second center node. Furthermore, the power converter includes an inductor and a set of power switches. Furthermore, the power converter includes a control unit configured to control the set of power switches such that the power converter operates in a first main state and a second main state in a mutually exclusive manner during an operating cycle.

[0010] In the first main state, the power converter has a first current path from ground through the first lower capacitor, through the inductor to the output; and a second current path with a subpath from the input through the second upper capacitor, through the second lower capacitor to the output, and with a subpath from ground through the first lower capacitor, through the first upper capacitor, through the second lower capacitor to the output.

[0011] In the second main state, the power converter has a first current path from ground through the second lower capacitor, through the inductor to the output and a second current path with a subpath from the input through the first upper capacitor, through the first lower capacitor to the output and with a subpath from ground through the second lower capacitor, through the second upper capacitor, through the first lower capacitor to the output.

[0012] According to a further aspect, a corresponding method for operating a power converter is described.

[0013] It should be noted that the methods and systems, including their preferred embodiments, as set forth in this document can be used independently or in combination with the other methods and systems disclosed in this document. Furthermore, the features set forth in the context of a system are also applicable to a corresponding method. Furthermore, all aspects of the methods and systems set forth in this document can be combined in any way. In particular, the features of the claims can be combined in any way.

[0014] In this document, the term "couple" or "coupled" refers to elements that are in electrical communication with each other, either directly connected, e.g. via wires, or by other means. Short description of the characters

[0015] The invention will be explained below by way of example with reference to the accompanying drawings, in which Fig. 1a shows an exemplary voltage regulator; Fig. 1b PWM pulses for different phases or states of the voltage regulator of Fig. 1a (in the case of a relatively low duty cycle); Fig. 1b PWM pulses for different phases of the voltage regulator of Fig. 1a (in the case of a relatively high duty cycle); Fig. Figure 2a shows the two or dual current paths of a first main state (here referred to as D1); Fig. Figure 2b shows the dual current paths of a second principal state (here denoted as D2); Fig. Figure 2c shows the dual current paths of a first valley state (here denoted as DV1); Fig. Figure 2d shows the dual current paths of a second valley state (here denoted DV2); Fig. Figure 3a shows the dual current paths of a first principal state (here denoted as D1) for relatively high conversion ratios; Fig. Figure 3b shows the dual current paths of a second principal state (here denoted as D2) for relatively high conversion ratios; Fig. Figure 3c shows the dual current paths of a first peak state (here referred to as DP1) for relatively high conversion ratios; Fig. Figure 3d shows the dual current paths of a second peak state (here referred to as DP2) for relatively high conversion ratios; Fig. Figure 3e shows the dual current paths of an alternative first peak state (here referred to as DP1) for relatively high conversion ratios; Fig. Figure 3f shows the dual current paths of an alternative second peak state (here referred to as DP2) for relatively high conversion ratios; Fig. 4a to 4c show different states for operating the power converter at conversion ratios greater than 0.5; Fig. Figure 5 shows a circuit for a transition mode; Fig. 6a to 6f show different states for operating the power converter in a boost or step-up mode; Fig. 7 shows relationships between conversion ratio and duty cycle; Fig. Figure 8 shows a power converter enabling peak efficiencies at CR = 0.33 and CR = 0.5; Fig. 9a to 9f different states of the power converter of Fig. 8 show; and Fig. 10 shows a flowchart of an exemplary method for operating a voltage regulator. Detailed description

[0016] As stated above, the present document relates to providing a voltage regulator that is particularly efficient at a conversion ratio of 4-to-1 or 3-to-1.

[0017] Fig. 1a shows an exemplary voltage regulator 100. The voltage regulator 100 includes the power switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, and S11. Furthermore, the voltage regulator 100 includes "flying" capacitors C1 and C2, which are each divided into series of flying capacitors C1A, C1B, and C2A and C2B, i.e., C1 → C1A + C1B and C2 → C2A + C2B. The divided capacitors C1A, C1B are referred to herein as the first upper capacitor C1A and the first lower capacitor C1B. The partial capacitors C2A, C2B are referred to herein as the second upper capacitor C1A and the second lower capacitor C1B.

[0018] The voltage regulator 100 exhibits peak efficiency at a conversion ratio (CR) of 0.33. Furthermore, the voltage regulator 100 is capable of maintaining accurate regulation over a relatively wide range of operating conditions, which is particularly advantageous for battery chargers used in mobile phone applications.

[0019] The control of voltage regulator 100 (which may be performed by control unit 120) may be based on a PWM scheme consisting of an error amplifier and two interleaved ramp signals that are 180° out of phase. A ramp signal may be started and reset by a clock signal. The modulator may be configured to generate two pulses of equal duration. The duty cycle of the two pulses with respect to the clock period may be defined as D1. PWM and D2 PWMAn error signal (generated by an error amplifier) ​​can interact with the PWM ramps to generate a first duty cycle interval (for a first main state D1) and a second duty cycle interval (for a second main state D2). Alternatively, the PWM pulses can be generated by other means, such as a digital controller 120.

[0020] If D1 PWM and D2 PWM do not overlap, the interval between them (and / or the corresponding state) can be called DV. If D1 PWM and D2 PWMoverlap, the overlap interval (and / or the corresponding state) may be referred to as DP. The four duty cycle intervals D1, D2, DV, and DP may correspond to respective states of the voltage regulator 100 that result in certain changes in the energy storage elements C1, C2, and / or L1 (or L2), as described herein. In particular, the duty cycle interval and / or the DP state may be used to magnetize the inductor L1, L2 (resulting in a peak inductor current condition). The duty cycle interval and / or the DV state may be used to demagnetize the inductor L1, L2 (resulting in a valley inductor current condition). The duty cycle interval and / or the D1 state may be used to charge the flying capacitor C1B (while the inductor L1, L2 may be either magnetized or demagnetized depending on CR).The duty cycle interval and / or state D2 can be used to charge C2B (while inductor L1, L2 can be magnetized or demagnetized depending on CR).

[0021] By standard convention, all duty cycle values ​​are typically limited to the range 0 to 1. Steady-state operation for a hybrid power converter typically requires that the volt-sec balance for inductor L1 be maintained and / or that the amp-sec balance for the flying capacitors C1, C2 be maintained. The switching sequence (as defined by the duty cycle sequence) can ensure that these two requirements are met.

[0022] Fig. Figure 1b shows exemplary switching states (and / or corresponding duty cycle intervals) D1 111, D2 112, DV 113 for a relatively low duty cycle. The switching sequence is D1 → DV → D2 → DV → (repeat). Further, Fig. 1b the corresponding inductor current 114 through the inductor L1, L2.

[0023] Fig. Figure 1c shows exemplary switching states (and / or corresponding duty cycle intervals) D1 111, D2 112, DP 123 for a relatively high duty cycle. The switching sequence is D1 → DP → D2 → DP → (repeat). Further, Fig. 1b the corresponding inductor current 114 through the inductor L1, L2.

[0024] The partial capacitor voltage regulator 100 can have three different operating ranges corresponding to three different CR ranges: • Range 1: VIN ≥ 3*VOUT (ie 0 ≤ CR < 0.33); • Range 2: 3*VOUT ≥ VIN ≥ 2*VOUT (ie 0.33 ≤ CR ≤ 0.5); and • Range 3: VIN ≤ 2*VOUT (ie 0.5 ≤ CR ≤ 1).

[0025] For range 3, the voltage regulator 100 can be operated by keeping the power switches S10 and S11 constantly closed, thereby removing the influence of the flying capacitors C1A and C2A on the operation of the voltage regulator 100. On the other hand, the flying capacitors C1A and C2A contribute to the operation of the voltage regulator 100 in ranges 1 and 2. Given this difference in operating mode, a transition between the different operating ranges can be defined to avoid disturbances in the regulated output of the voltage regulator 100 (for the transition between ranges 2 and 3).

[0026] The Fig. 2a to 2d show the switching states D1, D2, DV1 and DV2 respectively for range 1 with VIN ≥ 3*VOUT, where 0.33 ≥ CR ≥ 0. The state sequence can repeat according to the following switching pattern: D1 → DV1→ D2→ DV2→ (repeat), as in Fig. 1b (where DV is alternately replaced by DV1 and DV2). The state sequence D1 → DV1 → D2 → DV2 can correspond to a complete operating cycle repeated at a predetermined frequency.

[0027] During the switching state D1 111, the switches S1, S3, S6, S8, S9 and S11 are open and the switches S2, S4, S5, S7 and S10 are closed, as in Fig. 2a. The current at the output of the voltage regulator 100 is provided via a main path 101 (through the inductor L1, L2) and via a secondary path 102 (bypassing the inductor L1, L2). In this document, the main path 101 is represented by a dashed line and the secondary path 102 is represented by a dotted line (except for the Fig. 9a to 9f, where the main path 101 is represented by a dotted line and the secondary path 102 is represented by a line comprising dots and dashes. The main path 101 may be referred to as the first current path and the secondary path 102 may be referred to as the second current path. The (dual-path) current provided by the secondary path 102 supplements the current provided by the main path 102. The figures, in particular Fig. 2a, indicate the (approximate) voltages at various nodes within the voltage regulator 100.

[0028] The floating capacitor C1B (also referred to as the first lower capacitor) is discharged to magnetize the inductor L1, L2 (via the main path 101). The floating capacitor C1A (also referred to as the first higher capacitor) is then discharged to charge the floating capacitor C2B (via the secondary path 102). The floating capacitors C2A and C2B (also referred to as the second higher capacitor and the second lower capacitor, respectively) are then charged from the input of the voltage regulator 100 (via the secondary path 102).

[0029] Fig. Figure 2b shows switching state D2 112, during which switches S1, S3, S6, S8, and S11 are closed and switches S2, S4, S5, S7, S9, and S10 are open. The floating capacitor C2B is discharged to magnetize the inductor L1, L2 (via the main path 101). Furthermore, the floating capacitor C2A is discharged to charge the floating capacitor C1B (via the secondary path 102). Furthermore, the floating capacitors C1A and C1B are charged from the input of the voltage regulator 100 (via the secondary path 102). Therefore, state D2 112 is complementary to state D1 111.

[0030] Fig. Figure 2c shows the switching state DV1 113, during which switches S2, S4, S6, S7, S8, S10, and S11 are open and switches S1, S3, S5, and S9 are closed. The inductor L1, L2 is demagnetized to ground via the closed switch S9 (via main path 101). The floating partial capacitors C1A and C1B are charged from the input of the voltage regulator 100 (via secondary path 102).

[0031] Fig. Figure 2d shows the switching state DV2 113, which is complementary to the switching state DV1 113. During the switching state DV2 113, the switches S2, S3, S4, S6, S8, S10, and S11 are open, and the switches S1, S5, S7, and S9 are closed. The inductor L1, L2 is demagnetized to ground via the closed switch S9 (via the main path 101). The floating partial capacitors C2A and C2B are charged from the input of the voltage regulator 100 (via the secondary path 102).

[0032] The Fig. 3a to 3f show exemplary switching states for operating the voltage regulator 100 in Region 2 for 3*VOUT ≥ VIN ≥ 2*VOUT, where 0.5 ≥ CR ≥ 0.33. The transition from Region 1 operation to Region 2 operation is essentially seamless if the Fig. 1b and Fig. 1c is used, where the modulation scheme of Fig. 1b is used in the area 1 and the modulation scheme of Fig. 1c is used in area 2.

[0033] Four switching states can be used to generate a complete switching cycle for operation in Region 2. These states can be Fig. 1c are designated D1 111, D2 112, DP1 123, and DP2 123, where DP1 and DP2 alternate with DP. The state sequence repeats according to the following pattern: D1→DP1→D2→DP2→(repeat)···. The state sequence D1→DP1→D2→DP2 can correspond to a complete operating cycle repeated at a predetermined frequency.

[0034] The Fig. 3a to 3d show the four switching states D1, D2, DP1, and DP2, respectively. Furthermore, the voltage levels at various nodes of the voltage regulator 100 are indicated. The switching state D1 111 of Fig. 3a corresponds to the switching state D1 111 of Fig. 2a. The switching state D2 112 of Fig. 3b corresponds to the switching state D2 112 of Fig. 2b.

[0035] However, for operation in region 2, in state D1, the floating capacitor C1B is charged and the inductor L1, L2 is demagnetized (via main path 101). The floating capacitor C1A is discharged to charge the floating capacitor C2B (via secondary path 102). Furthermore, the floating capacitors C2A and C2B are charged from the input of the voltage regulator 100 (via secondary path 102).

[0036] Similarly, for operation in Region 2, in state D2, the floating capacitor C2B is charged and the inductor L1, L2 is demagnetized (via main path 101). Furthermore, the floating capacitor C2A is discharged to charge the floating capacitor C1B (via secondary path 102). Furthermore, the floating capacitors C1A and C1B are charged from the input of the voltage regulator 100 (via secondary path 102). Therefore, state D2 112 is complementary to state D1 111.

[0037] During the DP1 state of Fig. 3c, switches S4, S6, S7, S8, S9, S10, and S11 are open, and switches S1, S2, S3, and S5 are closed. The inductor L1, L2 is magnetized, and the floating capacitor C1A is charged from the input of the voltage regulator 100 (via the main path 101). Furthermore, the floating capacitors C1A and C1B are charged from the input of the voltage regulator 100 (via the secondary path 102). The floating capacitors C2A and C2B are floating. Switch S5 can be kept closed to set the input node of the floating capacitors C2A and C2B to a defined potential.

[0038] In a complementary manner, during the DP2 state of Fig. 3d, switches S2, S3, S4, S8, S9, S10, and S11 are open, and switches S1, S5, S6, and S7 are closed. The inductor L1, L2 is magnetized, and the floating capacitor C2A is charged from the input of the voltage regulator 100 (via the main path 101). Furthermore, the floating capacitors C2A and C2B are charged from the input of the voltage regulator 100 (via the secondary path 102). The floating capacitors C1A and C1B are "floating." Switch S1 can be kept closed to set the input node of the floating capacitors C1A and C1B to a defined potential.

[0039] Region 2 operation typically cannot extend to conditions where VIN ≤ 2*VOUT, because in such a case, the intervals DP1 + DP2 would have to be greater than 1, which is not possible. In other words, Region 2 operation typically reaches maximum duty cycle operation when VIN = 2*VOUT. For voltage regulator 100 to regulate when VIN < 2*VOUT, voltage regulator 100 may experience a significant change in operation, i.e., a mode change, which is discussed in a later section of this document.

[0040] Fig. Figure 3e shows an alternative DP1 state (as an alternative to the DP1 state of Fig. 3c), and Fig. Figure 3f shows an alternative DP2 state (as an alternative to the DP2 state of Fig. 3d). In the alternative DP1 state, switches S8 and S11 are closed, discharging the flying capacitors C2A and C2B, otherwise the alternative DP1 state corresponds to the DP1 state of Fig. 3c. Complementarily, in the alternative DP2 state, switches S4 and S10 are closed, discharging the flying capacitors C1A and C1B, otherwise the alternative DP2 state corresponds to the DP2 state of Fig. 3d. This allows for reliable A-sec balancing. However, it may be necessary to use back-to-back field-effect transistors (FETs) for switches S2 and S6 in the alternate DP1 and DP2 states to avoid body diode conduction.

[0041] The Fig. 4a to 4c show different states for operating the voltage regulator 100 in the region 3 for VIN ≤ 2*VOUT, where 1 ≥ CR ≥ 0.5. Fig. 4a shows the state D1 H , Fig. 4b shows the state D2 H and Fig. 4c shows the state DP H As can be seen, switches S10 and S11 are constantly closed, removing the influence of the floating capacitors C1A and C1B. The state sequence repeats according to the following pattern: D1 H → DP H → D2 H → DP H → repeat, where 1≥D1PWM≥0.5; D2PWM=D1PWM; D1H=1−D1PWM; D1H=D2H; and DPH=D1PWM−0.5.

[0042] The conversion ratio (CR) can be given by VOUTVIN=D1PWM2−D1PWM, such that 1 ≥ CR ≥ 0.33 for 1 ≥ D1 PWM ≥ 0.5.

[0043] In the state D1 H (see Fig. 4a) Switches S2, S4, S6, S8 are open and switches S1, S3, S5, S7, S9, S10, S11 are closed. The inductor L1, L2 is demagnetized and the floating capacitors C1B and C2B are charged. In state D2 H (see Fig. 4b) Switches S1, S3, S5, S7, S9 are open and switches S2, S4, S6, S8, S10, S11 are closed. The inductor L1, L2 is demagnetized and the floating capacitors C1B and C2B are discharged. In the DP state H (see Fig. 4c) Switches S4, S8, and S9 are open, and switches S1, S2, S3, S5, S6, S7, S10, and S11 are closed. The inductor L1 and L2 are magnetized, and the floating capacitors C1B and C2B are charged.

[0044] Whenever the operating conditions change between Regions 2 and 3, the voltage regulator 100 typically must undergo a mode transition to maintain the output at the programmed level. This is because the split-capacitor mode in Region 2 operates at a maximum duty cycle whenever VIN ≤ 2*VOUT. One difference between the split-capacitor mode in Region 2 and the operating mode in Region 3 is a difference in the steady-state voltages across the flying capacitors, which • V(C1A) = V(C2A) = VOUT (in the partial capacitor mode) vs. V(C1A) = V(C2A) = 0V in the range 3 operating mode; and • V(C1B) = V(C2B) = VIN - 2*VOUT (in the partial capacitor mode) vs. V(C1B) = V(C2B) = VIN-VOUT in the range 3 operating mode.

[0045] The regulator transition between partial capacitor mode and region 3 operating mode can be performed in two different ways, depending on whether the input voltage VIN is increasing or decreasing (assuming that the output voltage VOUT is fixed).

[0046] If the initial operating conditions correspond to Region 3, the controller 100 operates in the Region 3 operating mode (according to the Fig. 4a to 4c). When the input voltage VIN begins to rise so that VIN becomes slightly greater than 2*VOUT, switches S10 and S11 are held OFF, but the remaining power switches continue to sequence in the manner specified for the Region 3 operating mode. This allows the flying capacitors C1A and C2A to charge from 0V. Once it is detected that V(C1A) and V(C2A) are charged to ~VOUT, the controller 120 begins executing the switching sequence specified for the Region 2 operating mode.

[0047] When the initial operating conditions correspond to Region 1 or Region 2 operation, the controller 100 operates in a partial capacitor mode according to the Fig. 2a to 2d or Fig. 3a to 3f. When the input voltage VIN begins to decrease so that VIN becomes only slightly greater than 2*VOUT, the regulator 100 begins to transition to Region 3 operating mode. During this transition, the regulator 100 can operate in a linear (non-switching) manner. All but two of the power switches are held in either static ON or OFF states. Switches S10 and S11 can be operated in saturation, so they behave like voltage-controlled current sources. This transition interval can be referred to as "LDO mode." Fig. Figure 5 shows the power switch states and an example of the control for S10 and S11 during LDO mode. In particular, Fig. 5 shows a linear control device 500 for controlling switches S10 and S11 in a linear mode. As a result, the voltage across the floating capacitors C1A and C2A can be reduced to 0V.

[0048] To make a seamless transition from partial capacitor mode to Region 3 operation, the charge on the flying capacitors should be redistributed in a controlled manner. Specifically, the flying capacitors C1A and C2A are discharged to 0V, and the flying capacitors C1B and C2B are charged to VIN-VOUT. The LDO mode (in Fig. 5) facilitates the charge redistribution process while maintaining the output voltage at the desired level by directing the charge redistribution energy of the flying capacitor to the load in a controlled manner. At the beginning of the transition, the inductor (in Fig. 5 (referred to as L1) is demagnetized, causing its current to drop to 0A via switch S9. Switch S9 can be ON during the inductor current ramp-down interval and can be turned off when 0A is detected. Alternatively, switch S9 can be kept OFF throughout the transition, allowing the inductor current to flow through the body diode of switch S9.

[0049] An example of a sequence of events leading to a mode transition is as follows: CR rises to a value close to, but less than, 0.5, which causes the MODE_TRANS signal to be activated. This, in turn, causes the gates of S10 and S11 to be disconnected from the gate drivers and connected to the output of the linear regulator (in Fig. 5 labeled “LDO_CTRL”). The Fig. The error amplifier shown in Figure 5 senses VOUT and compares it to the reference voltage VDAC. The error amplifier controls VGS of M1 (via M2, MCACS, P1, and P2) as well as VGS of S10 and S11. The arrangement of M1, S10, and S11 is analogous to a dual-output current mirror, with M1 as the controlling FET. The error amplifier modulates VGS of S10 and S11 to ensure that VOUT is maintained at the correct level. Once C1A and C2A are discharged to a value near 0V, the MODE_TRANS signal is deactivated, the mode transition is complete, and the Region 3 operating mode of regulator 100 begins operation. Comparators, an ADC, or other means can be used to sense the thresholds for MODE_TRANS enable and disable. LDO mode can be used to transition from low CR to high CR operation.

[0050] The advantage of the Region 3 operating mode is that the regulator 100 can operate properly over a wide range of conversion ratios: ~VIN ≥ VOUT ≥ ~0V. Maximum duty cycle operation occurs when VIN is close to VOUT. The Region 3 operating mode is more efficient than a two-stage buck converter, but typically not as efficient as the split-capacitor mode for 0.5 ≥ CR ≥ 0. The switching state sequence for the Region 3 operating mode may depend on CR.

[0051] The regulator 100 can operate in a start-up mode. If the output voltage VOUT is initially low (e.g., 0 V) ​​before the regulator 100 becomes active, it can begin switching to the Region 3 operating mode or the partial capacitor mode. During the initial start-up interval (or during a soft-start phase), the output voltage VOUT can increase at a controlled rate until it reaches a predetermined regulation threshold. If the input voltage VIN is greater than twice the target output voltage VOUT, then the regulator 100 can operate exclusively in the partial capacitor mode. However, if the input voltage VIN is less than twice the target output voltage VOUT, then a transition from the partial capacitor mode to the Region 3 operating mode can occur once the output voltage VOUT rises to a level greater than half the input voltage VIN.In this case, it may be desirable to operate the controller in the Region 3 operating mode during the entire operation (i.e., both during the soft-start interval and during steady-state operation).

[0052] The Range 3 operating mode typically requires that D1 PWM is greater than 0.5. This requirement prevents CR from starting at 0, which would be the case if the output is initially 0V. Therefore, a modification of the switching sequence of the Range 3 operating mode can be used to accommodate conversion ratios in the range of 0 to 0.33. The above switching sequence of the Range 3 operating mode can be replaced by a 2-step sequence for a start: D1 H → D2 H → (repeat) ···, where D1 H = 1 - D1 PWM ; D2 H = D1 PWM ; and where D2 PWM is not used. The states of the circuit breakers for D1 Hand D2 H are in the Fig. 4a and 4b respectively.

[0053] The partial capacitor topology of Fig. 1a can be operated as an efficient boost regulator if the source and load (i.e., the input and output of regulator 100) are reversed. Similar to partial-capacitor buck operation (i.e., step-down operation), there are two different operating regimes: • Upward range 1: 2*VIN ≥ VOUT ≥ VIN, ie 2 ≥ CR ≥ 1; and • Up range 2: VOUT ≥ 2*VIN, ie CR > 2.

[0054] For the boost or step-up range 1 with 2*VIN ≥ VOUT ≥ VIN, where 2 ≥ CR ≥ 1, the four power switch states D1, D2, DV1 and DV2 (shown in the Fig. 6a, Fig. 6b, Fig. 6c or 6d) can be used to create a complete switching or operating cycle. The state sequence can have the following pattern: D1 → DV1 → D2 → DV2 → (repeat). The duty cycle control can be based on the nested dual-ramp scheme, as shown in Fig. 1b is shown.

[0055] In the D1 state (in Fig. As shown in Figure 6a, switches S1, S3, S5, S6, S7, S9 can be open, and switches S2, S4, S8, S10, S11 can be closed. The inductor L2 can be magnetized, and the floating capacitors C1B and C2B can be charged.

[0056] In the D2 state (in Fig. 6b), switches S1, S2, S3, S5, S7, S9 can be open, and switches S4, S6, S8, S10, S11 can be closed. The inductor L2 can be magnetized, and the floating capacitors C1B and C2B can be charged.

[0057] In the DV1 state (in Fig. 6c), switches S2, S4, S7, S8, S9 can be open, and switches S1, S3, S5, S6, S10, S11 can be closed. Inductor L2 can be demagnetized, and floating capacitor C1B can be discharged, while floating capacitor C2B is "floating."

[0058] In the DV2 state (in Fig. 6d), switches S3, S4, S6, S8, S9 can be open, and switches S1, S2, S5, S7, S10, S11 can be closed. Inductor L2 can be demagnetized, and floating capacitor C2B can be discharged while floating capacitor C1B is "floating."

[0059] For boost range 2 with VOUT ≥ 2*VIN, where CR ≥ 2, four power switch states D1, D2, DP1, and DP2 can be used to generate a complete switching cycle. The state sequence can have the following pattern: D1 → DP1 → D2 → DP2 → (repeat). D1 = 1 - D1 PWM ; D2 = 1- D2 PWM and D1 PWM= 1 - D2 PWM .

[0060] The switching states D1 and D2 are the same as for the operation of area 1 (shown in the Fig. 6a and 6b respectively). The switching states DP1 and DP2 are shown in the Fig. 6e and 6f respectively. The inductor L2 is demagnetized during states D1 and D2 because the voltage of the flying capacitor (V FLY- CAP = VIN-VOUT) is greater than VIN. Therefore, the DP switching states DP1 and DP2 can be used to magnetize the inductor L2.

[0061] In the DP1 state (in Fig. 6e), switches S2, S4, S6, S5, S7, S8 can be open, and switches S1, S3, S9, S10, S11 can be closed. Inductor L2 can be magnetized, and floating capacitor C1B can be discharged, while floating capacitor C2B is "floating."

[0062] In the DP2 state (in Fig. 6f), switches S1, S2, S3, S4, S6, S8 can be open, and switches S5, S7, S9, S10, S11 can be closed. Inductor L2 can be magnetized, and floating capacitor C2B can be discharged, while floating capacitor C1B is "floating."

[0063] It should be noted that in the Fig. 2 to 6 circuit breakers that are open are shown in a light and / or transparent manner. On the other hand, circuit breakers that are closed are shown in solid form. It should also be noted that the inductor may be referred to as L1 or L2 in this document.

[0064] Fig. Figure 7 shows the conversion ratio (CR) 702 as a function of the duty cycle D1 PWM701 for the partial capacitor mode (curve 711) and for the Region 3 operating mode (curve 712). It can be seen that for CR > 0.5, a transition from the partial capacitor mode to the Region 3 operating mode is performed. It can be shown that for CR = 0.25, a 25% reduction in ripple current can be achieved in the partial capacitor mode compared to the Region 3 operating mode. Since the core losses associated with inductor L2 depend on the current ripple, the partial capacitor mode results in a significant improvement in the overall efficiency of the regulator.

[0065] It should be noted that the effective switching frequency of the regulator 100 may be twice the clock frequency used for timing the ramp signals used to generate the duty cycle PWM pulses of the Fig. 1b and Fig. 1c. In addition, the duty cycle of the switching node LX2 of the regulator can be twice the duty cycle of D1 PWM be.

[0066] It can be shown that the dual-path current (through the secondary path 102) for the partial capacitor mode exceeds that of the region 3 operating mode for all values ​​of the duty cycle D1 PWM This results in a reduction in the power loss associated with the inductor's DCR (DC resistance), as the average inductor current is reduced proportionally to the increase in the dual-path current. Furthermore, the effective inductance is increased when the average inductor current is reduced due to the bias current dependence. As a result, a reduced average inductor current leads to reduced current ripple and reduced core loss.

[0067] As stated above, the voltage regulator 100 shifts from Fig. 1a, the conversion ratio for peak efficiency operation is reduced from CR = 0.5 to 0.33. This is advantageous for applications requiring a typical converter output voltage VOUT that is more than twice the input voltage VIN. After a mode transition to Region 3 operation, conversion ratios CR > 0.5 are supported, but efficiency is sacrificed in this conversion region because resonant switching cannot be performed at CR = 0.5.

[0068] Fig. Figure 8 shows a voltage regulator 100 with an additional efficiency optimum at the converter conversion ratio CR = 0.5. The regulator 100 of Fig. 8 can be used for applications where converter efficiency is also important at conversion ratios CR > 0.5.

[0069] The connection paths with switches S10 and S11 are provided with back-to-back isolation by adding switches S12 and S13 in an anti-serial arrangement with respect to switches S10 and S11, respectively. Furthermore, switches S14 and S15 are added, as shown in Fig. 8. The switches S12 and S13 can always be switched on during the partial capacitor mode of operation and the switches S14 and S15 can always be switched off and consequently do not increase the switching loss of the regulator and / or converter 100. Once the converter 100 has left the partial capacitor mode of operation (using the transition scheme mentioned above), the converter 100 can Fig. 8 in a nested manner with the main operating states D1 H2 and D2 H2 operated in Fig. 9a and 9b respectively.

[0070] During the transition, the flying capacitors C1A and C2A are discharged to 0V and the flying capacitors C1B and C2B are charged to VIN-VOUT. For target conversion ratios CR < 0.5, additional states DV1 H2 and DV2 H2 according to the Fig. 9c or 9d are inserted into the switching sequence so that the state sequence D1 H2 → DV1 H2 → D2 H2 → DV2 H2 → (repeat) can be.

[0071] In the state D1 H2 (see Fig. 9a) switches S2, S4, S5, S6, S7, S9, S10, S11, S12, S13, S14 are open and switches S1, S3, S8, S15 are closed. In state D2 H2 (see Fig. 9b) the switches S1, S2, S3, S6, S8, S9, S10, S11, S12, S13, S15 are open and the switches S4, S5, S7, S14 are closed.

[0072] In the state DV1 H2 (see Fig. 9c) switches S2, S4, S5, S6, S7, S8, S10, S11, S12, S13, S14, S15 are open and switches S1, S3, S9 are closed. In state DV2 H2 (see Fig. 9d) the switches S1, S2, S3, S4, S6, S8, S10, S11, S12, S13, S14, S15 are open and the switches S5, S8, S9 are closed.

[0073] For target conversion ratios CR > 0.5, DP1 H2 and DP2 H2 according to the Fig. 9e or 9f are inserted into the switching sequence so that the state sequence D1 H2 → DP1 H2 → D2 H2 → DP2 H2 → (repeat) can be.

[0074] In the state DP1 H2 (see Fig. 9e) switches S2, S4, S6, S7, S8, S9, S10, S11, S12, S13 are open and switches S1, S3, S5, S14, S15 are closed. In state DP2 H2 (see Fig. 9f) the switches S2, S3, S4, S6, S8, S9, S10, S11, S12, S13 are open and the switches S1, S5, S7, S14, S15 are closed.

[0075] Switches S10 - S13 remain off during the switching sequences in region 3 operation and thus do not add any switching losses. Asymmetries in the circuit (or in the timing of states D1 H2 and D2 H2 ) can cause a drift in the voltages across the flying capacitors. To keep the voltage across the flying capacitor C1A at zero, the switch S2 can be closed for a relatively short interval within the switching state D2 H2 This automatically controls the voltage across the floating capacitor C1B to VIN-VOUT. Similarly, switch S6 can be closed for a relatively short interval within the switching state D1 H2 closed to keep the voltage across the floating capacitor C2A at zero. This automatically controls the voltage across the floating capacitor C2B to VIN-VOUT. This can improve regulation quality.

[0076] At the conversion ratio CR = 0.5, the converter operates 100 from Fig. 8 in resonance mode with a zero voltage across the inductor. Thus, the converter enables 100 of Fig. 8 peak efficiency operation at CR = 0.5 and at CR = 0.33.

[0077] Fig. 10 shows a flowchart of an exemplary method 1000 for operating a power converter 100. The method 1000 may be executed by a controller 120. The power converter 100 is configured to convert electrical power at an input voltage VIN at an input of the power converter 100 into electrical power at an output voltage VOUT at an output of the power converter 100.

[0078] The power converter 100 includes a first upper capacitor C1A and a first lower capacitor C1B, which are coupled together via a first center node (where the first center node is directly arranged between the first upper capacitor C1A and the first lower capacitor C1B). Furthermore, the power converter 100 includes a second upper capacitor C2A and a second lower capacitor C2B, which are coupled together via a second center node (where the second center node is directly arranged between the second upper capacitor C2A and the second lower capacitor C2B). The power converter 100 further includes an inductor L1, L2 (specifically, a single inductor), and a set of power switches S1-S15.

[0079] The method 1000 comprises controlling 1001 the set of power switches S1-S15 such that during an operating cycle (in particular each operating cycle) the power converter 100 is operated in a first main state D1 and in a second main state D2 in a mutually exclusive manner.

[0080] A state may include a first current path 101 providing current to the output and a second current path 102 providing additional current to the output, thereby increasing the total current at the output. The first current path 101 typically passes through inductor L1, L2 of power converter 100. The second current path 102 typically bypasses inductor L1, L2 (i.e., does not pass through any inductor L1, L2 of power converter 100).

[0081] The power converter 100, in the first main state D1, may have a first current path 101 from ground through the first lower capacitor C1B, through the inductor L1, L2 to the output. Furthermore, in the first main state D1, the power converter 100 may have a second current path 102 with a subpath from the input (of the power converter 100) through the second upper capacitor C2A, through the second lower capacitor C2B to the output (of the power converter 100), and with a subpath from ground through the first lower capacitor C1B, through the first upper capacitor C1A, through the second lower capacitor C2B to the output.

[0082] In the second main state D2, the power converter 100 may have a first current path 101 from ground through the second lower capacitor C2B, through the inductor L1, L2 to the output. Furthermore, in the second main state D2, the power converter 100 may have a second current path 102 with a subpath from the input through the first upper capacitor C1A, through the first lower capacitor C1B to the output, and with a subpath from ground through the second lower capacitor C2B, through the second upper capacitor C2A, through the first lower capacitor C1B to the output.

[0083] It should be noted that the components listed as being on a rung 101, 102 may be the only components located on the rung 101, 102 (apart from one or more (closed) circuit breakers S1-S15). Furthermore, the different components on a rung 101, 102 may be arranged in the given order (given within the definition of the respective rung) on ​​the rung 101, 102.

[0084] Thus, a power converter 100 is described that is configured to convert electrical power at an input voltage VIN at an input of the power converter 100 into electrical power at an output voltage VOUT at an output of the power converter 100. The power converter 100 includes a first upper capacitor C1A and a first lower capacitor C1B, which are (directly) coupled to each other via a first center node. Furthermore, the power converter 100 includes a second upper capacitor C2A and a second lower capacitor C2B, which are (directly) coupled to each other via a second center node. Furthermore, the power converter 100 includes an inductor L1, L2, and a set of power switches S1-S15.

[0085] The set of power switches S1-S15 may include a first power switch S1 with an input node coupled (directly) to the input of the power converter 100 and an output node coupled (directly) to an input node of the first upper capacitor C1A and to an input node of a tenth power switch S10. Alternatively or additionally, the set of power switches S1-S15 may include a second power switch S2 with an input node coupled (directly) to the first middle node and an output node coupled (directly) to an input node LX2 of the inductor L1, L2. Alternatively or additionally, the set of power switches S1-S15 may include a third power switch S3 with an input node coupled (directly) to an output node of the first lower capacitor C1B and an output node coupled (directly) to the output of the power converter 100.Alternatively or additionally, the set of power switches S1-S15 may comprise a fourth power switch S4 with an input node (directly) coupled to the output node of the first lower capacitor C1B and with an output node (directly) coupled to ground. Alternatively or additionally, the set of power switches S1-S15 may comprise a fifth power switch S5 with an input node (directly) coupled to the input of the power converter 100 and an output node (directly) coupled to an input node of the second upper capacitor C2A and to an input node of an eleventh power switch S11. Alternatively or additionally, the set of power switches S1-S15 may comprise a sixth power switch S6 with an input node (directly) coupled to the second middle node and an output node (directly) coupled to the input node LX2 of the inductor L1, L2.Alternatively or additionally, the set of power switches S1-S15 may include a seventh power switch S7 with an input node (directly) coupled to an output node of the second lower capacitor C2B and with an output node (directly) coupled to the output of the power converter 100. Alternatively or additionally, the set of power switches S1-S15 may include an eighth power switch S8 with an input node (directly) coupled to the output node of the second lower capacitor C2B and with an output node (directly) coupled to ground. Alternatively or additionally, the set of power switches S1-S15 may include a ninth power switch S9 with an input node (directly) coupled to the input node LX2 of the inductor L1, L2 and with an output node (directly) coupled to ground.Alternatively or additionally, the set of circuit breakers S1-S15 may include the tenth circuit breaker S10 with an output node coupled (directly) to the second center node. Alternatively or additionally, the set of circuit breakers S1-S15 may include the eleventh circuit breaker S11 with an output node coupled (directly) to the first center node.

[0086] It should be noted that the term "coupled" can refer to two entities that are "directly coupled" (without any other intermediate component). Therefore, in this document, the term "coupled" can be replaced by the term "directly coupled."

[0087] An output node of the first upper capacitor C1A may be (directly) coupled to an input node of the first lower capacitor C1B at the first center node. An output node of the second upper capacitor C2A may be (directly) coupled to an input node of the second lower capacitor C2B at the second center node. An output node of the inductor L1, L2 may be (directly) coupled to the output of the power converter 100.

[0088] Alternatively or additionally, the set of power switches S1-S15 may comprise a twelfth switch S12 in anti-serial arrangement with the eleventh switch S11, arranged between the input node of the second upper capacitor C2A and the first middle node. Alternatively or additionally, the set of power switches S1-S15 may comprise a thirteenth switch S13 in anti-serial arrangement with the tenth switch S10, arranged between the input node of the first upper capacitor C1A and the second middle node. Alternatively or additionally, the set of power switches S1-S15 may comprise a fourteenth switch S14 with an input node (directly) coupled to the input node of the first upper capacitor C1A and an output node (directly) coupled to the input node LX2 of the inductor L1, L2.Alternatively or additionally, the set of power switches S1-S15 may comprise a fifteenth switch S15 having an input node coupled (directly) to the input node of the second upper capacitor C2A and an output node coupled (directly) to the input node LX2 of the inductor L1, L2.

[0089] Additionally, the power converter may include an (analog and / or digital) control unit 120 configured to control the set of power switches S1-S15. The power converter 100 may be operated in a sequence of operating cycles. Each operating cycle may have a predetermined (constant) cycle duration. Each operating cycle may include a sequence of different states of the power converter. The power converter 100 may be operated exclusively within a state (i.e., one state at a time).

[0090] An operating cycle may include a first main state D1 and a second main state D2. In the first main state D1, the power converter 100 may include a first current path 101 from ground through the first lower capacitor C1B, through the inductor L1, L2 to the output. Further, in the first main state D1, the power converter 100 may include a second current path 102. The second current path 102 may include a subpath from the input through the second upper capacitor C2A, through the second lower capacitor C2B to the output. Further, the second current path 102 may include a subpath from ground through the first lower capacitor C1B, through the first upper capacitor C1A, through the second lower capacitor C2B to the output.

[0091] In the second main state D2, the power converter 100 may have a first current path 101 from ground through the second lower capacitor C2B, through the inductor L1, L2 to the output. Further, in the second main state D2, the power converter 100 may have a second current path 102. The second current path 102 may have a subpath from the input through the first upper capacitor C1A, through the first lower capacitor C1B to the output. Further, the second current path 102 may have a subpath from ground through the second lower capacitor C2B, through the second upper capacitor C2A, through the first lower capacitor C1B to the output.

[0092] The control unit 120 may be configured to control the set of power switches S1-S15 during a sequence of consecutive operating cycles, each operating cycle having a (exactly one) first main state D1 and a (exactly one) second main state D2. Alternatively or additionally, the control unit 120 may be configured to control the set of power switches S1-S15 such that the first state and the second state are repeated alternately, and / or such that the duty cycle and / or duration of the first main state D1 is equal to the duty cycle and / or duration of the second main state D2.

[0093] The repeated operation of the power converter 100 in different states can be used to regulate the output voltage VOUT to a target voltage and / or to regulate the conversion ratio to a target conversion ratio. In particular, the control unit 120 can be configured to regulate the output voltage VOUT to a quarter, a third, or half of the input voltage VIN. Alternatively or additionally, the control unit 120 can be configured to set, in particular to regulate, the target conversion ratio between the input voltage VIN and the output voltage VOUT, in particular to a target conversion ratio of 0.25, or to a target conversion ratio of 0.33, or to a target conversion ratio of 0.5.In particular, the control unit 120 may be configured to adjust the duty cycle of the first main state D1 and / or the second main state D2 to modify the conversion ratio between the input voltage VIN and the output voltage VOUT.

[0094] The control unit 120 may be configured to control the set of power switches S1-S15 such that the power converter 100 is operated during an operating cycle in a first valley state DV1 and in a second valley state DV2, which in particular are individually located between the first main state D1 and the second main state D2 and / or between the second main state D2 and the first main state D1. In particular, a state sequence may comprise or consist of the first main state D1, followed by a first valley state DV1, followed by the second main state D2, and followed by a second valley state DV2 (forming an operating cycle), e.g., when the target conversion ratio is between 0 and 0.33.

[0095] In the first valley state DV1, the power converter 100 may have a first current path 101 from ground through the inductor L1, L2 to the output. Furthermore, in the first valley state DV1, the power converter 100 may have a second current path 102 from the input through the first upper capacitor C1A, through the first lower capacitor C1B to the output.

[0096] In the second valley state DV2, the power converter 100 may have a first current path 101 from ground through the inductor L1, L2 to the output. Furthermore, in the second valley state DV2, the power converter 100 may have a second current path 102 from the input through the second upper capacitor C2A, through the second lower capacitor C2B to the output.

[0097] The control unit 120 may be configured to control the set of power switches S1-S15 such that the power converter 100 is operated during an operating cycle in a first peak state DP1 and in a second peak state DP2, which in particular are individually located between the first main state D1 and the second main state D2 and / or between the second main state D2 and the first main state D1. In particular, a state sequence may comprise or consist of the first main state D1, followed by a first peak state DP1, followed by the second main state D2, and followed by a second peak state DP2 (forming an operating cycle), e.g., when the target conversion ratio is between 0.33 and 0.5.

[0098] In the first peak state DP1, the power converter 100 may have a first current path 101 from the input through the first upper capacitor C1A, through the inductor L1, L2 to the output. Furthermore, in the first peak state DP1, the power converter 100 may have a second current path 102 from the input through the first upper capacitor C1A, through the first lower capacitor C1B to the output.

[0099] In the second peak state DP2, the power converter 100 may have a first current path 101 from the input through the second upper capacitor C2A, through the inductor L1, L2 to the output. Furthermore, in the second peak state DP2, the power converter 100 may have a second current path 102 from the input through the second upper capacitor C2A, through the second lower capacitor C2B to the output.

[0100] Additionally, in the first peak state DP1, the second current path 102 may include a further subpath from ground through the second lower capacitor C2B, through the second upper capacitor C2A, through the first lower capacitor C1B, to the output. Similarly, in the second peak state DP2, the second current path 102 may include a further subpath from ground through the first lower capacitor C1B, through the first upper capacitor C1A, through the second lower capacitor C2B, to the output. This may further increase the efficiency and / or reliability of the power converter 100.

[0101] The control unit 120 can be configured to determine a target conversion ratio between the input voltage VIN and the output voltage VOUT. Different states D1, D2, DV1, DV2, DP1, DP2 of the power converter 100 can be selected for the operating cycle depending on the target conversion ratio. This allows the power converter 100 to operate in a wide range of conversion ratios.

[0102] The control unit 120 may be configured to control the set of power switches S1-S15 such that the first upper capacitor C1A and the second upper capacitor C1B are bypassed during a complete operating cycle (in particular, during a sequence of complete operating cycles). Alternatively or additionally, the control unit 120 may be configured to provide an operating mode of the power converter 100 in which the first upper capacitor C1A and the second upper capacitor C1B are bypassed and / or in which power conversion is performed without the involvement of the first upper capacitor C1A and the second upper capacitor C1B.

[0103] By providing an operating mode that bypasses the first and second upper capacitors C1A, C1B, relatively high conversion ratios CR > 0.5 can be provided, thereby further increasing the operating range of the power converter 100.

[0104] In particular, the control unit 120 may be configured to operate the power converter 100 in a high conversion ratio operating mode (for CR > 0.5). In the high conversion ratio operating mode, an operating cycle may include a first modified main state D1 H , a second modified main state D2 H and a modified peak state DP H have.

[0105] In the first modified main state D1 H The power converter 100 may have a first current path 101 from ground through the inductor L1, L2 to the output. Furthermore, in the first modified main state D1H, the power converter 100 may have a second current path 102 with a subpath from the input through the second lower capacitor C2B to the output and / or with a subpath from the input through the first lower capacitor C1B to the output.

[0106] In the second modified main state D2 H The power converter 100 may have a first current path 101 with a subpath from ground through the first lower capacitor C1B, through the inductor L1, L2 to the output and / or with a subpath from ground through the second lower capacitor C2B, through the inductor L1, L2 to the output. In the second modified main state D2 H the power converter 100 may not have a second current path 102 (bypassing the inductor L1, L2).

[0107] In the modified peak state DP H The power converter 100 may have a first current path 101 from the input through the inductor L1, L2 to the output. Furthermore, the power converter 100 may be in the modified peak state DP Ha second current path 102 having a subpath from the input through the second lower capacitor C2B to the output and / or a subpath from the input through the first lower capacitor C1B to the output.

[0108] The control unit 120 may be configured to operate the power converter 100 in a transition mode between a first operating mode including the first upper capacitor C1A and the second upper capacitor C1B and a second operating mode (in particular, the high conversion ratio operating mode) not including the first upper capacitor C1A and the second upper capacitor C1B. The transition mode may be configured to discharge the first upper capacitor C1A and the second upper capacitor C1B such that a voltage across the respective upper capacitor C1A, C1B is substantially 0V. Alternatively or additionally, the transition mode may be configured to modify a voltage across the first lower capacitor C1B and the second lower capacitor C2B from VIN-2*VOUT to VIN-VOUT. By providing a transition mode, the quality of the voltage regulation of the power converter 100 may be increased.

[0109] The control unit 120 may be configured to selectively operate the power converter 100 in a boost mode of operation, with the output voltage VOUT greater than the input voltage VIN, and in a buck mode of operation, with the output voltage VOUT less than the input voltage VIN.

[0110] This can be achieved by swapping the input and output of the power converter 100. Possible states of an operating cycle for the boost mode of operation are described in the context of Fig. 6a to 6f.

[0111] The control unit 120 may be configured to control the set of power switches S1-S15 such that during an alternative operating cycle, the power converter 100 is in a first alternative main state D1 H2 and in a second alternative main state D2 H2operated in a mutually exclusive manner. The alternative operating cycle can be used to provide a higher-efficiency conversion ratio CR = 0.5.

[0112] In the first alternative main state D1 H2 The power converter 100 may have a first current path 101 from ground through the second lower capacitor C2B, through the second upper capacitor C2A, through the inductor L1, L2 to the output. Furthermore, in the first alternative main state D1H2, the power converter 100 may have a second current path 102 from the input through the first upper capacitor C1A, through the first lower capacitor C1B to the output.

[0113] In the second alternative main state D2 H2The power converter 100 may have a first current path 101 from ground through the first lower capacitor C1B, through the first upper capacitor C1A, through the inductor L1, L2 to the output. Furthermore, the power converter 100 may be in the second alternative main state D2. H2 a second current path 102 from the input through the second upper capacitor C2A, through the second lower capacitor C2B to the output.

[0114] The control unit 120 may be configured to control the set of power switches S1-S15 such that during the alternative operating cycle, the power converter 100 is in a first alternative valley state DV1 H2 and in a second alternative valley state DV2 H2 which is operated individually between the first alternative main state D1 H2 and the second alternative main state D2 H2 and / or between the second alternative main state D2H2 and the first alternative main state D1 H2 An exemplary operating cycle may have the following sequence of states: D1 H2 , DV1 H2 , D2 H2 , DV2 H2 (e.g. for CR ≤ 0.5).

[0115] In the first alternative valley state DV1 H2 The power converter 100 may have a first current path 101 from ground through the inductor L1, L2 to the output. Furthermore, the power converter 100 may be in the first alternative valley state DV1 H2 a second current path 102 from the input through the first upper capacitor C1A, through the first lower capacitor C1B to the output.

[0116] In the second alternative valley state DV2 H2 The power converter 100 may have a first current path 101 from ground through the inductor L1, L2 to the output. Furthermore, the power converter 100 may be in the second alternative valley state DV2 H2a second current path 102 from the input through the second upper capacitor C2A, through the second lower capacitor C2B to the output.

[0117] The control unit 120 may be configured to control the set of power switches S1-S15 such that the power converter 100 is in a first alternative peak state DP1 during the alternative operating cycle. H2 and in a second alternative peak state DP2 H2 which is operated individually between the first alternative main state D1 H2 and the second alternative main state D2 H2 and / or between the second alternative main state D2 H2 and the first alternative main state D1 H2 An exemplary operating cycle may have the following sequence of states: D1 H2 , DP1 H2 , D2 H2 , DP2 H2 (e.g. for CR ≥ 0.5).

[0118] In the first alternative peak state DP1 H2 The power converter 100 may have a first current path 101 from the input through the inductor L1, L2 to the output. Furthermore, the power converter 100 may be in the first alternative peak state DP1 H2 a second current path 102 from the input through the first upper capacitor C1A, through the first lower capacitor C1B to the output.

[0119] In the second alternative peak state DP2H2, the power converter 100 may have a first current path 101 from the input through the inductor L1, L2 to the output. Furthermore, in the second alternative peak state DP2, the power converter 100 may H2 a second current path 102 from the input through the second upper capacitor C2A, through the second lower capacitor C2B to the output.

[0120] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments set forth in the present document are primarily intended to be expressly illustrative only to assist the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include equivalents thereof.

Claims

[1] A power converter (100) configured to convert electrical power at an input voltage (VIN) at an input of the power converter (100) into electrical power at an output voltage (VOUT) at an output of the power converter (100); wherein the power converter (100) comprises - a first upper capacitor (C1A) and a first lower capacitor (C1B) coupled to each other via a first center node; - a second upper capacitor (C2A) and a second lower capacitor (C2B) coupled to each other via a second center node; - an inductor (L1, L2); - a set of circuit breakers (S1-S15); and - a control unit (120) configured to control the set of power switches (S1-S15) such that, during an operating cycle, the power converter (100) is operated in a first main state (D1) and in a second main state (D2) in a mutually exclusive manner; wherein in the first main state (D1) the power converter (100) has - a first current path (101) from ground through the first lower capacitor (C1B), through the inductor (L1, L2) to the output; and - a second current path (102) with - a subpath from the input through the second upper capacitor (C2A), through the second lower capacitor (C2B) to the output, and - a subpath from ground through the first lower capacitor (C1B), through the first upper capacitor (C1A), through the second lower capacitor (C2B) to the output; and wherein in the second main state (D2) the power converter (100) has - a first current path (101) from ground through the second lower capacitor (C2B) through the inductor (L1, L2) to the output; and - a second current path (102) with - a subpath from the input through the first upper capacitor (C1A), through the first lower capacitor (C1B) to the output, and - a subpath from ground through the second lower capacitor (C2B), through the second upper capacitor (C2A), through the first lower capacitor (C1B) to the output. [2] The power converter (100) according to claim 1, wherein - the control unit (120) is configured to control the set of circuit breakers (S1-S15) during a sequence of consecutive operating cycles; and - each operating cycle has a first main state (D1) and a second main state (D2). [3] The power converter (100) according to any preceding claim, wherein the control unit (120) is configured to control the set of power switches (S1-S15) such that - the first main state (D1) and the second main state (D2) are repeated alternately; and / or - a working cycle and / or a duration of the first main state (D1) is equal to a working cycle and / or a duration of the second main state (D2). [4] The power converter (100) according to any preceding claim, wherein - the control unit (120) is configured to control the set of power switches (S1-S15) such that, during an operating cycle, the power converter (100) is operated in a first valley state (DV1) and in a second valley state (DV2), which in particular are individually located between the first main state (D1) and the second main state (D2) and / or between the second main state (D2) and the first main state (D1); - in the first valley state (DV1) the power converter (100) has - a first current path (101) from ground through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the first upper capacitor (C1A), through the first lower capacitor (C1B) to the output; and - in the second valley state (DV2) the power converter (100) has - a first current path (101) from ground through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the second upper capacitor (C2A), through the second lower capacitor (C2B) to the output. [5] The power converter (100) according to any preceding claim, wherein - the control unit (120) is configured to control the set of power switches (S1-S15) such that, during an operating cycle, the power converter (100) is operated in a first peak state (DP1) and in a second peak state (DP2), which in particular are individually located between the first main state (D1) and the second main state (D2) and / or between the second main state (D2) and the first main state (D1); - in the first peak state (DP1) the power converter (100) has - a first current path (101) from the input through the first upper capacitor (C1A) through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the first upper capacitor (C1A), through the first lower capacitor (C1B) to the output; and - in the second peak state (DP2) the power converter (100) has - a first current path (101) from the input through the second upper capacitor (C2A), through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the second upper capacitor (C2A), through the second lower capacitor (C2B) to the output. [6] The power converter (100) according to claim 5, wherein - in the first peak state (DP1), the second current path (102) has a further sub-path from ground through the second lower capacitor (C2B), through the second upper capacitor (C2A), through the first lower capacitor (C1B) to the output; and - in the second peak state (DP2), the second current path (102) has a further sub-path from ground through the first lower capacitor (C1B), through the first upper capacitor (C1A), through the second lower capacitor (C2B) to the output. [7] The power converter (100) according to any preceding claim, wherein the control unit (120) is configured to - Determining a target conversion ratio between the input voltage (VIN) and the output voltage (VOUT); and - Selecting different states (D1, D2, DV1, DV2, DP1, DP2) for the operating cycle of the power converter (100) depending on the target conversion ratio. [8] The power converter (100) according to claim 7, wherein the control unit (120) is configured to - using a state sequence comprising the first main state (D1), followed by a first valley state (DV1), followed by the second main state (D2) and followed by a second valley state (DV2) as an operating cycle when the target conversion ratio is between 0 and 0.33; and / or - Using a state sequence comprising the first main state (D1), followed by a first peak state (DP1), followed by the second main state (D2) and followed by a second peak state (DP2) as an operating cycle when the target conversion ratio is between 0.33 and 0.

5. [9] The power converter (100) according to any preceding claim, wherein the set of power switches (S1-S15) comprises - a first power switch (S1) having an input node coupled to the input of the power converter (100) and an output node coupled to an input node of the first upper capacitor (C1A) and to an input node of a tenth power switch (S10); - a second power switch (S2) having an input node coupled to the first center node and an output node coupled to an input node (LX2) of the inductor (L1, L2); - a third power switch (S3) having an input node coupled to an output node of the first lower capacitor (C1B) and an output node coupled to the output of the power converter (100); - a fourth power switch (S4) having an input node coupled to the output node of the first lower capacitor (C1B) and an output node coupled to ground; - a fifth power switch (S5) having an input node coupled to the input of the power converter (100) and an output node coupled to an input node of the second upper capacitor (C2A) and to an input node of an eleventh power switch (S11); - a sixth power switch (S6) having an input node coupled to the second center node and an output node coupled to the input node (LX2) of the inductor (L1, L2); - a seventh power switch (S7) having an input node coupled to an output node of the second lower capacitor (C2B) and an output node coupled to the output of the power converter (100); - an eighth power switch (S8) having an input node coupled to the output node of the second lower capacitor (C2B) and having an output node coupled to ground; - a ninth power switch (S9) having an input node coupled to the input node (LX2) of the inductor (L1, L2) and having an output node coupled to ground; - the tenth power switch (S10) having an output node coupled to the second center node; and - the eleventh circuit breaker (S11) with an output node coupled to the first middle node. [10] The power converter (100) according to claim 9, wherein - an output node of the first upper capacitor (C1A) is coupled to an input node of the first lower capacitor (C1B) at the first center node; - an output node of the second upper capacitor (C2A) is coupled to an input node of the second lower capacitor (C2B) at the second center node; and - an output node of the inductor (L1, L2) is coupled to the output of the power converter (100). [11] The power converter (100) according to any one of claims 9 to 10, wherein the set of power switches (S1-S15) comprises - a twelfth switch (S12) in anti-serial arrangement with the eleventh switch (S11) arranged between the input node of the second upper capacitor (C2A) and the first middle node; - a thirteenth switch (S13) in anti-serial arrangement with the tenth switch (S10) arranged between the input node of the first upper capacitor (C1A) and the second middle node; - a fourteenth switch (S14) having an input node coupled to the input node of the first upper capacitor (C1A) and an output node coupled to the input node (LX2) of the inductor (L1, L2); and - a fifteenth switch (S15) having an input node coupled to the input node of the second upper capacitor (C2A) and an output node coupled to the input node (LX2) of the inductor (L1, L2). [12] The power converter (100) according to any preceding claim, wherein the control unit (120) is configured to control the set of power switches (S1-S15) - such that the first upper capacitor (C1A) and the second upper capacitor (C1B) are bypassed during a complete operating cycle; and / or - to provide an operating mode of the power converter (100) in which the first upper capacitor (C1A) and the second upper capacitor (C1B) are bypassed and / or in which power conversion is performed without the involvement of the first upper capacitor (C1A) and the second upper capacitor (C1B). [13] The power converter (100) according to any preceding claim, wherein - the control unit (120) is configured to operate the power converter (100) in a high conversion ratio operating mode; - in the high conversion ratio operating mode, an operating cycle comprises a first modified main state (D1 H ), a second modified main state (D2 H ) and a modified peak state (DP H ); - in the first modified main state (D1 H ) the power converter (100) has - a first current path (101) from ground through the inductor (L1, L2) to the output; and - a second current path (102) with - a subpath from the input through the second lower capacitor (C2B) to the output; and - a subpath from the input through the first lower capacitor (C1B) to the output; - in the second modified main state (D2 H ) the power converter (100) has - a first current path (101) with - a sub-path from ground through the first lower capacitor (C1B), through the inductor (L1, L2) to the output; and - a sub-path from ground through the second lower capacitor (C2B), through the inductor (L1, L2) to the output; - in the modified peak state (DP H ) the power converter (100) has - a first current path (101) from the input through the inductor (L1, L2) to the output; and - a second current path (102) with - a subpath from the input through the second lower capacitor (C2B) to the output; and - a subpath from the input through the first lower capacitor (C1B) to the output. [14] The power converter (100) according to any preceding claim, wherein - the control unit (120) is configured to operate the power converter (100) in a transition mode between a first operating mode including the first upper capacitor (C1A) and the second upper capacitor (C1B) and a second operating mode not including the first upper capacitor (C1A) and the second upper capacitor (C1B); - the transition mode is configured to discharge the first upper capacitor (C1A) and the second upper capacitor (C1B) such that a voltage across the respective upper capacitor (C1A, C1B) is substantially 0V; and - the transition mode is configured to modify a voltage across the first lower capacitor (C1B) and the second lower capacitor (C2B) from VIN-2*VOUT to VIN-VOUT. [15] The power converter (100) according to any preceding claim, wherein the control unit (120) is configured to selectively operate the power converter (100) in a boost mode of operation, with the output voltage (VOUT) greater than the input voltage (VIN), and in a buck mode of operation, with the output voltage (VOUT) less than the input voltage (VIN). [16] The power converter (100) according to any preceding claim, wherein - the control unit (120) is configured to control the set of power switches (S1-S15) such that during an alternative operating cycle the power converter (100) is in a first alternative main state (D1 H2 ) and in a second alternative main state (D2 H2) is operated in a mutually exclusive manner; - in the first alternative main state (D1 H2 ) the power converter (100) has - a first current path (101) from ground through the second lower capacitor (C2B), through the second upper capacitor (C2A), through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the first upper capacitor (C1A), through the first lower capacitor (C1B) to the output; - in the second alternative main state (D2 H2 ) the power converter (100) has - a first current path (101) from ground through the first lower capacitor (C1B), through the first upper capacitor (C1A), through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the second upper capacitor (C2A), through the second lower capacitor (C2B) to the output. [17] The power converter (100) according to claim 16, wherein - the control unit (120) is configured to control the set of power switches (S1-S15) such that during the alternative operating cycle the power converter (100) is in a first alternative valley state (DV1 H2 ) and in a second alternative valley state (DV2 H2 ) which can be individually switched between the first alternative main state (D1 H2 ) and the second alternative main state (D2 H2 ) and / or between the second alternative main state (D2 H2 ) and the first alternative main state (D1 H2 ) lay; - in the first alternative valley state (DV1 H2 ) the power converter (100) has - a first current path (101) from ground through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the first upper capacitor (C1A), through the first lower capacitor (C1B) to the output; and - in the second alternative valley state (DV2 H2 ) the power converter (100) has - a first current path (101) from ground through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the second upper capacitor (C2A), through the second lower capacitor (C2B) to the output. [18] The power converter (100) according to claim 16, wherein - the control unit (120) is configured to control the set of power switches (S1-S15) such that during the alternative operating cycle the power converter (100) is in a first alternative peak state (DP1 H2 ) and in a second alternative peak state (DP2 H2) which can be individually switched between the first alternative main state (D1 H2 ) and the second alternative main state (D2 H2 ) and / or between the second alternative main state (D2 H2 ) and the first alternative main state (D1 H2 ) lay; - in the first alternative peak state (DP1 H2 ) the power converter (100) has - a first current path (101) from the input through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the first upper capacitor (C1A), through the first lower capacitor (C1B) to the output; and - in the second alternative peak state (DP2 H2 ) the power converter (100) has - a first current path (101) from the input through the inductor (L1, L2) to the output; and - a second current path (102) from the input through the second upper capacitor (C2A), through the second lower capacitor (C2B) to the output. [19] A method (1000) for operating a power converter (100) configured to convert electrical power at an input voltage (VIN) at an input of the power converter (100) into electrical power at an output voltage (VOUT) at an output of the power converter (100); wherein the power converter (100) comprises - a first upper capacitor (C1A) and a first lower capacitor (C1B) coupled to each other via a first center node; - a second upper capacitor (C2A) and a second lower capacitor (C2B) coupled to each other via a second center node; - an inductor (L1, L2); and - a set of power switches (S1-S15); and wherein the method (1000) comprises controlling (1001) the set of power switches (S1-S15) such that, during an operating cycle, the power converter (100) is operated in a first main state (D1) and in a second main state (D2) in a mutually exclusive manner; - wherein in the first main state (D1) the power converter (100) has - a first current path (101) from ground through the first lower capacitor (C1B), through the inductor (L1, L2) to the output; and - a second current path (102) with - a subpath from the input through the second upper capacitor (C2A), through the second lower capacitor (C2B) to the output; and - a subpath from ground through the first lower capacitor (C1B), through the first upper capacitor (C1A), through the second lower capacitor (C2B) to the output; and - wherein in the second main state (D2) the power converter (100) has - a first current path (101) from ground through the second lower capacitor (C2B), through the inductor (L1, L2) to the output; and - a second current path (102) with - a subpath from the input through the first upper capacitor (C1A), through the first lower capacitor (C1B) to the output, and - a subpath from ground through the second lower capacitor (C2B), through the second upper capacitor (C2A), through the first lower capacitor (C1B) to the output.

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