Scoreboard

Abstract

A display panel comprising: a glass substrate (10); a circuit layer (12) arranged on the glass substrate (10); a layer of light-emitting elements (14) arranged on the circuit layer (12); an encapsulation layer (16) covering the layer of light-emitting elements (14); and a first organic film (30) covering the encapsulation layer (16), wherein the first organic film (30) covers an extended residual portion of an inorganic film (16a) extending from the encapsulation layer (16) in an edge region (BZ) of the display panel (PNL), and wherein a portion of the first organic film (30) arranged directly on the residual inorganic film (16a) is exposed to the outside at an externally exposed side surface (EDGE) of the display panel (PNL).

Description

[0001] This application claims priority over Korean patent application No. 10-2021-0099886, which was filed in the Republic of Korea on July 29, 2021, and whose disclosure is incorporated herein in full by reference. Background of Revelation 1. Area

[0002] The present disclosure relates to a display board. 2. Discussion of the state of the art

[0003] Electroluminescent displays are broadly classified into inorganic and organic light-emitting displays, depending on the materials of their light-emitting layers. Active-matrix organic light-emitting displays include organic light-emitting diodes (hereinafter referred to as "OLEDs") that emit light themselves (i.e., are self-emitting) and offer fast response times and advantages, including high light emission efficiencies, brightness, and viewing angles. In organic light-emitting displays, the OLEDs are arranged in pixels. Because organic light-emitting displays offer fast response times, excellent light emission efficiencies, brightness, and viewing angles, and are capable of producing a gradation of black into a true black (e.g.,To show true black), the organic light-emitting display devices are excellent in contrast ratio and color reproduction capability.

[0004] Organic light-emitting displays do not require backlighting units and can be implemented on a flexible plastic substrate, a thin glass substrate, or a metal substrate. Therefore, flexible displays can be implemented as organic light-emitting displays.

[0005] The screen size of a flexible display can be varied by wrapping, folding, and bending the flexible display panel. Flexible displays can be implemented as rollable displays, foldable displays, bendable displays, sliding displays, or similar devices. Flexible displays can be applied not only to mobile devices such as smartphones and tablet PCs, but also to televisions, vehicle displays, and portable devices, and the range of applications for flexible display devices is constantly expanding.

[0006] Much research is being conducted to reduce the bezel area, which is present at the edge of a scoreboard. A bezel area is a non-display area where no image is shown on the scoreboard. Due to advancements in manufacturing technology, the bezel area of ​​a scoreboard is becoming smaller.

[0007] A scoreboard can consist of several inorganic and organic films. Due to deformation or impact on a substrate of the scoreboard, cracks can propagate inwards through any remaining inorganic film on the edge of the scoreboard. To prevent crack propagation, structures such as crack stoppers and the like can be incorporated into the edge of the scoreboard.

[0008] Multiple scoreboards can be obtained by separating a circuit pattern from a mother substrate during the scoreboard manufacturing process. When separating the circuit pattern from the mother substrate, a laser may irradiate the mother substrate with light. Heat can propagate through the inorganic films into the circuit pattern, potentially causing it to crack and become damaged. In other words, an exposed edge of an inorganic film can become a source of heat conduction / penetration and crack propagation. However, because the mother substrate requires a process tolerance for separating the circuit pattern from it, and sufficient space must be provided for a crack stop, there is a limit to reducing the scoreboard's border area, especially when the additional crack stop is used. Summary of Revelation

[0009] The present disclosure is aimed at solving the necessities and problems described above.

[0010] In particular, it is an object of the present disclosure to provide a display panel capable of preventing the propagation of heat and cracks while minimizing the size of the edging area. Furthermore, embodiments of the present disclosure can better prevent an edge section of an inorganic film from becoming a source of heat conduction / penetration during manufacturing, while also minimizing the edging area.

[0011] It should be noted that the present disclosure is not limited to the features described above and that other features of the present disclosure will be apparent to those skilled in the art from the following descriptions.

[0012] The problem is solved by the features of the independent claims. Preferred embodiments are specified in the dependent claims.

[0013] According to one aspect of the present disclosure, a display panel is created comprising: a circuit layer arranged on a glass substrate, a layer of light-emitting elements arranged on the circuit layer, an encapsulation layer designed to cover the layer of light-emitting elements, and an organic film designed to cover the encapsulation layer. The organic film covers an extended section of an inorganic film extending from the encapsulation layer in a border region of the display panel.

[0014] According to another aspect of the present disclosure, a display panel is provided comprising a circuit layer arranged on a glass substrate, a layer of light-emitting elements arranged on the circuit layer, an encapsulation layer designed to cover the layer of light-emitting elements, and an organic film designed to cover the encapsulation layer. A residual inorganic film extending from the encapsulation layer is exposed on an outward-facing side face of the display panel. On the side face of the display panel, the organic film is exposed on top of the inorganic film.

[0015] According to a further aspect of the present disclosure, a display panel is created comprising a circuit layer arranged on a glass substrate, a layer of light-emitting elements arranged on the circuit layer, an encapsulation layer designed to cover the layer of light-emitting elements, and an organic film designed to cover the encapsulation layer. On an outwardly exposed side face of the display panel, a portion of the organic film is exposed, covering a remaining inorganic film extending from the encapsulation layer.

[0016] In one or more embodiments, the display panel may further have one or more dam patterns extending away from the glass substrate in an area between an end of the circuit layer and a side surface of the display panel.

[0017] In one or more embodiments, the glass substrate can have a tapered surface that is positioned in the edging area of ​​the display panel.

[0018] In one or more embodiments, the glass thickness can decrease from a tapered surface of the glass substrate towards a side surface of the display panel.

[0019] In one or more embodiments, the display panel may further have a conductor interconnection pattern formed on the encapsulation layer, wherein the first organic film may cover the conductor interconnection pattern.

[0020] In one or more embodiments, the display panel may further include a polarization plate arranged on the first organic film.

[0021] In one or more embodiments, one end of the polarization plate can be spaced inwards or can project outwards from one end of a side surface of the glass substrate by a predetermined separation distance.

[0022] In one or more embodiments, the polarizing plate and the glass substrate can form a stepped section on a side surface of the display panel.

[0023] In one or more embodiments, the display panel may further comprise a touch sensor layer formed on the encapsulation layer.

[0024] In one or more embodiments, the display panel may further comprise a color filter layer formed on the touch sensor layer.

[0025] In one or more embodiments, the first organic film can cover a conductor interconnection pattern of the touch sensor layer or can cover a color filter and a black matrix pattern of the color filter layer.

[0026] In one or more embodiments, the display panel may further comprise a second organic film for glass protection, which is arranged on a rear surface of the glass substrate.

[0027] In one or more embodiments, the circuit layer, the layer of light-emitting elements, the encapsulation layer and the first organic film can be stacked on a front surface of the glass substrate.

[0028] In one or more embodiments, the second organic film for glass protection is in contact with the first organic film on a side surface of the display panel.

[0029] In one or more embodiments, a side surface of the extended section of the inorganic film can be surrounded by the second organic film for glass protection and the first organic film.

[0030] In one or more embodiments, the encapsulation layer and the section of the first organic film can be made of the same material.

[0031] In one or more embodiments, the thickness of the section of the first organic film can be less than the thickness of the encapsulation layer.

[0032] In one or more embodiments, the thickness of the first organic film can be greater than the thickness of the section of the first organic film.

[0033] In one or more embodiments, the first organic film can be arranged directly on the section of the first organic film in an area corresponding to the outwardly exposed side surface of the display panel. List of characters

[0034] The foregoing and other tasks, features and advantages of the present disclosure will become clearer to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings; these show: Fig. 1 and Fig. 2 views showing display devices of embodiments of the present disclosure; Fig. 3-6 Views of various examples of embodiments of the present disclosure when a display board is folded; Fig. 7 to Fig. 9 Circuit diagrams showing various pixel circuits applicable to a pixel circuit according to embodiments of the present disclosure; Fig. 10 a waveform diagram showing control signals that are sent to the in Fig. 9 pixel circuit shown according to an embodiment of the present disclosure; Fig. 11 a cross-sectional view showing a structure of a display board according to an embodiment of the present disclosure; Fig. 12 a cross-sectional view showing a structure of a display board according to another embodiment of the present disclosure; Fig. 13 a cross-sectional view showing a structure of a display board according to yet another embodiment of the present disclosure; Fig. 14 to Fig. 17 cross-sectional views showing structures of edge areas of display boards (PNL) according to embodiments of the present disclosure; Fig. 18 a view showing several cells formed on a mother substrate according to an embodiment of the present disclosure; Fig. 19 a selective glass etching process of an embodiment of the present disclosure; Fig. 20 to Fig. 22 views showing a complete glass etching process and a selective glass etching process in time series according to embodiments of the present disclosure; Fig. 23 a view detailing a process for reducing an enclosure area with a structure in which no heat and crack propagation occurs in a manufacturing process of a display board according to an embodiment of the present disclosure. Detailed description of the embodiments

[0035] The advantages and features of the present disclosure and its implementation methods are illustrated by the embodiments described below, which are described with reference to the accompanying drawings. However, the present disclosure can be implemented in numerous different forms and is not limited to the embodiments set forth herein. Rather, the present embodiments will complete the disclosure and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is defined only within the scope of the appended claims.

[0036] Shapes, sizes, ratios, angles, and numbers disclosed in the accompanying drawings for describing embodiments of the present disclosure are merely examples, and thus the present disclosure is not limited to them. The same reference numerals refer to the same elements throughout the description. Furthermore, detailed descriptions of known related technologies may be omitted from the description of the present disclosure to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0037] The terms "comprise," "contain," "exhibit," and "consist of" used here are generally intended to allow the addition of other components, unless the terms are used with the term "only." All references to a singular form may include plural forms unless explicitly stated otherwise.

[0038] Components are interpreted as encompassing a normal error range, even if this is not explicitly stated.

[0039] When the positional relationship between two components is described using terms such as "on", "above", "below", and "next to", one or more components may be positioned between the two components unless the terms are used with the term "immediately" or "directly".

[0040] The terms “first”, “second”, and the like may be used to distinguish components from one another, but the functions or structures of the components are not restricted by ordinal numbers or component names preceding the components.

[0041] The following embodiments can be partially or fully connected or combined and can be linked and operated in technically different ways. The embodiments can be implemented independently of one another or in combination with one another.

[0042] In a display device of embodiments of the present disclosure, a pixel circuit and the gate drive circuit may comprise several transistors. Transistors may be implemented as oxide thin-film transistors (oxide TFTs) containing an oxide semiconductor, low-temperature polysilicon TFTs (LTPS TFTs) containing low-temperature polysilicon, or the like. Each of the transistors may be implemented as a p-channel TFT or as an n-channel TFT.

[0043] In general, a transistor can be a three-electrode device comprising a gate, a source, and a drain. The source is an electrode that supplies charge carriers to the transistor. Inside the transistor, charge carriers begin to flow from the source. The drain is an electrode through which charge carriers exit the transistor. In a transistor, charge carriers flow from a source to a drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. The n-channel transistor has a current flow direction from the drain to the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain.Since holes flow from the source to the drain in a p-channel transistor, a current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on an applied voltage. Therefore, the disclosure is not limited to a single source and drain of a transistor. In the following description, the source and drain of a transistor are referred to as the first electrode and the second electrode.

[0044] A gate signal oscillates between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the transistor's threshold voltage, and the gate-off voltage is set to a voltage lower than the transistor's threshold voltage.

[0045] The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, a gate-on voltage can be a high gate voltage (VGH or VEH), and a gate-off voltage can be a low gate voltage (VGL or VEL). In the case of a p-channel transistor, the gate-on voltage can be a low gate voltage (VGL or VEL), and the gate-off voltage can be a high gate voltage (VGH or VEH).

[0046] Various embodiments of the present disclosure can be described in detail below with reference to the accompanying drawings.

[0047] With reference to Fig. 1 and Fig. 2 comprises a display device of the present disclosure, a display panel PNL in which a pixel arrangement is arranged on a screen, and a display panel driver.

[0048] A pixel arrangement AA of the PNL display panel comprises data lines DL, gate lines GL that intersect the data lines DL, and pixels P, which are defined by the data lines DL and the gate lines GL and arranged in a matrix form. The PNL display panel may have a border area BZ, which is a non-display area outside the pixel arrangement AA.

[0049] Each pixel P comprises subpixels of different colors for color representation. These subpixels can include red subpixels (hereinafter referred to as "R subpixels"), green subpixels (hereinafter referred to as "G subpixels"), and blue subpixels (hereinafter referred to as "B subpixels"). Additionally, each pixel P can also contain a white subpixel. For example, a pixel unit can contain three and / or four subpixels. Hereinafter, a pixel can be interpreted as a subpixel unless otherwise defined. Each subpixel can have a pixel circuit.

[0050] The pixel circuit can include a light-emitting element, a driver element that supplies a current to the light-emitting element, one or more switching elements that switch current paths of the driver element and the light-emitting element, at least one capacitor that maintains a gate-source voltage Vgs of the driver element, and the like.

[0051] The light-emitting element can be implemented as an organic light-emitting diode (OLED). The OLED comprises an organic compound layer formed between an anode and a cathode. The organic compound layer can include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but this disclosure is not limited to these. When voltages are applied to the anode and cathode of the OLED, holes passing through the HTL and electrons passing through the ETL are moved into the EML to form excitons, and visible light is emitted from the EML. The OLED used as the light-emitting element (EL) can have a tandem structure in which multiple emission layers are stacked. The tandem-structured OLED can improve the luminance and lifetime of pixels.

[0052] The display driver writes pixel data of an input image to the pixels P. The display driver comprises a data driver, which supplies a data voltage of the pixel data to the data lines DL, and a gate driver GIP, which sequentially supplies a gate pulse to one or more gate lines GL. The data driver is integrated into an integrated control circuit (driver IC) DIC. The integrated control circuit DIC can be bonded to the display PNL.

[0053] The integrated control circuit DIC is connected to the data lines DL via data output channels to supply a voltage of a data signal to the data lines DL. The control IC DIC may include a timing controller. The timing controller sends pixel data of an input image received from a host system SYS to the data driver and controls the operating timing of the data driver and the gate driver GIP.

[0054] The data driver of the control IC DIC converts the pixel data into a gamma compensation voltage using a digital-to-analog converter (DAC) and outputs the data voltage to the pixel circuits via the data lines.

[0055] The gate driver GIP can include a shift register that is implemented with the pixel array on a circuit layer of the display panel PNL. Under the control of the timing controller, the shift register of the gate driver GIP sequentially supplies gate signals to the gate lines GL. The gate signal can include a sampling pulse and an emission control pulse (hereinafter referred to as the "EM pulse"). The shift register can include a sampling driver that outputs the sampling pulse and an EM driver that outputs the EM pulse.

[0056] The host system SYS can be implemented as an application processor (AP). The host system SYS sends the pixel data of the input image to the driver IC DIC. The host system SYS can be connected to the driver IC DIC via a flexible printed circuit (FPC).

[0057] The display panel of the present disclosure can be manufactured on a thin, flexible glass substrate. The glass substrate can be a glass film with a thickness of 0.2 mm or less. The glass film can be a commercially available tempered glass film.

[0058] The PNL display panel has a width in the X-axis direction, a length in the Y-axis direction, and a constant thickness in the Z-axis direction. Since a circuit layer and a layer of light-emitting elements are arranged on the glass substrate, the thickness of the PNL display panel is greater than that of the glass substrate. The width and length of the PNL display panel can be specified to different design values ​​depending on the application of the display device. The PNL display panel can be manufactured to have a rectangular plate shape, but this disclosure is not limited to that. For example, the PNL display panel can be manufactured as a deformable panel with a curved portion. If the thickness of the glass substrate of the PNL display panel is small, even a small force can flexibly bend the glass substrate with a sufficiently large curvature.

[0059] The PNL display board may have a protruding folding section FP, as shown in the Fig. 1 and Fig. Figure 3 shows the folding part FP with the control IC DIC, which can be folded backwards.

[0060] As in Fig. As shown in Figure 4, the edging areas EB on two sides of a PNL scoreboard, on each side of which a GIP gate driver is mounted, can be folded. Furthermore, the PNL scoreboard can be folded once or several times, as shown in Figure 4. Fig. 5 and Fig. Figure 6 is shown. Fig. 5 and Fig. 6. Fold lines FL can overlap a pixel arrangement AA through which an input image is displayed. The glass substrate can be etched at the fold lines FL, and thus the thickness of the folded area can be less than that of an unfolded area (e.g., to facilitate folding).

[0061] Due to process variations and element property variations caused during the manufacturing process of the display panel, differences in the electrical properties of a driver element can occur between subpixels, and these differences can increase as the pixel drive time increases. To compensate for variations in the electrical properties of the driver elements among the pixels, an internal or external compensation technique can be applied to an organic light-emitting display device.

[0062] In internal compensation, an internal compensation circuit implemented in each pixel circuit is used to detect a threshold voltage of a driver for each subpixel, and the gate-source voltage (Vgs) of the driver is compensated by this threshold voltage. In external compensation, an external compensation circuit is used to detect a current or voltage of a driver in real time, which varies according to the electrical characteristics of the driver. With external compensation, by modulating the pixel data (digital data) of an input image by varying (or changing) the electrical characteristics of the driver, as detected for each pixel, the variation (or change) in the electrical characteristics of the driver is compensated in real time at each pixel.

[0063] Fig. 7 to Fig. Figure 9 are circuit diagrams showing various pixel circuits applicable to the pixel circuits of the present disclosure. It should be noted that the pixel circuits of the present disclosure do not relate to those in Fig. 7 to Fig. The 9 shown are limited.

[0064] With reference to Fig. Figure 7 comprises a pixel circuit consisting of a light-emitting element EL, a drive element DT that supplies a current to the light-emitting element EL, a switching element M01 that connects data lines DL in response to a scanning pulse SCAN, and a capacitor Cst connected to a gate electrode of the drive element DT. In the pixel circuit, the drive element DT and the switching element M01 can be implemented as n-channel transistors.

[0065] The switching element M01 is switched on according to a gate-on voltage of the scanning pulse SCAN in order to connect the data line DL to the gate electrode of the control element DT.

[0066] The driver element DT comprises a first electrode connected to a VDD line PL, to which a pixel drive voltage ELVDD is applied; a gate electrode connected to the switching element M01 and the capacitor Cst; and a second electrode connected to the light-emitting element EL. The driver element DT supplies a current to the light-emitting element EL according to a gate-source voltage Vgs to drive the light-emitting element EL. When a forward voltage between an anode and a cathode is greater than or equal to a threshold voltage of the light-emitting element EL, the light-emitting element EL is switched on and emits light.

[0067] The capacitor Cst is positioned between the gate electrode and a second electrode of the control element DT and is connected to them, and stores the gate-source voltage Vgs.

[0068] With reference to Fig. 8. The pixel circuit can further comprise a second switching element M02, which is arranged between a reference voltage line REFL and the second electrode of the control element DT and is connected to them. In the pixel circuit, the control element DT and the switching elements M01 and M02 can be implemented as n-channel transistors.

[0069] The second switching element M02 is switched on according to the gate-in voltage of the scanning pulse SCAN or a detection pulse SENSE in order to connect the reference voltage line REFL, to which a reference voltage Vref is applied, to the second electrode of the control element DT.

[0070] In a sensing mode, a current flowing through a channel of the driver DT, or a voltage between the driver DT and the light-emitting element EL, can be sensed via the reference line REFL. The current flowing through the reference line REFL is converted into a voltage using an integrator and then into digital data using an analog-to-digital converter (hereinafter referred to as an "ADC"). The digital data is sensing data, which includes the threshold voltage of the driver DT or mobility information. The sensing data can be sent to a compensation unit of the driver IC DIC. The compensation unit can receive the sensing data from the ADC and compensate for any deviation or change in the threshold voltage of the driver DT by adding or multiplying a compensation value, selected based on the sensing data, with pixel data.

[0071] The in Fig. 7 and Fig. The pixel circuits shown in Figure 8 can further include an EM switching element that switches a current path of the light-emitting element EL in response to the EM pulse. The EM switching element can be arranged between and connected to the pixel drive voltage ELVDD and the drive element DT, or between and connected to the drive element DT and the light-emitting element (e.g., OLED).

[0072] Fig. Figure 9 is a circuit diagram that represents an example of a pixel circuit to which an internal compensation circuit is applied. Fig. 10 is a waveform diagram representing control signals sent to the Fig. The 9 pixel circuit shown will be created.

[0073] With reference to Fig. 9 and Fig. 10 The pixel circuit comprises a light-emitting element EL, a control element DT that supplies a current to the light-emitting element EL, and switching circuits that switch voltages applied to the light-emitting element EL and the control element DT.

[0074] The switching circuits are connected to power lines PL1, PL2, and PL3, to which a pixel drive voltage ELVDD, a low-potential power voltage ELVSS, and an initialization voltage Vini are applied, as well as data lines DL and gate lines GL1, GL2, and GL3. The switching circuits activate voltages applied to the light-emitting element EL and the drive element DT in response to scanning pulses SCAN(N-1) and SCAN(N) and an EM pulse EM(N).

[0075] The switching circuit samples a threshold voltage Vth of the driver element DT using several switching elements M1 to M6, stores the sampled threshold voltage Vth of the driver element DT in a capacitor Cst, and compensates a gate voltage of the driver element DT with the threshold voltage Vth of the driver element DT. Both the driver element DT and the switching elements M1 to M6 can be implemented as p-channel transistors.

[0076] A pixel circuit's control period can be divided into an initialization period Tini, a sampling period Tsam, and an emission period Tem, as described in Fig. 10 is shown.

[0077] An Nth sampling pulse SCAN(N) is generated as a gate-on voltage VGL in the sampling period Tsam and applied to a first gate line GL1. An (N-1)th sampling pulse SCAN(N-1) is generated before the Nth sampling pulse SCAN(N) and applied to a second gate line GL2. The initialization period Tini is defined by the (N-1)th sampling pulse SCAN(N-1). The EM pulse EM(N) is generated as a gate-off voltage VEH in the initialization period Tini and the sampling period Tsam and applied to a third gate line GL3.

[0078] During the initialization period Tini, the (N-1)th sampling pulse SCAN(N-1) is generated as a gate-on voltage VGL and applied to the second gate line GL2. During the initialization period Tini, the voltages of the first and third gate lines GL1 and GL3 are gate-off voltages VGH and VEH.

[0079] During the sampling period Tsam, the Nth sampling pulse SCAN(N) is generated as a pulse of the gate-in voltage VGL and applied to the first gate line GL1. During the sampling period Tsam, the voltages of the second and third gate lines GL2 and GL3 are gate-out voltages VGH.

[0080] During at least one segment of the emission period Tem, the EM pulse EM(N) is generated as a gate-on voltage VEL and applied to the third gate line GL3. During the emission period Tem, the voltages of the first and second gate lines GL1 and GL2 constitute the gate-off voltage VGH.

[0081] An anode of the light-emitting element EL is connected to a fourth node n4, which is located between the fourth and sixth switching elements M4 and M6. The fourth node n4 is connected to the anode of the light-emitting element EL, a second electrode of the fourth switching element M4, and a second electrode of the sixth switching element M6. A cathode of the light-emitting element EL is connected to a VSS line PL3, to which the low-potential power voltage ELVSS is applied. The light-emitting element EL emits light with a current flowing according to a gate-source voltage Vgs of the driver element DT. A current path of the light-emitting element EL is switched through the second and fourth switching elements M2 and M4.

[0082] The capacitor Cst is positioned between and connected to a VDD line PL1 and a second node n2. The capacitor Cst has a first electrode connected to the VDD line PL1 and a second electrode connected to the second node n2. The data voltage Vdata, compensated by a threshold voltage Vth of the driver DT, is charged into the capacitor Cst. Since the data voltage Vdata in each subpixel is compensated by the threshold voltage Vth of the driver DT, the subpixels are compensated with respect to any variation (or change) in the properties of the driver DT.

[0083] A first switching element M1 is switched on in response to the gate-on voltage VGL of the Nth sampling pulse SCAN(N) and connects the second node n2 to a third node n3. The second node n2 is connected to a gate electrode of the drive element DT, the second electrode of the capacitor Cst, and a first electrode of the first switching element M1. The third node n3 is connected to a second electrode of the drive element DT, a second electrode of the first switching element M1, and a first electrode of the fourth switching element M4. A gate electrode of the first switching element M1 is connected to the first gate line GL1 to receive the Nth sampling pulse SCAN(N). The first electrode of the first switching element M1 is connected to the second node n2, and the second electrode of the first switching element M1 is connected to the third node n3.

[0084] Since the first switching element M1 is switched on during a very short horizontal period 1H, in which the Nth scanning pulse SCAN(N) is generated as the gate-on voltage VGL in a single frame period, a leakage current can be generated in an off state. To suppress the leakage current of the first switching element M1, the first switching element M1 can be implemented as a transistor with a dual-gate structure, in which two transistors are connected in series.

[0085] The second switching element M2 is switched on in response to the gate-on voltage VGL of the Nth sampling pulse SCAN(N) to supply the data voltage Vdata to the first node n1. One gate electrode of the second switching element M2 is connected to the first gate line GL1 to receive the Nth sampling pulse SCAN(N). A first electrode of the second switching element M2 is connected to the first node n1. A second electrode of the second switching element M2 is connected to the data line DL, to which the data voltage Vdata is applied. The first node n1 is connected to the first electrode of the second switching element M2, a second electrode of a third switching element M3, and a first electrode of the control element DT.

[0086] The third switching element M3 is switched on in response to the gate-on voltage VEL of the EM pulse EM(N) to connect the VDD line PL1 to the first node n1. One gate electrode of the third switching element M3 is connected to the third gate line GL3 to receive the EM pulse EM(N). One electrode of the third switching element M3 is connected to the VDD line PL1. A second electrode of the third switching element M3 is connected to the first node n1.

[0087] The fourth switching element M4 is switched on in response to the gate-on voltage VEL of the EM pulse EM(N) to connect the third node n3 to the fourth node n4. One gate electrode of the fourth switching element M4 is connected to the third gate line GL3 to receive the EM pulse EM(N). The first electrode of the fourth switching element M4 is connected to the third node n3, and a second electrode of the fourth switching element M4 is connected to the fourth node n4.

[0088] A fifth switching element M5 is turned on in response to a gate-on voltage VGL of the (N-1)th sampling pulse SCAN(N-1) to connect the second node n2 to a Vini line PL2. One gate electrode of the fifth switching element M5 is connected to the second gate line GL2 to receive the (N-1)th sampling pulse SCAN(N-1). A first electrode of the fifth switching element M5 is connected to the second node n2, and a second electrode of the fifth switching element M5 is connected to the Vini line PL2, to which the initialization voltage Vini is applied. To suppress leakage current from the fifth switching element M5, the fifth switching element M5 can be implemented as a transistor with a dual-gate structure, where two transistors are connected in series.

[0089] The sixth switching element M6 is switched on in response to the gate-on voltage VGL of the Nth sampling pulse SCAN(N) to connect the Vini line PL2 to the fourth node n4. One gate electrode of the sixth switching element M6 is connected to the first gate line GL1 to receive the Nth sampling pulse SCAN(N). One electrode of the sixth switching element M6 is connected to the Vini line PL2, and the second electrode is connected to the fourth node n4. In another embodiment, the gate electrodes of the fifth and sixth switching elements M5 and M6 can be connected together to the second gate line GL2, to which the (N-1)th sampling pulse SCAN(N-1) is applied. In this case, the fifth and sixth switching elements M5 and M6 can be switched on simultaneously in response to the (N-1)th sampling pulse SCAN(N-1) during the initialization period Tini.

[0090] The control element DT adjusts the current flowing through the light-emitting element EL according to the gate-source voltage Vgs in order to drive the light-emitting element EL. The control element DT comprises the gate electrode connected to the second node n2, the first electrode connected to the first node n1, and the second electrode connected to the third node n3.

[0091] During the initialization period Tini, the (N-1)th sampling pulse SCAN(N-1) is generated as the gate-on voltage VGL. The Nth sampling pulse SCAN(N) and the EM pulse EM(N) maintain the gate-off voltages VGH and VEH, respectively, during the initialization period Tini. Therefore, during the initialization period Tini, the fifth switching element M5 is turned on, and the second node n2 is initialized to the initialization voltage Vini. If the fifth and sixth switching elements M5 and M6 are turned on during the initialization period Tini, the second and fourth nodes n2 and n4 are initialized to the initialization voltage Vini.

[0092] A hold period Th can be set between the initialization period Tini and the sampling period Tsam, and between the sampling period Tsam and the emission period Tem. During the hold period Th, the sampling pulses SCAN(N-1) and SCAN(N), the EM pulse EM(N), the gate-off voltages VGH, and the main nodes n1 to n4 of the pixel circuit are suspended.

[0093] During the sampling period Tsam, the Nth sampling pulse SCAN(N) is generated as the gate-on voltage VGL. One pulse of the Nth sampling pulse SCAN(N) is synchronized with the data voltage Vdata of the pixel data to be written to the subpixels of the Nth pixel row. The (N-1)th sampling pulse SCAN(N-1) and the EM pulse EM(N) are the gate-off voltages VGH and VEH, respectively, during the sampling period Tsam. Therefore, during the sampling period Tsam, the first and second switching elements M1 and M2 are switched on. In this situation, the sixth switching element M6 is also switched on to supply the initialization voltage Vini to the fourth node n4, thus preventing light emission from the light-emitting element EL.

[0094] During the sampling period Tsam, the gate voltage DTG of the control element DT is increased by the current flowing through the first and second switching elements M1 and M2. During the sampling period Tsam, the threshold voltage Vth of the control element DT is sampled by the capacitor Cst.

[0095] During the emission period Tem, the EM pulse EM(N) can be generated as a gate-on voltage VGL. During the emission period Tem, the voltage of the EM pulse EM(N) can be inverted with a predefined duty cycle. Therefore, the EM pulse EM(N) can be generated as a gate-on voltage VGL for at least part of the emission period Tem.

[0096] When the EM pulse EM(N) is the gate-on voltage VEL, a current flows between the pixel drive voltage ELVDD and the light-emitting element EL, and thus the light-emitting element EL can emit light. During the emission period Tem, the (N-1)th and Nth scan pulses SCAN(N-1) and SCAN(N) are the gate-off voltages VGH. During the emission period Tem, the third and fourth switching elements M3 and M4 are turned on in response to the gate-on voltage VEL of the EM pulse EM(N). When the EM pulse EM(N) is the gate-on voltage VEL, the third and fourth switching elements M3 and M4 are turned on, and current flows through the light-emitting element EL. During the emission period Tem, the current flowing through the light-emitting element EL is equal to K(ELVDD-Vdata). 2 . K denotes a constant value determined by charge mobility, parasitic capacitance, and channel capacitance of the control element DT.

[0097] Fig. 11 to Fig. Figure 13 are cross-sectional views showing structures of display boards according to embodiments of the present disclosure.

[0098] With reference to Fig. 11 A display panel PNL can have a circuit layer 12, a layer of light-emitting elements 14 and an encapsulation layer 16 stacked on a glass substrate 10.

[0099] The glass substrate 10 can be made of sheet-shaped, alkali-free glass or non-alkali glass. The glass substrate 10 will not deform if its impact resistance is greater than that of a plastic substrate.

[0100] Layer 12 can include pixel circuits connected by intermediate links such as data lines, gate lines, power lines, and the like, a gate driver GIP connected to the gate lines, and similar components. The intermediate links and circuit elements of layer 12 can comprise multiple insulating layers, two or more metal layers separated by the insulating layers in between, and an active layer containing a semiconductor material.

[0101] The layer of light-emitting elements 14 can comprise light-emitting elements EL that are controlled by the pixel circuits. The light-emitting elements EL can include red light-emitting elements, green light-emitting elements, and blue light-emitting elements. In a further embodiment, the layer of light-emitting elements 14 can include a white light-emitting element and / or a color filter. The light-emitting elements EL of the layer of light-emitting elements 14 can be covered by a protective layer comprising an organic film and a protective film.

[0102] The encapsulation layer 16 covers the light-emitting element layer 14 to seal the circuit layer 12 and the light-emitting element layer 14. The encapsulation layer 16 can have a multi-layer insulating film structure in which an organic film and an inorganic film are stacked alternately. The inorganic film blocks the penetration of moisture or oxygen. The organic film planarizes one surface of the inorganic film. When the organic and inorganic films are stacked in multiple layers, the path of movement for moisture or oxygen is longer than when the organic and inorganic films are formed as a single layer, and thus the penetration of moisture / oxygen that could affect the light-emitting element layer 14 can be effectively blocked.

[0103] With reference to Fig. 12. A display panel PNL can further comprise a touch sensor layer 18 formed on an encapsulation layer 16. The touch sensor layer 18 can be implemented as a capacitive touch sensor that detects a touch input based on a change in capacitance before and after the touch input. The touch sensor layer 18 includes conductor interconnection patterns 18a that form the capacitance of the touch sensors. The capacitance of the touch sensors can be formed between the conductor interconnection patterns 18a.

[0104] The touch sensor layer 18 can comprise an organic film covering the conductor connection patterns 18a of the touch sensors. An extended section of the organic film can cover a residual inorganic film or a glass substrate 10 in a border area BZ, that is, an edge area, of the display panel PNL.

[0105] Furthermore, a polarizing plate can be bonded to the touch sensor layer 18. The polarizing plate can convert the polarization of external light reflected from the metal patterns of the circuit layer 12, thus improving visibility and contrast. The polarizing plate can be implemented as a linear polarizing plate and a phase-delay film combined, or as a circular polarizing plate. A cover glass can be bonded to the polarizing plate.

[0106] With reference to Fig. 13. A display panel PNL may further comprise a touch sensor layer 18 formed on an encapsulation layer 16 and a color filter layer 20 formed on the touch sensor layer 18.

[0107] The color filter layer 20 can comprise a red, green, and blue filter CF. Furthermore, the color filter layer 20 can comprise a black matrix pattern BM. The color filter layer 20 can absorb a portion of a wavelength of light reflected by a circuit layer 12 to act as a polarizing plate, thereby increasing color purity. In the present embodiment, the color filter layer 20, which has a higher light transmittance than the polarizing plate, can be applied to the display panel PNL, thus improving the light transmittance, thickness, and flexibility of the display panel PNL. Additionally, a cover glass can be bonded to the color filter layer 20.

[0108] The color filter layer 20 can comprise an organic film covering the color filters and the black matrix patterns. An extended section of the organic film can cover a remaining inorganic film or a glass substrate 10 in a border area BZ, that is, an edge area, of the display panel PNL.

[0109] Fig. 14 to Fig. Figure 17 are cross-sectional views showing the structures of edge regions of PNL display boards according to embodiments of the present disclosure. Fig. 4 to Fig. 17 The reference mark “EDGE” designates a side surface of the PNL display board on at least one of its four sides. The EDGE side surface of the PNL display board is exposed to the outside.

[0110] With reference to Fig. 14 to Fig. 17 an organic film 30 in a border area BZ of the display board PNL covers a remaining inorganic film 16a, which extends from an encapsulation layer 16.

[0111] A glass substrate 10 has a tapered surface 10a at an end region near the EDGE side surface of the PNL scoreboard, and the tapered surface 10a of the glass substrate 10 is positioned in the edging region BZ of the PNL scoreboard or in a shaded area where the remaining inorganic film is present. The glass thickness on the tapered surface 10a of the glass substrate 10 gradually decreases towards the EDGE side surface of the PNL scoreboard.

[0112] The edge of the PNL scoreboard comprises the remaining inorganic film 16a formed on the glass substrate 10 and the organic film 30 covering the remaining inorganic film 16a. The edge of the PNL scoreboard may further comprise one or more dam patterns 15.

[0113] The remaining inorganic film 16a may be a thin residual film extending over the dam patterns 15 when an upper inorganic film of the encapsulation layer 16 is formed. Since heat and cracks can propagate through the remaining inorganic film 16a, the remaining inorganic film 16a may not be exposed on the side surface of the PNL scoreboard. Alternatively, the remaining inorganic film 16a may be exposed on the side surface of the PNL scoreboard with a very small thickness, at which point heat and cracks do not propagate.

[0114] The dam patterns 15 can protrude in an area between the end of the circuit layer 12 and the side surface EDGE of the display panel PNL or in an outer area from the glass substrate 10.

[0115] The dam pattern 15 blocks an organic film material of the encapsulation layer 16 over the end of the edge of the display panel PNL during the process of forming the encapsulation layer 16 on the display panel PNL. The dam pattern 15 can be formed from an organic film or an inorganic film forming the circuit layer 12 and the light-emitting element layer 14, or it can be configured to have a multilayer structure in which an inorganic film and an organic film are stacked.

[0116] The organic film 30 covers the remaining inorganic film 16a. The organic film 30 is thicker than the remaining inorganic film 16a. In a selective glass etching process, the organic film 30 acts as an etch stop, thus etching the glass substrate 10 down to the organic film 30. The remaining inorganic film 16a, which is covered by the organic film 30 on the EDGE side surface of the PNL display panel, is exposed with a thin layer. Therefore, it is possible to solve the problem of heat and crack propagation through the remaining inorganic film 16a.

[0117] The organic film 30 can be a section extending from the organic film covering conductor interconnection pattern of a touch sensor layer 18 and planarizing a surface of it, or can be a section extending from the organic film covering the color filters and black matrix pattern in the color filter layer 20 and planarizing a surface of it.

[0118] The remaining inorganic film 16a extending from the encapsulation layer 16 may be exposed at the EDGE side surface of the PNL scoreboard, and the organic film 30 formed on it and covering the remaining inorganic film 16a may also be exposed. Alternatively, the remaining inorganic film 16a may not be exposed at the PNL side surface, and a portion of the organic film 30 covering the remaining inorganic film 16a may be exposed.

[0119] Since the remaining inorganic film 16a is barely exposed on the EDGE side surface of the PNL scoreboard, a separate crack stop is not required. Therefore, the BZ border area of ​​the PNL scoreboard can be minimized.

[0120] In the EDGE side surface of the PNL display panel, a polarizing plate 22, the organic film 30, the remaining inorganic film 16a, and the glass substrate 10 can be exposed on a surface essentially without step differences, as shown in Fig. Figure 14 shows that in this situation, the remaining inorganic film 16a may be exposed or partially exposed at the EDGE side surface. For example, the edge of the polarizing plate 22 and the edge of the organic film 30 may each be much thicker than the edge of the remaining inorganic film 16a.

[0121] As it is in Fig. As shown in Figure 15, a polarizing plate 22 can be cut at a position that is inwardly spaced by a predetermined distance G from the side face EDGE of the display panel PNL. In this situation, the glass substrate 10 can project further outward than the polarizing plate 22, and thus the glass substrate 10 and the polarizing plate 22 can have a step or stepped section. The organic film 30, which is stacked on the glass substrate 10, can essentially coincide with one end of a side face of the polarizing plate 22, and therefore a small step difference can exist between them.

[0122] As it is in Fig. As shown in Figure 16, a polarizing plate 22 can be cut at a position spaced outwards by a predetermined distance G from the side face EDGE of the display panel PNL. In this situation, the polarizing plate 22 can project further outwards than the glass substrate 10, and thus the glass substrate 10 and the polarizing plate 22 can have a step or stepped section. The organic film 30 stacked on the glass substrate 10 can essentially coincide with the end of the side face of the polarizing plate 22, and therefore a small step difference can exist between them.

[0123] A circuit layer 12, a layer of light-emitting elements 14, and an encapsulation layer 16 can be stacked on a front surface of the glass substrate 10, and an organic film 11 for protecting the glass can be formed on a rear surface of the glass substrate 10, as shown in Fig. Figure 17 shows that the polarizing plate 22 can be cut at a position where the polarizing plate 22, the organic film 30, and the organic film 11 are stacked for glass protection. In this situation, as shown in Figure 17, the polarizing plate 22 can be cut at a position where it, the organic film 30, and the organic film 11 are stacked for glass protection. Fig. As shown in Figure 17, the organic film 11 for glass protection, the organic film 30 and the polarization plate 22 can be exposed essentially on the EDGE side surface of the PNL display panel without a step difference.

[0124] As it is in Fig. As shown in Figure 17, the organic film 11 for glass protection and the organic film 30 on the EDGE side surface of the PNL scoreboard can be in direct contact with each other. In this situation, the remaining inorganic film 16a on the EDGE side surface of the scoreboard may not be exposed. In other words, the edge of the remaining inorganic film 16a may be enclosed and protected by the organic film 30 and the organic film 11.

[0125] Although the polarizing plate 22 can be arranged on the organic film 30, the polarizing plate 22 can be derived from the structure of the display panel. Fig. 13 can be omitted.

[0126] In the PNL display manufacturing process, each of several cells, separated from a mother substrate (mother glass), can be produced as an individual display. The mother substrate can be applied in a multi-layer process to reduce the display's manufacturing costs, thus allowing multiple cells to be formed on the mother substrate simultaneously.

[0127] Fig. Figure 18 is a view showing several cells formed on a mother substrate. Fig. Figure 19 is a view that represents a selective glass etching process. Fig. 20 to Fig. Figure 22 shows views of a complete glass etching process and a selective glass etching process in a time series.

[0128] With reference to Fig. 18 to Fig. 22. Several cells CELL1 to CELL3 can be formed simultaneously on a mother substrate 100, which is a large glass substrate. A cell can comprise a pixel array AA and a gate driver GIP of a single display panel. In an etching process, the thickness t1 of 500 µm of the mother substrate 100 can be reduced to a thickness t2 of 200 µm or less.

[0129] To reduce the thickness of the substrate 100 and partially remove glass, both full and selective glass etching processes can be performed. To divide the substrate 100 into cell units, a scribing process and a laser trimming process can be performed, or the laser trimming process alone can be used.

[0130] In the complete glass etching process, the thickness of the glass of the parent substrate 100 is reduced. In the selective glass etching process, the parent substrate 100 can be exposed to a glass etching agent at an intercellular boundary, thus allowing the parent substrate 100 to be selectively etched. As a result of both the complete and selective glass etching processes, the thickness of the parent substrate 100 is reduced, and the glass is etched from an intercellular boundary SL down to an organic film 30. In this situation, as depicted in Fig. As shown in Figure 19, an inorganic film can react with the glass etchant in a section where the glass has been removed, and thus a residual inorganic film 16a can be removed.

[0131] As it is in Fig. As shown in Figure 20, the complete glass etching process can be carried out, followed by the selective glass etching process. In the complete glass etching process, the entire surface of the mother substrate 100 is etched by the glass etchant, thus reducing the thickness t1 of the mother substrate 100 to thickness t2. After the complete glass etching process has been carried out, the selective glass etching process can be performed. In the selective glass etching process, a mask film 101 can be formed on a rear surface of the mother substrate 100. The mask film 101 has an open through-hole through which a portion of the glass of the mother substrate 100 is exposed.

[0132] The mother substrate 100 can be etched by spraying an etchant onto the mother substrate 100, on which the mask film 101 is formed, or by immersing the mother substrate 100 in a water tank containing a glass etchant. During the etching process of the mother substrate 100, the organic film 30 can act as an etch stopper, and the glass can be etched until the mother substrate 100 is etched and the glass etchant reaches the organic film 30 (see, for example, also Fig. 19).

[0133] The glass etching agent reacts with the glass of the mother substrate 100 through the open through-hole of the mask film 101, thus etching the glass. By adjusting the duration of the selective glass etching process, the depth of the mother substrate 100 etched along a boundary line SL between cells, as well as the length, thickness, angle, etc., of the tapered surface, can be adjusted.

[0134] The mask film 101 can be removed or can remain on the glass substrate 10 after the mother substrate 100 has been divided into units of cells. Prior to a process of cutting the polarizing plate 22, the organic film 11 can be formed on the rear surface of the glass substrate 10 to protect the glass, as shown in Fig. 17 is shown.

[0135] As it is in Fig. As shown in Figure 21, after the mask film 101 has been formed to expose a selectively etched area, including the boundary line SL between cells on the rear surface of the mother substrate 100, the glass in the selectively etched area can be etched with the glass etchant to a depth less than the thickness t1 of the mother substrate 100. Next, if the mask film 101 is removed and then the rear surface of the mother substrate 100 is completely etched, the thickness of the mother substrate 100 can be reduced, and the glass and the remaining inorganic film 16a can be completely removed in the selectively etched area, as shown in Figure 21. Fig. 19 is shown.

[0136] As it is in Fig. As shown in Figure 22, in the selectively etched area, after a laser beam has been directed onto the mask film 101 and the glass has then been removed to a depth less than the thickness t1 of the parent substrate 100, the complete glass etching process can be carried out. In this situation, the glass and the remaining inorganic film 16a in the selectively etched area can be completely removed, as shown in Figure 22. Fig. 19 is shown.

[0137] In the scribing process, the mother substrate 100 is cut by a scribing wheel along the boundary line SL between cells and divided into units of cells. After the scribing process has been carried out, in the laser trimming process the side surface EDGE of each of the display panels PNL is trimmed using a laser cutting device. As described in Fig. As shown in Figure 19, the mother substrate 100, since the glass of the mother substrate 100 and the remaining inorganic film 16a in the selectively etched area are completely removed, can be subdivided into units of cells solely by the laser trimming process without the scribing process.

[0138] Fig. Figure 23 is a view that details a process for reducing an enclosure area with a structure in which no heat and crack propagation occurs in a manufacturing process of a display board.

[0139] With reference to Fig. 23 In a mother substrate 100, a crack-stopping pattern 40, which suppresses crack propagation, can be formed in a shaded area SR between a boundary line SL between cells and dam patterns 15, or a process can be carried out without the crack-stopping pattern 40. The crack-stopping pattern 40 can be formed from an inorganic film and / or an organic film forming a circuit layer 12 and a layer of light-emitting elements 14 and can protrude from the mother substrate 100. The crack-stopping pattern 40 can block a path along which cracks propagate to a pixel array within the cells by means of a residual inorganic film 16a in a scribing process or a laser trimming process. The crack-stopping pattern 40 can be removed when the mother substrate 100 is subdivided into units of cells.

[0140] The shaded area SR can be subdivided into an inner shaded area ISR near the boundary line SL between cells and an outer shaded area OSR near the dam pattern 15.

[0141] The thickness of the parent substrate 100 is reduced during an etching process, and the parent substrate 100 in the shaded area SR is completely removed in a selective etching process. Subsequently, the shaded area SR can be completely removed in a laser trimming process, or, for example, the inner shaded area ISR can be partially removed. Fig. In Figure 23, the reference symbol “LR” denotes a laser trim line. After the laser trimming process has been carried out, at least a section of the shaded area SR of the mother substrate 100 can be removed, thus minimizing the edging area BZ of a scoreboard PNL. In this situation, a side surface EDGE of one end of the scoreboard PNL can be aligned with an end of a tapered surface 10a of a glass substrate 10, as shown in Figure 23. Fig. 14 and Fig. 15 is shown.

[0142] According to the present disclosure, by using a glass substrate as the substrate of a scoreboard, it is possible to implement a scoreboard that is less affected by an external impact and is not easily deformed compared to a plastic substrate.

[0143] According to the present disclosure, it is possible to prevent the propagation of heat and cracks by reducing the thickness of an inorganic film that can serve as a nucleus or starting point for heat and crack propagation on a side surface of a display panel, or by preventing the inorganic film from being exposed.

[0144] According to the present disclosure, after an encapsulation layer has been formed on a display board, an extended section of an organic film formed on the encapsulation layer is used as an etch stop to prevent the penetration of a glass etchant at an edge of the display board, and thus it is possible to minimize an edge area of ​​the display board without a process for adding a separate etch stop.

[0145] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are apparent to those skilled in the art from the above description and the attached claims.

[0146] The problems to be solved by the present disclosure, the means of solving the problems and the effects of the above-described disclosure are examples and thus the scope of the claims is not limited thereto.

[0147] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited to them and can be implemented in many different forms without deviating from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. It is therefore understood that the embodiments described above are illustrative in all aspects and do not limit the present disclosure.The scope of protection of the present disclosure should be interpreted on the basis of the following claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

Claims

[1] Scoreboard comprising: a glass substrate (10); a circuit layer (12) arranged on the glass substrate (10); a layer of light-emitting elements (14) arranged on the circuit layer (12); an encapsulation layer (16) covering the layer of light-emitting elements (14); and a first organic film (30) covering the encapsulation layer (16), wherein the first organic film (30) covers an extended section of an inorganic film (16a) extending from the encapsulation layer (16) in a border area (BZ) of the display panel (PNL). [2] Display panel according to one of the preceding claims, further comprising one or more dam patterns (15) extending away from the glass substrate (10) in an area between an end of the circuit layer (12) and a side surface (EDGE) of the display panel (PNL). [3] Display panel according to one of the preceding claims, wherein the glass substrate (10) has a tapered surface (10a) which is arranged in the edging area (BZ) of the display panel (PNL), and / or the thickness of the glass decreases from a tapered surface (10a) of the glass substrate (10) to a side surface (EDGE) of the display panel (PNL). [4] Scoreboard which includes: a glass substrate (10); a circuit layer (12) arranged on the glass substrate (10); a layer of light-emitting elements (14) arranged on the circuit layer (12); an encapsulation layer (16) covering the light-emitting element layer (14); and a first organic film (30) covering the encapsulation layer (16), wherein a residual inorganic film (16a) extending from the encapsulation layer (16) is exposed to the outside on an externally exposed side surface (EDGE) of the display panel (PNL), wherein the residual inorganic film (16a) is thinner than the encapsulation layer (16), and wherein a section of the first organic film (30) which is arranged on the remaining inorganic film (16a) is exposed to the outside at the side surface (EDGE) of the display panel (PNL). [5] Scoreboard which includes: a glass substrate (10); a circuit layer (12) arranged on the glass substrate (10); a layer of light-emitting elements (14) arranged on the circuit layer (12); an encapsulation layer (16) arranged on the light-emitting element layer (14); and a first organic film (30) arranged on the encapsulation layer (16), wherein a section of the first organic film (30) extending from the encapsulation layer (16) is exposed to the outside on an externally exposed side surface (EDGE) of the display panel (PNL). [6] A display board according to one of the preceding claims, further comprising at least one of the following elements: a conductor interconnection pattern (18a) formed on the encapsulation layer (16), wherein the first organic film (30) covers the conductor interconnection pattern (18a); a polarizing plate (22) arranged on the first organic film (30), and / or wherein one end of the polarization plate (22) is spaced inwards or projects outwards from one end of a side surface (EDGE) of the glass substrate (10) by a predetermined separation distance, and / or wherein the polarization plate (22) and the glass substrate (10) form a stepped section on a side surface (EGDE) of the display panel (PNL). [7] Display board according to one of the preceding claims, further comprising at least one of the following elements: a touch sensor layer (18) formed on the encapsulation layer (16); and a color filter layer (20) formed on the touch sensor layer (18), and / or wherein the first organic film (30) covers a conductor interconnection pattern (18a) of the touch sensor layer (18) or covers a color filter (20) and a black matrix pattern (BM) of the color filter layer (20). [8] Display panel according to one of the preceding claims, further comprising a second organic film (11) for glass protection, which is arranged on a rear surface of the glass substrate (10), and / or wherein the circuit layer (12), the layer of light-emitting elements (14), the encapsulation layer (16) and the first organic film (30) are stacked on a front surface of the glass substrate (10), and / or the second organic film (11) for glass protection is in contact with the first organic film (30) on a side surface of the display panel (PNL), and a side surface of the extended section of the inorganic film (18) is surrounded by the second organic film (11) for glass protection and the first organic film (30). [9] Display panel according to one of the preceding claims, wherein the encapsulation layer (16) and the portion of the first organic film (30) are made of the same material and / or the thickness of the portion of the first organic film (30) is less than the thickness of the encapsulation layer (16) and / or the thickness of the first organic film (30) is greater than the thickness of the portion of the first organic film (30). [10] Display panel according to one of the preceding claims, wherein the first organic film (30) is arranged directly on the section of the first organic layer (30) in an area corresponding to the side surface (EDGE) of the display panel (PNL) which is exposed to the outside.

Images