FIELD EFFECT RANSISTOR AND METHOD FOR MANUFACTURING A FIELD EFFECT RANSISTOR
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2022-08-02
- Publication Date
- 2026-07-09
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
[0001] The present disclosure relates to a field-effect transistor and to a method for manufacturing the field-effect transistor.
[0002] JP 2019-046 908 A discloses a field-effect transistor with a trench-gate electrode. The field-effect transistor disclosed in JP 2019-046 908 A has multiple body regions, multiple interconnect regions, and multiple field relaxation regions. Each of the body regions is p-type and is located in an inter-trench semiconductor region. Each of the body regions is in contact with a gate insulating film on the side surface of the trench. An n-type drift region is in contact with the body region at the bottom of the body region. When the field-effect transistor is turned on, a channel forms in a region adjacent to the gate insulating film of each of the body regions, with the channel connecting to the drift region. Each of the interconnect regions is p-type and protrudes downward from the corresponding body region. Each of the interconnect regions extends along the trench.Each of the connection areas is positioned separately from each of the trenches. Each of the field relaxation areas is p-type and located beneath each of the connection areas. Each of the field relaxation areas is located beneath the gate electrode and extends in a direction that intersects the gate electrode. Each of the field relaxation areas is connected to the body region via the connection area. As a result, the potential of each of the field relaxation areas is stabilized.
[0003] When the field-effect transistor is switched off, a depletion layer spreads from each of the field relaxation regions into their surroundings. This depletion layer, spreading from each of the field relaxation regions, creates an electric field at the gate insulating film near the lower end of each of the grooves. Therefore, this field-effect transistor exhibits a higher breakdown voltage.
[0004] To increase channel density, trench-gate electrodes with a higher density are used. In other words, the distances between the trench-gate electrodes are small. When the distance between the trench-gate electrodes is reduced to the limit of machining accuracy, as is the case in the Fig. 15 and Fig. As shown in Figure 16, each of the connection areas 136 is in contact with a trench, i.e., a gate insulating film. In the Fig. 15 and Fig. Figure 16 shows a body region 134, a field relaxation region 138, and a drift region 140. In the structure of the Fig. 15 and Fig. 16. A channel formed in the body region is not connected to a drift region in an inter-trench semiconductor region with the junction region. In other words, no current flows in a region where the inter-trench semiconductor region is present. In the Fig. 15 and Fig. 16 only provides a portion of the inter-trench semiconductor areas as a connection area to ensure the area in which the current flows. In the Fig. 15 and Fig. 16. With respect to the field-effect transistor in the ON state, the current does not flow through the entire inter-trench semiconductor region that contains the junction. Therefore, the current is concentrated in the inter-trench semiconductor region adjacent to the inter-trench semiconductor region that contains the junction. In the field-effect transistor in each of the Fig. 15 and Fig. 16 means the permissible amount of current that can be conducted is relatively low.
[0005] The purpose of the present disclosure is to provide a field-effect transistor having multiple trench-gate electrodes arranged at a higher density, while reducing or decreasing a current concentration.
[0006] According to a first aspect of the present disclosure, a field-effect transistor comprises a semiconductor substrate, trenches, a gate insulating film, a gate electrode, and a source electrode. The trenches are arranged on an upper surface of the semiconductor substrate. The gate insulating film is arranged in each of the trenches. The gate electrode is arranged in each of the trenches. The source electrode covers the upper surface of the semiconductor substrate. The trenches each extend in a first direction along the upper surface, and the trenches are spaced apart in a direction perpendicular to the first direction. The semiconductor substrate contains several inter-trench semiconductor regions, and each of the inter-trench semiconductor regions is arranged between two adjacent trenches. The inter-trench semiconductor regions each contain source regions, contact regions, and body regions.Each of the source regions is n-type and in contact with the source electrode and the gate insulating film. Each of the contact regions is p-type and in contact with the source electrode. Each of the body regions is p-type with a lower p-type impurity concentration than each of the contact regions and is in contact with the gate insulating film on one side closer to a lower surface of the semiconductor substrate than the gate insulating film. It is also in contact with a corresponding contact region and a corresponding source region on one side closer to the lower surface of the semiconductor substrate than the contact regions and the source regions. The semiconductor substrate contains interconnect regions, each p-type, field relaxation regions, each p-type, and a drift region, which is n-type.The interconnection regions are located on a side closer to the lower surface of the semiconductor substrate than the body regions. Each interconnection region extends in a second direction that intersects the first direction in a top view of the semiconductor substrate and is spaced apart in a direction perpendicular to the second direction in the top view. The interconnection regions are connected to the body regions at intersection points where the interconnection regions and body regions intersect. The field relaxation regions are located on a side closer to the lower surface of the semiconductor substrate than the interconnection regions and the trenches.The field relaxation regions extend in a third direction that intersects the first and second directions in the plan view of the semiconductor substrate and are spaced apart in a direction perpendicular to the third direction in the plan view. The field relaxation regions are connected to the interconnect regions at intersection points where the field relaxation regions and interconnect regions intersect. The drift region is located in a first spacing section between two adjacent interconnect regions, a second spacing section between two adjacent field relaxation regions, and at a location on a side closer to the bottom surface of the semiconductor substrate than the field relaxation regions.The drift region is in contact with the body regions on one side that is closer to the lower surface of the semiconductor substrate than the body regions, and is in contact with the gate insulating film on one side that is closer to the lower surface of the semiconductor substrate than the gate insulating film.
[0007] The field relaxation zone can partially overlap the connecting zones and the ditches in one depth direction. In other words, at least one of the field relaxation zones is located below the connecting zones and at least one of the field relaxation zones is located below the ditches.
[0008] In this field-effect transistor, each of the interconnection regions extends in the second direction, intersecting the first and third directions. Each of the trenches extends in the first direction. Each of the field relaxation regions extends in the third direction. The interconnection regions are connected to the field relaxation regions at intersection points where the interconnection regions cross the field relaxation regions. Furthermore, the interconnection regions are connected to the body regions at intersection points where the interconnection regions intersect the body regions. Therefore, the field relaxation regions are connected to the body regions via the interconnection regions. As a result, the potential of each of the field relaxation regions is stabilized.When the field-effect transistor is switched on, one channel is not connected to the drift region, and no current flows at a crossover point where the connection region intersects the trench. Since the field relaxation regions extend in a direction that intersects the trenches, crossover points where the field relaxation regions intersect the trenches are scattered across the trenches. This makes it possible to inhibit the concentration of the current flowing through the specific inter-trench semiconductor region. According to the field-effect transistor described above, it is possible to inhibit the current concentration.
[0009] According to a second aspect of the present disclosure, a method for manufacturing the field-effect transistor described above includes the steps of injecting p-conducting impurities or defects into the contact areas and the interconnection areas via a common mask.
[0010] According to the method described above, it is possible to manufacture the field-effect transistor efficiently.
[0011] Further tasks, features, and advantages of the present disclosure are more clearly evident from the following detailed description with reference to the accompanying drawings. The drawings show: Fig. 1 a perspective cross-sectional view of a metal-oxide-semiconductor field-effect transistor (MOSFET) according to an embodiment and furthermore an upper surface of a semiconductor substrate, a cross-section of a semiconductor substrate of the MOSFET along the xz-plane and a cross-section of the semiconductor substrate along the yz-plane; Fig. 2 a top view of the upper surface of the semiconductor substrate of the MOSFET according to the embodiment; Fig. 3 a cross-sectional view of the MOSFET according to the embodiment along the xz-plane on line III-III of Fig. 2; Fig. 4 a cross-sectional view of the MOSFET according to the embodiment along the xz-plane on line IV-IV of Fig. 2; Fig. 5 a cross-sectional view of the MOSFET according to the embodiment along the yz-plane on line VV of Fig. 2; Fig. 6 a cross-sectional view of the MOSFET according to the embodiment along the yz-plane on line VI-VI of Fig. 2; Fig. 7 a perspective cross-sectional view of the MOSFET according to the embodiment and furthermore a cross-section of an area of the MOSFET including a connection area along the xy-plane, a cross-section of the MOSFET along the xz-plane and a cross-section of the MOSFET along the yz-plane; Fig. 8 a top view of an arrangement of the trench, the interconnection area and a field relaxation area in a top view of the semiconductor substrate; Fig. 9 a channel and a current path from Fig. 3; Fig. 10. A top view of a MOSFET according to a comparative example, which Fig. 2 corresponds to; Fig. 11 a method for manufacturing the MOSFET according to the embodiment; Fig. 12 A top view of a MOSFET according to a first modification of the in Fig. 8 MOSFETs shown; Fig. 13 A top view of a MOSFET according to a second modification of the in Fig. 8 MOSFETs shown; Fig. 14 A top view of a MOSFET according to a third modification of the in Fig. 3 MOSFETs shown; Fig. 15 a cross-sectional view of a MOSFET according to a comparative example; and Fig. 16 A top view of the MOSFET according to the comparison example.
[0012] Below is a metal-oxide-semiconductor field-effect transistor (MOSFET) 10 according to an embodiment with reference to the Fig. 1 to Fig. 5 described. The MOSFET 10 can also simply be referred to as a field-effect transistor. In the following, a direction parallel to an upper surface 12a of a semiconductor substrate 12 can also be referred to as the x-direction, a thickness direction of the semiconductor substrate 12 can also be referred to as the z-direction, and a direction perpendicular to the x-direction and the z-direction can also be referred to as the y-direction. The semiconductor substrate 12 is made of silicon carbide (SiC). However, the semiconductor substrate 12 can also be made of another material such as silicon or gallium nitride. In Fig. Figure 1 lacks a representation of a source electrode 22, which is arranged on the upper surface 12a of the semiconductor substrate 12.
[0013] As in the Fig. 1 and Fig. Figure 2 shows several trenches 14 arranged on the upper surface 12a of the semiconductor substrate 12. The trenches 14 extend in the y-direction along the upper surface 12a. The trenches 14 are arranged such that they are spaced apart from each other in the x-direction.
[0014] As in the Fig. 1 to Fig. As shown in Figure 5, the inner surface of each of the grooves 14 is covered with a gate insulating film 16. The inner surface can also be referred to as the bottom surface and side surface of each of the grooves 14. A gate electrode 18 is arranged in each of the grooves 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. As shown in the Fig. 3 to Fig. As shown in Figure 5, the upper surface of the gate electrode 18 is covered with an intermediate insulating film 20.
[0015] As in the Fig. 3 to Fig. As shown in Figure 6, the source electrode 22 is located on the top surface of the semiconductor substrate 12. The source electrode 22 covers the interlayer insulating film 20. The source electrode 22 is insulated from the gate electrodes 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the top surface 12a of the semiconductor substrate 12 at a section where the interlayer insulating film 20 is not present. A drain electrode 24 is located on the bottom surface of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire area of the bottom surface 12b of the semiconductor substrate 12.
[0016] As in the Fig. 1, Fig. 3 and Fig. As shown in Figure 4, the semiconductor substrate contains 12 inter-trench semiconductor regions 26, each located between the trenches 14. Each inter-trench semiconductor region 26 extends in the y-direction along the trench 14. A source region 30, a contact region 32, and a body region 34 are provided in each of the inter-trench semiconductor regions 26.
[0017] As in the Fig. 1 to Fig. As shown in Figure 4, several source regions 30 and several contact regions 32 are provided in a region that encloses the upper surface 12a of the semiconductor substrate 12. Each of the source regions 30 is n-type and exhibits a relatively high concentration of n-type impurities. Each of the contact regions 32 is p-type and exhibits a relatively high concentration of p-type impurities. As shown in the Fig. 3 and Fig. As shown in Figure 4, the source areas 30 and the contact areas 32 are in ohmic contact with the source electrode 22. As shown in the Fig. 1 and Fig. As shown in Figure 2, each of the source regions 30 and each of the contact regions 32 has a rectangular shape in a direction 100 that obliquely intersects the longitudinal direction of each of the grooves 14, i.e., in the y-direction. The source regions 30 and the contact regions 32 are arranged alternately in a direction perpendicular to the direction 100. In other words, the contact regions 32 are arranged at intervals in a direction perpendicular to the direction 100 and extend in the direction 100 that intersects the y-direction in the top view of the semiconductor substrate 12, as shown in Figure 2. Fig. Figure 2 shows that the source regions 30 are arranged at intervals in a direction perpendicular to direction 100 and extend in direction 100, which intersects the y-direction in the top view of the semiconductor substrate 12, as shown in Fig. Figure 2 shows the source area 30 being arranged between the contact areas 32, and the contact area 32 is arranged between the source areas 30. As shown in the Fig. 1 and Fig. As shown in Figure 3, each of the source areas 30 is in contact with the gate insulating film 16 at the uppermost part of the side surface of the trench 14. Each of the contact areas 32 is in contact with the gate insulating film 16 at the uppermost part of the side surface of the trench 14.
[0018] Each of the body regions 34 is p-conducting and exhibits a lower p-conducting impurity concentration than the contact region 32. As in the Fig. 1, Fig. 3, Fig. 4 and Fig. As shown in Figure 6, the body regions 34 are arranged beneath the source regions 30 and the contact regions 32. In each of the inter-trench semiconductor regions 26, each of the body regions 34 is distributed along the entire x- and y-directions. The body regions 34 are each in contact with the source regions 30 and the contact regions 32, specifically beneath them. Each of the body regions 34 is in contact with the gate insulating film 16 on the side surface of the trench 14, which is located beneath the source region 30 and the contact region 32.
[0019] As in the Fig. 3 to Fig. As shown in Figure 6, the semiconductor substrate 12 contains several interconnection areas 36, several field relaxation areas 38, a drift area 40, a buffer area 42 and a drain area 44.
[0020] Each of the connection areas 36 is p-conducting and exhibits a higher p-conducting defect concentration than body area 34. As in the Fig. 1 and Fig. 3 to Fig. As shown in Figure 6, the connecting areas 36 are arranged below the body areas 34. Fig. As shown in Figure 7, the connection areas 36 extend in the top view onto the semiconductor substrate 12 in a direction 100 that obliquely intersects the y-direction. The connection areas 36 are arranged at intervals in the top view onto the semiconductor substrate 12 in a direction perpendicular to the direction 100. As shown in the Fig. 1 and Fig. As shown in Figure 3, each of the connection areas 36 is located directly below the corresponding contact area 32. Therefore, each of the contact areas 32 extends in the direction 100 to overlap the corresponding connection area 36 in the top view of the semiconductor substrate 12. As shown in the Fig. 3, Fig. 4 and Fig. As shown in Figure 6, the connecting areas 36 are connected to the body areas 34 at intersection sections 35, each of which intersects the body areas 34. The connecting areas 36 extend downwards from the lower surface of each of the body areas 34 to a position lower than the lower end of each of the body areas 34. Each of the connecting areas 36 is in contact with the gate insulating film 16 on the side surface of the trench 14, which is located below the body areas 34.
[0021] Each of the field relaxation areas 38 is p-conducting. Each of the field relaxation areas 38 exhibits a p-conducting impurity concentration that is higher than that of the body areas 34, but lower than that of the connection areas 36. As in the Fig. 1, Fig. 3, Fig. 5 and Fig. As shown in Figure 6, the field relaxation areas 38 are arranged below the connection area 36. As shown in the Fig. 1 and Fig. As shown in Figure 8, each of the field relaxation regions 38 has an elongated shape in the x-direction. In other words, each of the field relaxation regions 38 extends in the x-direction, intersecting the y-direction and direction 100 in the top view of the semiconductor substrate 12. The y-direction corresponds to the longitudinal direction of the trench 14, and direction 100 corresponds to the longitudinal direction of the interconnection region 36. The field relaxation regions 38 are arranged at intervals in the y-direction perpendicular to the x-direction. As shown in the Fig. 3, Fig. 5 and Fig. As shown in Figure 6, an upper end section of each of the field relaxation areas 38 is arranged in a depth region that overlaps a lower end section of the connection region 36. The field relaxation areas 38 are connected to the connection regions 36 at intersection sections 37, each of which intersects the connection region 36. The field relaxation areas 38 are connected to the source electrode 22 via the connection regions 36, the body regions 34, and the contact regions 32.
[0022] The drift region 40 is n-conducting. As in the Fig. 1 and Fig. 3 to Fig. As shown in Figure 6, the drift area 40 is distributed from a position in contact with the lower surface of each of the body regions 34 to a position below the field relaxation regions 38. In other words, the drift area 40 is distributed in a distance section 36x between the connection regions 36, a distance section 38x between the field relaxation regions 38, and a region below the field relaxation regions 38. Within the distance section 36x between the connection regions 36, the drift area 40 is in contact with the lower surface of the body region 34. Within the distance section 36x, the drift area 40 is in contact with the gate insulating film 16 on the side surface of the trench 14 and the lower surface of the trench 14, which is located below the corresponding body region 34. The drift area 40 includes a high concentration region 40a and a low concentration region 40b.The n-conducting impurity concentration of the high-concentration area 40a is higher than the n-conducting impurity concentration of the low-concentration area 40b. In other words, the high-concentration area 40a is distributed in the distance section 36x between the connection areas 36, a distance section 38x between the field relaxation areas 38, and an area below the field relaxation areas 38. The low-concentration area 40b is located below the high-concentration area 40a. The low-concentration area 40b is in contact with the high-concentration area 40a.
[0023] Buffer zone 42 is n-conducting and exhibits a higher concentration of n-conducting impurities than the low-concentration zone 40b of drift zone 40. Viewed from below, buffer zone 42 is in contact with the low-concentration zone 40b.
[0024] The drain region 44 is n-type and exhibits a higher concentration of n-type impurities than the buffer region 42. Viewed from below, the drain region 44 is in contact with the buffer region 42. The drain region 44 is located in a region that includes the lower surface 12b of the semiconductor substrate 12. The drain region 44 is in ohmic contact with the drain electrode 24 on the lower surface 12b.
[0025] When using MOSFET 10, the drain electrode 24 has a higher potential than the source electrode 22. If a potential above a threshold value is applied to the gate electrode 18, a channel 50 forms in the body region 34 near the gate insulating film 16, as shown in Fig. 9 is shown. Channel 50 connects the source area 30 and the drift area 40. As indicated by arrow 102 in Fig. As illustrated in Figure 9, electrons flow from the source region 30 through the channel 50 to the drift region 40. Therefore, the electrons flow from the source electrode 22 through the source region 30, the channel 50, the drift region 40 and the buffer region 42 to the drain electrode 24.
[0026] When the potential of each of the gate electrodes 18 is reduced from a value equal to or greater than a gate threshold to a value below the gate threshold, channel 50 disappears and the electron flow stops. In other words, the MOSFET 10 is switched off, or cut off. When channel 50 disappears, the potential of the drift region 40 increases. Conversely, since the body regions 34 are connected to the source electrode 22 via the contact regions 32, the potential of each of the body regions 34 is maintained at a potential that is essentially identical to that of the source electrode 22, i.e., at a relatively low potential. When channel 50 disappears, the pn junction at the interface between the corresponding body region 34 and the drift region 40 is subjected to a reverse bias. Therefore, the depletion region spreads from the body region 34 into the drift region 40.The field relaxation regions 38 are connected to the source electrode 22 via the connection regions 36, the body regions 34, and the contact regions 32. Therefore, the potential of each of the connection regions 36 is also maintained at a potential that is essentially identical to that of the source electrode 22, i.e., at a relatively low potential. When the channel 50 disappears, the blocking voltage is applied to the pn junction of the interface between the corresponding field relaxation region 38 and the drift region 40, and the depletion layer propagates from the corresponding field relaxation region 38 into the drift region 40. The depletion layer propagating from the corresponding field relaxation region 38 rapidly depletes the drift region 40 around the lower end of the trench 14. This inhibits the concentration of the electric field around the lower end of the trench 14.
[0027] In the MOSFET 10 of the present embodiment, as described in Fig. As shown in Figure 8, it is possible to ensure the connection of the field relaxation areas 38 to the body areas 34 via the connection areas 36, since each of the connection areas 36 extends in a direction that intersects the field relaxation areas 38. Therefore, the barrier layer spreads easily from the corresponding field relaxation area 38 to the drift area 40 to effectively suppress the concentration of the electric field at the lower end of the corresponding trench 14.
[0028] In the MOSFET 10 of the present embodiment, as described in Fig. As shown in Figure 8, it is possible to suppress the concentration of the electric field when the MOSFET 10 is switched on, since each of the connection regions 36 extends in a direction that intersects the trenches 14. The suppression of the electric field concentration is described below. As shown in Fig. As shown in Figure 9, in an overlap section where the connection area 36 overlaps the trench 14, the channel 50 formed at the body area 34 is not connected to the drift area 40, since the connection area 36 is located below the body area 34. Therefore, no current flows through the channel 50 in the overlap section where the connection area 36 overlaps the trench 14. Since, in the present embodiment, as shown in Figure 9, the connection area 36 is located below the body area 34, the channel 50 is not connected to the drift area 40. Fig. As shown in Figure 8, each of the connection areas 36 extends in a direction that intersects the trenches 14. The overlap section in which the connection area 36 overlaps the trench 14 is arranged such that it is scattered over the trenches 14. In other words, in the MOSFET 10 of the present embodiment, there is no situation in which the entire side surface of a specific trench overlaps the connection area 136, as shown in the Fig. 15 and Fig. 16 shown. As in the Fig. 15 and Fig. As shown in Figure 16, the current concentrates in the channel adjacent to the overlap section when the entire side surface of the specific trench overlaps with the connection area 136. In contrast, in the MOSFET 10 of the present embodiment, as shown in Fig. Figure 8 illustrates that the overlap section, where the connection area 36 overlaps the trench 14, is dispersed across the trenches 14. The area where current does not flow is dispersed, and current concentration does not readily occur. The overlap section corresponds to an intersection section. Since, in the present embodiment, each of the connection areas 36 cuts the trenches 14 obliquely, the overlap section, i.e., the intersection section, is dispersed along the longitudinal direction of the trench 14. The MOSFET 10 of the present embodiment suppresses current concentration. For this reason, the MOSFET of the present embodiment has a higher permissible current that can be conducted.
[0029] In the MOSFET 10 of the present embodiment, each of the contact areas 32 is arranged in a position that overlaps the corresponding connection area 36 in the top view of the semiconductor substrate 12. This reduces the on-resistance of the MOSFET 10. The reduction of the on-resistance is described below. As in Fig. As shown in Figure 9, in an overlap section where the contact area 32 overlaps the trench 14, the channel 50 formed in the body area 34 is not connected to the source area 30, since the contact area 32 is located above the body area 34. Therefore, no current flows through the channel 50 in the overlap section where the contact area 32 overlaps the trench 14. If the connection area 36 and the contact area 32 extend in different directions, the overlap section where the contact area 32 overlaps the trench 14 and the overlap section where the connection area 36 overlaps the trench 14 are formed at different positions, as in the MOSFET according to the comparative example of Figure 9. Fig. 10. Each of the overlap regions described above corresponds to a section where current does not flow through the channel. For this reason, the area where current can flow is narrow. In contrast, in the MOSFET 10 of the present embodiment, the contact region 32 and the interconnection region 36 extend in the direction 100 in the overlap state. In a top view of the semiconductor substrate 12, the position of the intersection section where the contact region 32 intersects the trench 14 is essentially the same as the position of the intersection section where the interconnection region 36 intersects the trench 14. This allows for a larger area where current can flow. Consequently, the MOSFET 10 of the present embodiment has a relatively low on-resistance.
[0030] In the MOSFET 10 of the present embodiment, each of the connection areas 36 crosses the trench 14 obliquely. As in Fig. As shown in Figure 8, the distance W1 between the connection areas 36 is narrower than the distance W2 between the connection areas 36 in one direction along the trench 14. When a higher voltage is applied to the MOSFET 10 in the OFF state, the barrier layer spreads from the corresponding connection area 36 into the drift area 40 around the connection area 36, and the voltage is maintained by the barrier layer. Since the distance W1 is narrow, the drift area 40 within the area of distance W1 is slightly depleted by the barrier layer spreading from the corresponding connection area 36. According to the structure described above, it is possible to increase the breakdown voltage, i.e., the dielectric strength of the MOSFET 10. If the distance W2 is larger in one direction along the trench 14, it can be ensured that a larger area (i.e.,The trench 14 (in an area that does not overlap the connection area 36) is present, allowing current to flow through the channel. This makes it possible to reduce the on-resistance of the MOSFET. As described above, this structure allows for a higher breakdown voltage and a lower on-resistance.
[0031] A method for manufacturing the MOSFET 10 according to the present embodiment is described below. Since this manufacturing method has features in the formation of the contact area 32 and the connection area 36, the formation of both the contact area 32 and the connection area 36 is described below.
[0032] In the formation of both the contact area 32 and the connection area 36, as in Fig. As shown in Figure 11, a mask 90 is formed on the upper surface 12a of the semiconductor substrate 12. The mask 90 is formed such that an opening 92 is located on an upper section of a region corresponding to the contact area 32 and the connection area 36. Subsequently, p-type impurity ions are implanted into the semiconductor substrate 12 via the mask 90. By changing the ion implantation energy, the p-type impurities are injected into a depth region of the connection area 36 and into a depth region of the contact area 32. The connection area 36 and the contact area 32 are then formed by activation annealing of the impurities. In this manufacturing process, it is possible to form the connection area 36 and the contact area 32 by ion implantation using the common mask 90. This makes it possible to efficiently fabricate the MOSFET 10. (First modification)
[0033] In the MOSFET 10 according to the embodiment above, the side surface of each of the connection regions 36 extends linearly in the direction 100. In a first modification of the present disclosure, for example, the side surface of each of the connection regions 36 can extend while bending in the direction 100, as shown in Fig. 12. However, in a region closer to the limit of semiconductor processing accuracy, particularly pattern exposure accuracy, the difference in the respective shapes of the interconnection regions becomes greater when the interconnection region 36 is formed such that one side surface is curved, as in Fig. 12 shown. In contrast, if the side surface of each of the connection areas 36 extends linearly in the direction 100, as in Fig. As shown in Figure 8, it is possible to form each of the connection areas 36 with higher precision, and it is possible to suppress the differences in the properties of the MOSFET 10. (Second modification)
[0034] In the above-mentioned embodiment, as in Fig. As shown in Figure 8, in the top view of the semiconductor substrate 12, the field relaxation region 38 extends in a direction perpendicular to the trench 14. However, as shown in Fig. As shown in Figure 13, the field relaxation area 38 could extend in a direction oblique to the trench 14 according to a second modification of the present disclosure. (Third modification)
[0035] In the above embodiment, the distance between the field relaxation area 38 and the lower end of the trench 14 is provided as shown in Fig. 3 shown. However, according to a third modification of the present disclosure, the field relaxation area 38 could be Fig.14 shown, with the lower end of trench 14 in contact.
[0036] The y-direction described in this embodiment corresponds to a first direction. The direction 100 described in this embodiment corresponds to a second direction. The x-direction described in this embodiment corresponds to a third direction.
[0037] In the field-effect transistor described in the present disclosure, each of the contact areas can extend in the second direction to overlap with a corresponding connection area in a top view of a semiconductor substrate.
[0038] When the field-effect transistor is switched on, i.e., conducting, no channel is connected to a source electrode, and no current flows through the section where each contact area intersects the trenches. Since each contact area overlaps the corresponding connection area, the section where no current flows lies on top of each other. In other words, the intersection section where the connection area intersects the trench and the intersection section where the corresponding contact area intersects the corresponding trench overlap. Therefore, it is possible to reduce the area where current does not flow. This, in turn, makes it possible to reduce the on-resistance of the field-effect transistor.
[0039] In the field-effect transistor described in the present disclosure, the second direction can intersect obliquely with respect to a first direction.
[0040] According to the structure mentioned above, the intersection sections, where the connecting areas each cross the trenches, are scattered along a longitudinal direction of the trenches. This longitudinal direction corresponds to the first direction. Therefore, it is possible to effectively alleviate the current concentration.
[0041] In the field-effect transistor described in the present disclosure, each of the interconnection areas has a side surface with a linear shape that can extend in the second direction.
[0042] This makes it possible to stabilize the properties of the field-effect transistor.
[0043] Although the embodiments are described in detail above, these serve only as examples and do not limit the scope of this disclosure. The techniques described in this disclosure include various modifications and adaptations of the specific examples shown above. The technical elements described in this disclosure or in the drawings have technical benefits, either individually or in various combinations, and are not limited to the combinations described in this disclosure at the time of filing. Furthermore, the techniques presented herein solve several problems simultaneously, the solution of only one of which is itself of technical benefit. QUOTES INCLUDED IN THE DESCRIPTION
[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature
[0000] JP 2019046908 A
[0002]
Claims
[1] Field-effect transistor with: - a semiconductor substrate (12); - several trenches (14) arranged on an upper surface of the semiconductor substrate; - a gate insulating film (16) arranged in each of the trenches; - a gate electrode (18) arranged in each of the trenches; and - a source electrode (22) covering the upper surface of the semiconductor substrate, wherein - the trenches each extend in a first direction along the upper surface, and the trenches are spaced apart in a direction perpendicular to the first direction, - the semiconductor substrate has several inter-trench semiconductor regions (26), and each of the inter-trench semiconductor regions is arranged between two adjacent trenches, - the inter-trench semiconductor regions each have multiple source regions (30), multiple contact regions (32) and multiple body regions (34), - each of the source areas is n-conducting and in contact with the source electrode and the gate insulating film, - each of the contact areas is p-conducting and in contact with the source electrode, - each of the body areas is p-conducting and has a lower p-conducting impurity concentration than each of the contact areas, - each of the body areas is in contact with the gate insulating film on a side that is closer to a lower surface of the semiconductor substrate than the source areas, and is in contact with a corresponding contact area and a corresponding source area on a side that is closer to the lower surface of the semiconductor substrate than the contact areas and the source areas, - the semiconductor substrate further exhibits: - several interconnection areas (36), each of which is p-conducting; - several field relaxation areas (38), each of which is p-conducting; and - a drift region (40) that is n-conducting, wherein - the connection areas are arranged on a side that is closer to the lower surface of the semiconductor substrate than the body areas, - the interconnection areas each extend in a second direction that intersects the first direction in a top view of the semiconductor substrate, and are arranged such that they are spaced apart from each other in a direction perpendicular to the second direction in the top view of the semiconductor substrate, - the connecting areas are connected to the body areas at intersection sections where the connecting areas intersect with the body areas, - the field relaxation regions are arranged on a side that is closer to the lower surface of the semiconductor substrate than the interconnection regions and the trenches, - the field relaxation regions extend in a third direction that intersects the first direction and the second direction in the top view of the semiconductor substrate, and are arranged such that they are spaced apart from each other in a direction perpendicular to the third direction in the top view of the semiconductor substrate, - the field relaxation areas are connected to the connection areas at intersection sections where the field relaxation areas intersect with the connection areas, - the drift region is arranged at a first spacing section (36x) between two adjacent interconnection regions, a second spacing section (38x) between two adjacent field relaxation regions, and a location closer to the lower surface of the semiconductor substrate than the field relaxation regions, and - the drift area is in contact with the body areas on one side that is closer to the lower surface of the semiconductor substrate than the body areas, and is in contact with the gate insulating film on one side that is closer to the lower surface of the semiconductor substrate than the gate insulating film. [2] Field-effect transistor according to claim 1, wherein each of the contact areas extends in the second direction to overlap a corresponding connection area in the top view of the semiconductor substrate. [3] Field-effect transistor according to claim 1 or 2, wherein the second direction is inclined to the first direction. [4] Field-effect transistor according to one of claims 1 to 3, wherein each of the connection areas has a side surface with a linear shape extending in the second direction. [5] Method for manufacturing a field-effect transistor, the method comprising the following steps: - Injecting p-type impurities into multiple contact areas of a semiconductor substrate and multiple interconnection areas of the semiconductor substrate via a common mask, wherein - the field-effect transistor exhibits: - the semiconductor substrate (12); - several trenches (14) arranged on an upper surface of the semiconductor substrate; - a gate insulating film (16) arranged in each of the trenches; - a gate electrode (18) arranged in each of the trenches; and - a source electrode (22) covering the upper surface of the semiconductor substrate, wherein - the trenches each extend in a first direction along the upper surface, and the trenches are spaced apart in a direction perpendicular to the first direction, - the semiconductor substrate has several inter-trench semiconductor regions (26), and each of the inter-trench semiconductor regions is arranged between two adjacent trenches, - the inter-trench semiconductor regions each have several source regions (30), contact regions (32) and several body regions (34), - each of the source areas is n-conducting and in contact with the source electrode and the gate insulating film, - each of the contact areas is p-conducting and in contact with the source electrode, - each of the body areas is p-conducting and has a lower p-conducting impurity concentration than each of the contact areas, - each of the body areas is in contact with the gate insulating film on a side that is closer to a lower surface of the semiconductor substrate than the source areas, and is in contact with a corresponding contact area and a corresponding source area on a side that is closer to the lower surface of the semiconductor substrate than the contact areas and the source areas, - the semiconductor substrate further exhibits: - the connecting areas (36), each of which is p-conducting; - several field relaxation areas (38), each of which is p-conducting; and - a drift region (40) that is n-conducting, wherein - the connection areas are arranged on a side that is closer to the lower surface of the semiconductor substrate than the body areas, - the interconnection areas each extend in a second direction that intersects the first direction in a top view of the semiconductor substrate, and are arranged such that they are spaced apart from each other in a direction perpendicular to the second direction in the top view of the semiconductor substrate, - the connecting areas are connected to the body areas at intersection sections where the connecting areas intersect with the body areas, - the field relaxation regions are arranged on a side that is closer to the lower surface of the semiconductor substrate than the interconnection regions and the trenches, - the field relaxation regions extend in a third direction that intersects the first direction and the second direction in the top view of the semiconductor substrate, and are arranged such that they are spaced apart from each other in a direction perpendicular to the third direction in the top view of the semiconductor substrate, - the field relaxation areas are connected to the connection areas at intersection sections where the field relaxation areas intersect with the connection areas, - the drift region is located in a first spacing section (36x) between two adjacent interconnection regions, a second spacing section (38x) between two adjacent field relaxation regions, and a location on one side that is closer to the lower surface of the semiconductor substrate than the field relaxation regions, and - the drift area is in contact with the body areas on one side that is closer to the lower surface of the semiconductor substrate than the body areas, and is in contact with the gate insulating film on one side that is closer to the lower surface of the semiconductor substrate than the gate insulating film.