Piezoresistive transistor device and electronic power module with a piezoresistive transistor device

Abstract

Piezoresistive transistor power device comprising: a first transistor cell (210) with a first body (120_1) of piezoelectric material, and a first body (140_1) of piezoresistive material, wherein the first body (120_1) of piezoelectric material and the first body (140_1) of piezoresistive material are arranged in a stacked configuration, and a first electrical resistance of the first body (140_1) of piezoresistive material depends on a voltage applied across the first body (120_1) of piezoelectric material by means of a pressure exerted by the first body (120_1) of piezoelectric material on the first body (140_1) of piezoresistive material;a second transistor cell (220) comprising a second body (120_2) of piezoelectric material and a second body of piezoresistive material, wherein the second body (120_2) of piezoelectric material and the second body (140_2) of piezoresistive material are arranged in a stacked configuration, and a second electrical resistance of the second body of piezoresistive material depends on a voltage applied across the second body of piezoelectric material by means of a pressure exerted by the second body (120_2) of piezoelectric material on the second body (140_2) of piezoresistive material; a control terminal (150) of the piezoresistive transistor power device; a first load terminal (160) of the piezoresistive transistor power device; a second load terminal (170) of the piezoresistive transistor power device;and an internal electrical connection of the piezoresistive transistor power device configured to electrically connect the first electrical resistance and the second electrical resistance in parallel.

Description

Technical area

[0001] This disclosure relates generally to the field of transistor devices and in particular to piezoresistive transistor devices. background

[0002] The most common transistor type is the MOSFET (metal-oxide-semiconductor field-effect transistor). MOSFETs exploit the special properties of semiconductor materials, enabling small electrical voltage signals to control the switching of sometimes much larger current signals. Over the years, MOSFETs have achieved enormous improvements in power density, breakdown strength, and reliability, but they face the ongoing challenge of minimizing losses, failure rates, and power densities, as well as improving their thermal and dynamic behavior.

[0003] A conventional way to achieve these performance characteristics is miniaturization. Although such MOSFET devices have excellent adaptability to be tailored for various applications, such advances in design go hand in hand with developments in other areas such as efficiency and cost.

[0004] Field-effect transistors are controlled by independent carrier particles (electrons or holes) that thermally overcome a potential barrier, their carrier statistics being explained by Boltzmann statistics. In contrast, a Mott transistor utilizes a transition from the insulator to the metal (Mott junction) in the channel. A Mott transistor can operate at low gate voltages because the Mott junction can be induced by a small change in the gate voltage. More precisely, in a Mott transistor, the gate voltage is converted into an internal state (pressure) that is switched on and then converted back into a voltage at the output. This operating principle does not require thermionic emission of charge carriers across a barrier (as is the case with MOSFETs) and therefore avoids the fundamental limitations and problems of MOSFETs. However, existing Mott transistors are limited to low-voltage switching. Brief description

[0005] According to one aspect of the disclosure, a piezoresistive transistor device comprises a first transistor cell. The first transistor cell comprises a first body made of piezoelectric material and a first body made of piezoresistive material. The first body made of piezoelectric material and the first body made of piezoresistive material are arranged in a stacked configuration, and the first electrical resistance of the first body made of piezoresistive material is dependent on a voltage applied across the first body made of piezoelectric material by means of a pressure exerted on the first body made of piezoelectric material. The piezoresistive transistor device comprises a second transistor cell. The second transistor cell comprises a second body made of piezoelectric material and a second body made of piezoresistive material.The second body made of piezoelectric material and the second body made of piezoresistive material are arranged in a stacked configuration. The resistance of the second body made of piezoresistive material is controlled by a pressure exerted on it by the second body made of piezoelectric material, which in turn depends on a voltage applied across the second body made of piezoelectric material. The piezoresistive transistor device includes a control terminal, a first load terminal, a second load terminal, and an internal electrical connection configured to connect the first and second resistances electrically in series or parallel.

[0006] According to another aspect of the disclosure, a piezoresistive transistor device comprises a first plurality of transistor cells and a second plurality of transistor cells. Each transistor cell comprises a body of piezoelectric material and a body of piezoresistive material, wherein the body of piezoelectric material and the body of piezoresistive material are arranged in a stacked configuration, and the electrical resistance of the body of piezoresistive material depends, by means of a pressure exerted by the body of piezoelectric material on the body of piezoresistive material, on a voltage applied across the body of piezoelectric material.The piezoresistive transistor device further comprises a control terminal, a first load terminal, a second load terminal and an internal electrical connection configured to electrically connect the electrical resistances of the first plurality of transistor cells in series, electrically connect the electrical resistances of the second plurality of transistor cells in series and electrically connect these two series circuits in parallel.

[0007] According to another aspect of the disclosure, an electronic power module comprises a piezoresistive transistor device as described above and a carrier on which the piezoresistive transistor device is mounted. The electronic power module further comprises a heat sink attached to the carrier.

[0008] According to another aspect of the disclosure, a piezoresistive transistor device comprises a first transistor cell. The first transistor cell comprises a body made of piezoelectric material and a first body made of piezoresistive material. The body made of piezoelectric material and the first body made of piezoresistive material are arranged in a stacked configuration. The first electrical resistance of the first body made of piezoresistive material is dependent on a voltage applied across the body made of piezoelectric material by means of a pressure exerted on the first body made of piezoresistive material. The piezoresistive transistor device also comprises a second transistor cell. The second transistor cell comprises the body made of piezoelectric material and a second body made of piezoresistive material.The first body, made of piezoelectric material, and the second body, made of piezoresistive material, are arranged in a stacked configuration. The electrical resistance of the second body, measured by the pressure exerted on it by the first body, depends on the voltage applied across it. The first and second bodies are oriented in different, non-parallel spatial planes. Brief description of the drawings

[0009] In the drawings, identical reference numerals denote identical or similar elements. The features of the various embodiments shown may be combined, provided they are not mutually exclusive, and / or they may be selectively omitted if they are not described as absolutely necessary. The embodiments are illustrated in the drawings and are further explained by way of example in the following description. Fig. Figure 1A is a perspective view of an exemplary piezoresistive transistor device with a layer or body stack containing a body of piezoelectric material and a body of piezoresistive material. Fig. Figure 1B is a side view of an exemplary piezoresistive transistor device with a layer or body stack, such as that shown in e.g. Fig. 1A is shown. Fig. Figure 2 is a perspective view of an internally parallel connected exemplary piezoresistive transistor device with a layer or body stack containing a body of piezoelectric material and a first and a second body of piezoresistive material. Fig. Figure 3A is a perspective view of an internally series-connected piezoresistive transistor device according to a first series-connection concept. Fig. 3B is a perspective view of an internally series-connected piezoresistive transistor device according to a second series connection concept. Fig. Figure 4 is a perspective view of an internally parallel connected piezoresistive transistor device with a layer or body stack containing a body of piezoelectric material and a plurality of bodies of piezoresistive material. Fig. Figure 5 is a perspective view of an internally parallel connected piezoresistive transistor device with a layer or body stack containing a plurality of bodies of piezoelectric material and a plurality of bodies of piezoresistive material. Fig. Figure 6 is a perspective view of an internally series-connected piezoresistive transistor device according to the first series-connection concept of the Fig. 3A. Fig. Figure 7 is a perspective view of an internally serially and parallel-connected piezoresistive transistor device, where the internal serial connections correspond to the first series connection concept of Fig. 3A corresponds. Fig. Figure 8 is a perspective view of an example of a piezoresistive transistor device with the exemplary layer or body stack of the Fig. 4, which is housed in a housing structure with an upper metal plate and a lower metal plate. Fig. Figure 9 shows perspective views of a package with multiple housing structures. Fig. 8. Fig. Figure 10A is a side view or sectional representation of a housing structure with cavities for receiving transistor cells, wherein the cavities are arranged side by side with respect to a lateral dimension of the housing structure. Fig. Figure 10B is a side view or sectional representation of another housing structure with cavities for receiving transistor cells, wherein the cavities are arranged side by side with respect to a lateral dimension of the housing structure. Fig. Figure 11A is a perspective view of an exemplary piezoresistive transistor device with a layer or body stack in which a first transistor cell and a second transistor cell are oriented in different spatial directions. Fig. Figure 11B shows a device with a plurality of layer or body stacks, as in Fig. 11A is shown. Fig. Figure 12 shows an electronic power module with a piezoresistive transistor device, a carrier on which the piezoresistive transistor device is mounted, and a heat sink attached to the carrier. Fig. Figure 13 shows an arrangement of electronic power modules arranged in a row. Fig. Figure 14 is a perspective view of an exemplary piezoresistive transistor device in which a first transistor cell and a second transistor cell are oriented in different spatial directions. Detailed description

[0010] It is understood that the features of the various embodiments and examples described here can be combined with each other, unless expressly stated otherwise.

[0011] As used in this description, the terms “electrically connected” or “connected” or similar terms are not to be understood as meaning that the elements are in direct contact with one another; intermediate elements may be provided between the “electrically connected” or “connected” elements. However, in accordance with the disclosure, the above and similar terms may optionally also have the specific meaning that the elements are in direct contact with one another, i.e., that no intermediate elements are provided between the “electrically connected” or “connected” elements.

[0012] Furthermore, the words "over" or "under" can be used here in reference to a part, element, layer, or body of material that is formed or arranged "over" or "under" a surface to mean that the part, element, layer, or body of material is arranged (e.g., placed, formed, arranged, deposited, etc.) "directly on" or "directly under," i.e., in direct contact with the designated surface. However, the word "over" or "under" used here in reference to a part, element, layer, or body of material that is formed or arranged "over" or "under" a surface can also be used here to mean that the part, element, layer, or body of material is arranged (e.g., placed, formed, arranged, deposited, etc.) "indirectly on" or "indirectly under" the designated surface.) is, wherein one or more additional parts, elements, material layers or material bodies are arranged between the designated surface and the part, element, material layer or material body.

[0013] The Fig. 1A and Fig. Figure 1B shows an example of a Mott field-effect transistor (MottFET) device 100. The MottFET device 100 comprises a transistor cell having a body made of piezoelectric material (PE) 120 (which may, for example, have the form of a layer, a beam, or a cube) and a body made of piezoresistive material (PR) 140 (which may, for example, have the form of a layer). The PE material body 120 and the PR material body 140 are arranged in a stacked configuration.

[0014] The MottFET device 100 includes a control terminal 150, which is referred to as the gate terminal (G), a first load terminal 160, which is referred to as the common terminal (C), and a second load terminal 170, which is referred to as the source terminal (S).

[0015] Furthermore, the MottFET device 100 can include a control metal layer 152, a first metal layer 162, and a second metal layer 172. The control metal layer 152 can be arranged on the underside of the PE material body 120 and electrically coupled to the control terminal 150. The first metal layer 162 can be arranged between the PE material body 120 and the PR material body 140 and electrically coupled to the first load terminal 160. The second metal layer 172 can be arranged on the top side of the PR material body 140 and electrically coupled to the second load terminal 170. The control metal layer 152, the first metal layer 162, and the second metal layer 172 form a control electrode, a first load electrode, and a second load electrode, respectively, of the MottFET device 100. The control electrode need not be in the form of a layer but can contain a control metal element with other shapes, e.g., in the form of a rod or beam (see figure). Fig. 11A, Fig. 11B, Fig. 14).

[0016] For example, the MottFET device 100 can be a five-layer stacking device consisting of the control metal layer (or element) 152, the PE material body (or layer) 120, the first metal layer 162, the PR material body (or layer) 140 and the second metal layer 172.

[0017] The MottFET device 100 can include a housing structure 180 that forms a cavity 182 for receiving the transistor cell. The housing structure 180 can be made of a robust material, e.g., a high-strength material (HSM). The surrounding HSM can provide strong support against which the PE material body 120 can exert pressure on the PR material body 140. In other words, the PE material body 120 and the PR material body 140 are clamped together by a mechanical cage formed by the housing structure 180.

[0018] The cavity 182 can contain a void (e.g. after the removal of a sacrificial material by etching) in the HSM to allow free lateral displacement of the PE material body 120 and the PR material body 140.

[0019] During operation, an input voltage applied between the control terminal 150 (G) and the first load terminal 160 (C), e.g., via the PE material body 120, causes the PE material body 120 to expand against the PR material body 140. This converts the input voltage into an internal mechanical pressure signal (internal transduction). The PE material body 120, acting as a capacitor dielectric, prevents any significant leakage current. The PR material body 140, on the other hand, undergoes a pressure-induced continuous Mott junction, which changes the resistance by several orders of magnitude, thus creating a low-resistance path between the second load terminal 170 (S) and the first load terminal 160 (C) and converting the pressure signal back into an electrical voltage.

[0020] A large area ratio between the PE material body 120 and the PR material body 140 serves to convert a low voltage in the PE material body 120 into a high voltage in the PR material body 140, so that only a small input voltage (or drive voltage) is required to switch the S-to-C impedance (the impedance of the PR material body 140) from high to low (internal potential step). Adequate strain and electric fields in the PE material body 120 are achieved by maintaining a high area ratio of PE material body 120 to PR material body 140.

[0021] In other words, the input voltage V triggers GC the piezoelectric effect. The piezoelectric effect is transmitted via the body made of piezoelectric material 140. The piezoresistive effect causes the Mott junction, on which the electrical switching of the MottFET device 100 is based.

[0022] In other words, the piezoelectric reaction of the actuator, which includes the PE material body 120, sets the input voltage V GC converts into a mechanical pressure that modulates the electrical resistance of the PR material body 140, e.g., the output piezoresistivity. In the OFF state of the MottFET device 100, the PR material body 140 is in a high-resistance state, thus blocking the output current, while in the ON state of the MottFET device 100, the voltage V GC This causes the PE material body 120 to expand in a direction perpendicular to the layer plane, thereby exerting pressure on the PR material body 140. This reduces the electrical resistance of the PR material body 140, allowing the output current to flow between the first metal layer 162 and the second metal layer 172, and thus between the first load terminal 160 (C) and the second load terminal 170 (S).

[0023] The device's design takes advantage of the Mott junction of the PR material. In its insulating state, the electrons are bound to their transition metal atoms, their electron-electron Coulomb repulsion is large, and their interatomic jump energy is low. Even when a voltage V is applied, GC When pressure is applied to such a material, the Coulomb barrier is insurmountable due to the kinetic jump energy. When pressure is applied, the crystal structure of such a material deforms, leading to a multitude of vacancies on which the electrons can move, thus eliminating the energy gap.

[0024] In a model for MottFET operation, the resistivity of PR materials is typically approximately exponential with pressure over a wide range, so the pressure dependence can be modeled as follows. ρ=ρ0exp[−Qρ] Q=−d ln ρ / dp.

[0025] Q denotes the material constant, which is defined as a function of pressure (p), and ρ0 is the PR material resistance at zero pressure (p = 0). The dependence of pressure on stress V GC It is based on the assumptions of a linear response of the PE to the applied field and the applicability of the theory of linear elasticity to the transistor cell. A relatively simple approximation, which only considers the d 33 Taking into account the components of the stress (outside the plane), the strain and the piezoelectric response, the following results: p≅d33VGClYPR+dYPEwith d=La / A.

[0026] This involves d 33 the piezoelectric coefficient, Y PR and Y PE are the elastic moduli of the PR and PE materials, respectively, 1 is the thickness of the PR material, d is the thickness L of the PE material scaled by the reciprocal of the reinforcement factor A / a (see Fig. 1A). Using the two relationships above, the linear electrical resistance R can be determined. SC of the PR material body 140 in the form of a V GC as follows RSC=R0exp(−VGCVθ) with Vθ=(lYPR+dYPE) / (Qd33) R0=ρ0l / a.

[0027] In this equation, the threshold voltage is V. θ and the resistance in the off state R0. Consequently, the current flowing through the PR material body 140 (i.e., the common source current) I SC given by: ISC=VSC / RSC=VSCR0−1exp(VGCVθ).

[0028] It is desirable to provide a MottFET device 100 that is capable of power switching, i.e., that is suitable for switching higher voltages and / or higher currents than conventional Mott transistors. This power switching capability can be achieved by appropriately adapting the dimensions of the device and / or by selecting a suitable material for the PE and, in particular, the PR material(s), and / or by appropriately implementing an internal interconnect in the MottFET device 100.

[0029] Using the given values ​​of the PE and PR materials, the dimensions of the device were adjusted to achieve a threshold voltage of approximately 1.2 V. High values ​​for R were used. OFF / R ON observed. In particular, the maximization of the ratio R OFF / R ONThis is an important criterion for power components, e.g., for high-power devices with a high vertical current flow and a thick PR material body that ensures blocking capability. Unlike low-voltage devices, the PR material body 140 can have a voltage blocking capability between 25 V and 7 kV and carry currents between a few A and more than 50 A (locally with much higher current densities under surge current conditions, short-circuit events, and overcurrent shutdown).

[0030] Another criterion for high-power devices is the required robustness against cosmic radiation events. The desired material selection and dimensions (layer thickness, area, etc.) can be optimized with regard to these specific high-power applications. Typically, the thickness of the PR 140 material body is more than five times greater than that of conventional low-voltage switching Mott transistors. The lateral dimensions of the PR 140 material body can even be more than an order of magnitude greater than those of conventional low-voltage switching Mott transistors.

[0031] The following example values ​​for sizes can be chosen, for example: Thickness of the PR material body 140: 1 = 40 nm Surface area of ​​the PR material body 140: a = 10,000 nm 2 PE material body thickness 120: L = 500 nm Surface area of ​​the PE material body 120: A = 50,000 nm 2 D = L*a / A = 500

[0032] Typical values ​​include, for example: d 33 = 1.4 nm / V B = 5.4 GPa -1 Y PE = 60 GPa Y PR = 40 GPa ρ0 = 0.2 S2m Threshold voltage = 1.2 to 30 V for power applications.

[0033] Therefore, for example, V GG = 25 V, R SC = 1.79 10 -10 Q, see equation (3).

[0034] All dimensions of the components of the device can be selected, for example, within a range of ±50%, in particular ±30% or in particular ±15% of the above-mentioned example values.

[0035] With typical values ​​of such a PE and PR material combination and the choice of device dimensions, the threshold stress and the ratio R can be determined. ON / R OFF will be calculated.

[0036] PE materials can include or be, for example, AlN, BaTiO3, LiNbO3, PMN-PT, PZT, AlScN, PVDF and / or AlScN.

[0037] PR materials can include, for example, SMS, SMS, V x O y (e.g. VO2, V2O3, V2O5) , TmTe, (Sm 1-x EU x ) S, (V 1-x Cr x ) 2O3, and / or SiC nanowires. These materials may, for example, be appropriately doped with foreign atoms.

[0038] In at least some of these PR materials, the Mott transition is based on the pressure sensitivity of the energy gap between the 4f and 5d bands. Under stress, the energy gap narrows continuously, allowing the thermal promotion of localized 4f states into the conduction band. The increase in 5d band population leads to an exponential increase in the conductivity (i.e., a decrease in electrical resistivity) of the PR material body 140.

[0039] An input voltage pulse VGC activates the PE material body 120, which supplies the input voltage V GC converts into a pressure pulse. The pressure pulse, in turn, controls the Mott junction in the PR material body 140. Using the known properties of bulk materials, it can be shown that the MottFET device 100, according to the disclosure, achieves clock speeds in the multi-GHz range and a large ON / OFF switching ratio (e.g., ~10). 6 - 10 7 ) for circuit breakers.

[0040] Fig. Figure 2 shows a layer stack of a MottFET device 200, which contains at least two transistor cells 210, 220. A first transistor cell 210 comprises a first PE material body 120_1 and a first PR material body 140_1. The first PE material body 120_1 and the first PR material body 140_1 are arranged in a stacked configuration.

[0041] Furthermore, the MottFET device 200 contains a second transistor cell 220. The second transistor cell 220 comprises a second PE material body 120_2 and a second PR material body 140_2. The second PE material body 120_2 and the second PR material body 140_2 are arranged in a stacked configuration.

[0042] In the example of the Fig. In section 2, the first PE material body 120_1 and the second PE material body 120_2 are formed by a common, continuous PE material body 120. In other words, the PE material body 120 is only conceptually divided into a first and a second PE material body 120_1, 120_2. That is, the two transistor cells 210, 220 share a common PE material body 120, which is also referred to as the "PE busbar".

[0043] The first and second PE material bodies 120_1, 120_2, and the PE material body 120 can, for example, have the form of a structured layer. However, it is also possible that the first and second PE material bodies 120_1, 120_2, and the PE material body 120 have the form of a rod, a block, a cube, or a cylinder (see, for example, [reference]). Fig. 11A, Fig. 11B, Fig. 14) .

[0044] The electrical resistance of the first PR material body 140_1 is determined by a pressure exerted on the first PR material body 140_1 by the voltage V by the first PE material body 120_1. GC dependent on the voltage applied across the first PE material body 120_1. Similarly, the electrical resistance of the second PR material body 140_2 is determined by a pressure exerted by the second PE material body 120_2 on the second PR material body 140_2 by the voltage V. GCdependent, which is applied via the second PE material body 120_2. For this purpose, the first and second transistor cells 210, 220 can each be connected by means of a housing structure 180 (in, as described above). Fig. (2 not shown) are clamped. The housing structure 180 can, for example, have a common cavity that accommodates the first transistor cell 210 and the second transistor cell 220, or it can alternatively be provided with separate cavities, each of which accommodates only one (or more generally, if more than two transistor cells are provided, a subset) of the transistor cells 210, 220.

[0045] The MottFET device 200 further comprises an internal electrical connection configured to electrically connect the electrical resistance of the first PR material body 140_1 and the electrical resistance of the second PR material body 140_2 in parallel. For this purpose, the electrical connection can connect the common control metal layer 152 to the control terminal (G) 150, the (e.g., common) first metal layer 162 to the first load terminal (C) 160, and the second metal layers 172_1, 172_2 of the first and second transistor cells 210, 220 to the second load terminal (S) 170.

[0046] As further below (e.g. in the Fig. 4 and Fig. 5) as described in more detail, more than two transistor cells 210, 220 can be used.

[0047] The Fig. 3A and Fig. Figure 3B shows an exemplary layer stack of a MottFET device 300 with a first transistor cell 310 and a second transistor cell 320A. Similar to what has already been described in connection with the MottFET device 200, the MottFET device 300 optionally uses a common PE material body 120, which is, for example, conceptually divided into the first PE material body 120_1 and the second PE material body 120_2.

[0048] The first transistor cell 310 may be identical to the first transistor cell 210 of the MottFET device 200, and reference is made to the above description to avoid repetition.

[0049] The second transistor cell 320A can contain an insulating layer 322. The insulating layer 322 electrically isolates the base of the second PR material body 140_2 from the (optionally common) first metal layer 162.

[0050] A first load electrode 362_2 of the second transistor cell 320A can be realized by a metal layer that, for example, covers part of the upper surface of the second PR material body 140_2. The first load electrode 362_2 of the second transistor cell 320A can be electrically connected to the second metal layer 172_1 (i.e., the second load electrode) of the first transistor cell 310.

[0051] Furthermore, the second transistor cell 320A can be equipped with a second load electrode 372 2. In the example of the Fig. In 3A, the second load electrode 372_2 of the second transistor cell 320A can be realized by a metal layer that covers a different, separate part of the upper surface of the second PR material body 140_2. That is, the first load electrode 362_2 and the second load electrode 372_2 of the second transistor cell 320A are separated from each other, for example, by a gap. They are electrically coupled to each other by the second PR material body 140_2 of the second transistor cell 320A.

[0052] The second load electrode 372_2 of the second transistor cell 320A can be electrically connected to the second load terminal (S) 170 of the MottFET device 300.

[0053] In MottFET device 300, the electrical resistance of the first PR material body 140_1 and the electrical resistance of the second PR material body 140_2 are connected in series. In both MottFET devices 200 and 300, the electrical resistance of the first PR material body 140_1 is a resistance to a load current flowing in a direction normal to the first PR material body 140_1. However, while in MottFET device 200 the electrical resistance of the second PR material body 140_2 is also a resistance to a load current flowing in a direction perpendicular to the second PR material body 140_2, in MottFET device 300 the electrical resistance of the second PR material body 140_2 is a resistance to a load current flowing at least partially in a direction parallel to the second PR material body 140_2.

[0054] Fig. Figure 3B shows a MottFET device 300', which is similar to the MottFET device 300 in that the first transistor cell 310 and a second transistor cell 320B are connected in series. However, the second transistor cell 320B differs from the second transistor cell 320A of the MottFET device 300 in that the electrical resistance of the second PR material body 140_2 is a resistance to a load current flowing in a direction perpendicular to the second PR material body 140_2.

[0055] For this purpose, the second transistor cell 320B can be provided with a first load electrode 362_2, which can be arranged between the insulating layer 322 and the base of the second PR material body 140_2. The second metal layer (second electrode) 172_1 of the first transistor cell 310 can be electrically connected to the first load electrode 362_2 of the second transistor cell 320B. The second load electrode 372_2 of the second transistor cell 320B can, in turn, be connected to the second load terminal (S) 170 of the MottFET device 300'.

[0056] The MottFET devices 200, 300, and 300' can be used as stacked modules that can be combined or extended to form MottFET devices containing more than two transistor cells. Any combination of these modules is possible, in particular combinations of parallel ( Fig. 2) and series circuits ( Fig. 3A, Fig. 3B). Some examples of such power MottFET devices are described below.

[0057] In general, the above disclosure regarding dimensions, materials, constructions, in particular the design of the housing and / or the internal connection, can be applied to all the examples described below.

[0058] The concept of connecting at least two transistor cells in parallel or in series makes it possible to obtain MottFET devices that can be tailored to specific power applications, such as high-voltage and / or high-current circuits. Connecting the transistor cells in series improves the blocking capability of the MottFET device. Connecting transistor cells in parallel improves the ability to switch high currents. Since both approaches (series and parallel) can be combined in a single MottFET device, it is possible to achieve the desired characteristics of the power device through appropriate design.

[0059] Fig. Figure 4 illustrates a MottFET device 400 in which several transistor cells 410, 420, 430, 440 are connected in parallel by an internal interconnection that uses, for example, a common first metal layer 162 as the first electrodes of the respective PR material bodies 140_1, 140_2, 140_3, 140_4. The common first metal layer 162 improves the load current distribution across the transistor cells 410, 420, 430, 440. This design is particularly suitable for the fabrication of power MottFET devices with tight tolerances in electrical specifications.

[0060] Fig. Figure 5 shows a MottFET device 500, which differs from the MottFET device 400 in that the first metal layers (first electrodes) 162 of the transistor cells are structurally separated from each other. Furthermore, the PE material body 120 can (optionally) also be structurally separated into discrete PE material bodies 120_1, 120_2, 120_3, 120_4 or as a common PE material body 120, as in Fig. As shown in Figure 4, the internal electrical connection can be designed such that the first load terminal (C) 160 is electrically connected to all first metal layers (first electrodes) 162. With respect to the second load terminal (S) 170, the electrical connection can be identical to the electrical connection of the MottFET device 400.

[0061] The MottFET device 500 provides for a parallelization of the transistor cells 520, 520, 530, 540, which enables an improved current carrying capacity.

[0062] The Fig. 6 and Fig. Figure 7 shows further examples of MottFET devices with multiple transistor cells 600, 700. In the MottFET device 600, several transistor cells 310, 320A_1, 320A_2, 320A_3 are connected in series. The series connection of the Fig. 3A is used, but in other examples the series connection of the Fig. 3B can be used.

[0063] Due to the insulating layer(s) 322 provided beneath the PR material bodies 140_2, 140_3, 140_4, the transistor cells 310, 320A_1, 320A_2, 320A_3 are held in series during the off-state, thus achieving a high blocking capability of the MottFET device 600. The number of series-connected transistor cells can be varied depending on the desired voltage class.

[0064] The MottFET device 700 relies on an internal electrical connection that allows a mixed series and parallel connection of several transistor cells. Specifically, the MottFET device 700 comprises a control terminal (G) 150, a first load terminal (C) 160, and a second load terminal (S) 170. The MottFET device 700 comprises at least a first plurality of transistor cells 710 and a second plurality of transistor cells 720. The MottFET device 700 further comprises an internal electrical connection configured to connect the electrical resistances of the first plurality of transistor cells 710 in series, the electrical resistance of the second plurality of transistor cells 720 in series, and these two series connections in parallel.

[0065] As in Fig. As shown in Figure 7, a further large number of transistor cells (here: e.g. four) can be connected internally in series and then, for example, in parallel.

[0066] In the MottFET device 700, the PE material bodies of the first plurality of transistor cells 710 are configured as a first common PE material body 120_1, and the PE material bodies of the second plurality of transistor cells 720 are similarly configured as a second common PE material body 120_2. The first and second common PE material bodies 120_1, 120_2 are, for example, separated from each other. The control terminal (G) 150 is connected to a control electrode of the first common PE material body 120_1 and to a control electrode of the second common PE material body 120_2, respectively. The control electrodes can, for example, be provided by a continuous, common control metal layer 152.

[0067] In the MottFET device 700, the first load terminal (C) 160 can be connected to one or more first load electrodes 162 of a subset of transistor cells of any plurality of transistor cells 710, 720. Fig. 7 is, for example, only one transistor cell of each multitude of transistor cells 710, 720 connected to each first load electrode 162.

[0068] In the MottFET device 700, the second load terminal (S) 170 can be connected to one or more second load electrodes of a subset of transistor cells of the first plurality of transistor cells 710 and to one or more second load electrodes of a subset of transistor cells of the second plurality of transistor cells 720. In the example shown, the second load terminal 170 is connected to (only) one second load electrode of the respective subsets of transistor cells.

[0069] All the examples described above can be applied to the MottFET device 700. For example, the internal series connection of the multiple transistor cells 710, 720, 730, 740 can be carried out according to... Fig. 3B instead of according to Fig. 3A may be executed and / or the first metal layer(s) 162 may be a continuous metal layer and / or the PE material bodies 120_1, 120_2, 120_3, 120_4 may be formed by a common, continuous PE material body (e.g. layer) 120, etc.

[0070] As previously mentioned, all MottFET devices 200, 300, 300', 400, 500, 600, 700 can have a housing structure with one or more cavities for accommodating the first and second transistor cells 210, 220, 310, 320A, 320A_1-3, 320B, 410-440, 510-540 and / or the first and second plurality of transistor cells 710, 720. The cavities can be arranged adjacent to each other with respect to a lateral dimension of the housing structure.

[0071] Fig. Figure 8 shows a MottFET device 800 with a housing structure comprising an upper metal plate 810 and a lower metal plate 820. The lower metal plate 820 can form the control terminal (G) 150 of the MottFET device 800 and / or the upper metal plate 810 can form the second load terminal (S) 170 of the MottFET device 800.

[0072] In Fig. The 8 transistor cells are 510, 520, 530, 540 (see also Fig. 5) e.g. arranged between the upper metal plate 810 and the lower metal plate 820. Each of the above described stacks of MottFET devices 100, 200, 300, 300', 400, 500, 600, 700 can be inserted between such metal plates 810, 820.

[0073] The metal plates 810, 820 can have the function of providing the control connection 150 and the second load connection 170, and / or can (additionally) have the function of forming clamping elements that cause the pressure pulse from the PE material bodies 120_1, 120_2, 120_3, 120_4 to cause the Mott transition in the PR material bodies 140_1, 140_2, 140_3, 140_4.

[0074] In Fig. 8 is the housing structure (see, for example, the housing structure 180 from Fig. 1B) not shown, with the exception of the lower and upper metal plates 820, 810, which form part of the housing structure. In all MottFET devices 100, 200, 300, 300', 400, 500, 600, 700, 800 described here, the housing structure 180 can form a closed cavity 182, which can be, for example, hermetically sealed.

[0075] In all MottFET devices described here, the control metal layer 152 and / or the PE material body 120 and / or the first metal layer 162 and / or the PR material body 140 can have a circumferentially rounded or cylindrical shape (instead of a circumferentially rectangular shape, as shown in the example figures) to avoid the occurrence of electrical potential spikes at corners. Furthermore, the metal plates 810, 820 can have a circumferentially rounded (e.g., cylindrical) shape or a substantially rectangular shape.

[0076] Fig. Figure 9 shows a Package 900 containing a variety of package structures or MottFET devices, e.g., MottFET devices 800, as in Fig. Figure 8 shows that Package 900 can be a so-called press-pack enclosure. Package 900 comprises a base 910 and a lid 920. The lid 920 can be screwed to the base 910 or otherwise rigidly attached to it. When the lid 920 is attached to the base 910, the interior of Package 900 can be hermetically sealed.

[0077] The MottFET device 800 (or other MottFET devices 100 to 700) is housed inside the lower part 910. Fig. 9 An array of such MottFET devices 800 can be housed in the package 900. The upper metal plates 810 of the MottFET devices 800 can be exposed when the package 900 is not closed. When the package 900 is closed by attaching the top part 920 to the bottom part 910, the upper metal plates 810 can be pressed down and electrically connected to the top part 920. Therefore, the top part 920 (which may be electrically insulated from the bottom part 910) can serve as the common load terminal of the package, which is connected to the second load terminals (S) 170 of the MottFET devices 800. In this way, the package 900 itself constitutes a MottFET device containing a plurality of internally connected MottFET devices in parallel.

[0078] Fig. Figure 10A shows a MottFET device 1000 with a housing structure 1080, which is provided with a plurality of cavities 182 for receiving transistor cells, as described above. The cavities 182 are arranged adjacent to each other with respect to a lateral dimension of the housing structure 1080.

[0079] In the MottFET device 1000, the PE material bodies 120 and the PR material bodies 140 of the transistor cells are oriented perpendicularly (or, more generally, obliquely) to the lateral dimension of the housing structure 1080. It is also possible that these PE material bodies 120 at least partially enclose the PR material body 140.

[0080] The 1080 package structure can, for example, comprise a first substrate 1080_1 and a second substrate 1080_2. The first substrate 1080_1 can, for example, be a wafer or part of a wafer (e.g., a chip), and / or the second substrate 1080_2 can also be a wafer or part of a wafer (e.g., a chip). The material of the first substrate 1080_1 can, for example, be an HSM, and / or the material of the second substrate 1080_2 can also be an HSM. The material of the first substrate 1080_1 and / or the second substrate 1080_2 can, for example, be silicon, silicon carbide, or silicon nitride. Other materials that can be used for the first and / or second substrates 1080_1 and 1080_2 are glass, sapphire, or quartz glass. For example, the first substrate 1080_1 can be made from silicon and the second substrate 1080_2 from silicon nitride.

[0081] The cavities 182 can be produced by isotropic etching of the first substrate 1080_1. Known MEMS (microelectromechanical systems) techniques can be used.

[0082] The first substrate 1080_1 and the second substrate 1080_2 can be joined together, for example, by wafer bonding or other techniques known in engineering.

[0083] In the example shown, the MottFET device 1000 contains, for example, a single transistor cell per cavity. However, it is also possible that some or all of the cavities 182 are configured to accommodate a plurality of transistor cells. For example, a first cavity 182 can accommodate a first plurality of transistor cells 710 (see Fig. 7), a second cavity 182 can accommodate a second plurality of transistor cells 720, etc. In this case, the MottFET device 1000 can be used to connect the MottFET device 700 according to Fig. 7 to realize.

[0084] In general, each cavity 182 can accommodate any of the MottFET devices 100 to 800 described above. The MottFET device 1000 then includes another internal connection (not shown) configured to connect these MottFET devices 100 to 800 in series or parallel.

[0085] In other words, starting from the "building blocks" of Fig. 2, Fig. 3A and Fig. 3B and the examples of MottFET devices shown demonstrate how a variety of different modules can be created.

[0086] Fig. Figure 10B shows a MottFET device 1000' with a package structure 1080, which is the package structure 1080 of Fig. 10A is similar or identical, and reference is made to the description above. The MottFET device 1000' uses a layer stack in which PR material bodies 140 are arranged on opposite sides of the PE material body 120 per cavity 182. This can be achieved by a two-dimensional layer stack in which all layers 120, 140, 162, 172 are perpendicular to the plane of the paper, or by a radially symmetric layer stack in which the PE material body 120 is central (and e.g. designed as a cylinder) and is surrounded radially by the first metal layer 162, the PR material body 140, and the second metal layer 172. Here, the expansion of the PE material in at least two opposite directions (or e.g. in all radial directions) is used to actuate the PR material bodies 140, which increases the amount of PR material and thus the power density of the MottFET device 1000'.

[0087] The Fig. 11A and Fig. Figure 11B shows examples of MottFET devices 1100 and 1100' in which at least two transistor cells are oriented in different spatial directions. For example, a first transistor cell 210 comprises a first PE material body 120_1 and a first PR material body 140_1. The first PE material body 120_1 and the first PR material body 140_1 are arranged in a stacked configuration.

[0088] Furthermore, the MottFET device 1100 contains a second transistor cell 220. The second transistor cell 220 comprises a second PE material body 120_2 (which in the example shown is made of the same PE material as the first PE material body 120_1) and a second PR material body 140_2. The second PE material body 120_2 and the second PR material body 140_2 are arranged in a stacked configuration.

[0089] The first PR material body 140_1 and the second PR material body 140_2 are aligned in different spatial planes that are not parallel to each other. For example, while the first PR material body 140_1 may be aligned in the XZ plane, the second PR material body 140_2 may be aligned in the XY plane.

[0090] The first PE material body 120_1 and the second PE material body 120_2 can be configured as a single, structured PE material body 120, as shown. The structured PE material body 120 has side faces. The first PR material body 140_1 (of the first transistor cell 210) can extend over the top surface of the single, structured PE material body 120, while the second PR material body 140_2 (of the second transistor cell 220) can extend over a side face of the structured PE material body 120.

[0091] The common, structured PE material body 120 can be deformed in all directions X, Y, Z and -X, -Y, -Z when activated.

[0092] For example, the MottFET device 1100 can include a common control metal layer 152, which may be shaped, for example, as a rib or a rod. The structured PE material body can encapsulate the common control metal layer 152 on at least two sides, for example, on the top and on one or both side faces. Furthermore, the first metal layer 162 can cover the structured PE material body on at least two sides. In other words, the structured PE material body can be encapsulated by the first metal layer 162 on, for example, two, three, or four sides.

[0093] Regarding the internal electrical connection, it shows Fig. Figure 11A shows an exemplary implementation in which the first and second transistor cells 210, 220 are connected in parallel. This is comparable to the exemplary implementation of the MottFET device 200 from Fig. 2. However, it is also possible that the first and second transistor cells 210, 220 are connected in series. In this respect, the values ​​in the Fig. 3A and Fig. The special implementations shown in 3B can, for example, be applied directly to the “three-dimensional” MottFET device 1100’.

[0094] While the first and second transistor cells 210, 220 are oriented in different spatial directions (in this example in the Y-direction and the -Z-direction), another transistor cell 1230 can, for example, be oriented in the third dimension (in this example in the -X-direction). In general, the at least two transistor cells 210, 220, 1230 described here should be oriented in at least two different spatial directions.

[0095] Fig. Figure 11A shows the internal electrical circuitry for only two transistor cells, 210 and 220. All in Fig. The transistor cells shown in 11A can be connected either in series or in parallel, or partly in parallel and partly in series, see e.g. Fig. 7.

[0096] Fig. Figure 11B illustrates another implementation of a “three-dimensional” MottFET device 1100’. The MottFET device 1100’ uses a multitude of MottFET devices 1100 as building blocks, connected in parallel or in series or by a mixed series and parallel electrical connection (not shown).

[0097] To better illustrate, the Fig. 11A and Fig. 11B does not refer to the housing structure that allows the stress exerted by the structured PE material body 120 to be transferred as a compressive force to the various PR material bodies 140_1, 140_2 of the transistor cells 210, 220, 1230. Housing structures as described above could be used.

[0098] Due to the specific application requirements in power electronics, a variety of such Mott transistor cells 210, 220, 1230 (“Mott switches”) could use the same bus (i.e. the same PE material body 120) that initiates the transition from insulator to metal in the various Mott switches.

[0099] The encapsulation scheme described above makes it possible to utilize the various surfaces of the structured PE material body 120 (which could also be referred to as a “PE rod”), thereby enabling a higher power density for such an exemplary Mott transistor-based power switch, as is the case, for example, with MottFET devices 1100 or 1100’.

[0100] Fig. Figure 12 shows an electronic power module 1200 containing a MottFET device MD. The MottFET device MD can be, for example, one of the MottFET devices 100 to 800 or 1000, 1000', 1100, 1100' described above, or any variants or combinations thereof.

[0101] The electronic power module 1200 also includes a carrier 1220. The carrier 1220 can be, for example, a frame, a printed circuit board, or another known carrier, such as a ceramic-based carrier. The MottFET device MD is mounted on the carrier 1220.

[0102] The electronic power module 1200 can also include a heat sink 1240. The heat sink 1240 is attached to the support 1220. A base plate 1260, for example, can be arranged between the heat sink 1240 and the support 1220. Both the base plate 1260 and the heat sink 1240 can be made of a metal (e.g., at least one of copper, titanium, titanium nitride, aluminum, tungsten, tantalum, tantalum nitride) or of a ceramic (e.g., AlN, Al₂O₃, ...).

[0103] The electronic power module 1200 can also include a temperature sensor 1280. The temperature sensor can be, for example, a thermistor, also known as an NTC thermistor (negative temperature coefficient). The temperature sensor 1280 can be configured to monitor the temperature within the electronic power module 1200. The electronic power module 1200 can have a threshold voltage in a range between 1.2 and 30 V.

[0104] Fig. Figure 13 shows an exemplary arrangement 1300 of electronic power modules 1200 arranged in a series. The electronic power modules 1200 can be, for example, arranged according to Fig. The electronic power modules 1200 are assembled in series (i.e., laterally) connection to connection and vertically connection to heat sink.

[0105] Fig. Figure 14 is a perspective view of an exemplary MottFET device 1400. The MottFET device 1400 differs from all the MottFET devices described above in that there is no requirement for an internal connection through which the transistor cells 210, 220 are connected either in series or in parallel. In particular, the MottFET device 1400 can, for example, be a non-power or logic transistor device.

[0106] As in the Fig. 11A and Fig. Reference 11B, which is made to avoid repetition, states that at least two transistor cells are oriented in different spatial directions. In other words, the first PR material body 140_1 (of the first transistor cell 210) and the second PR material body 140_2 (of the second transistor cell 220) are oriented in different spatial planes that are not parallel to each other. For example, while the first PR material body 140_1 may be oriented in the XZ plane, the second PR material body 140_2 may be oriented in the XY plane.

[0107] As described above, the first PE material body 120_1 and the second PE material body 120_2 are formed as a common, structured PE material body 120, as shown. The structured PE material body 120 has side surfaces. The first PR material body 140_1 (of the first transistor cell 210) can extend over the top surface of the common, structured PE material body 120, while the second PR material body 140_2 (of the second transistor cell 220) can extend over a side surface of the structured PE material body 120.

[0108] The structured PE material body 120 can encapsulate the common control metal layer 152 on at least two sides, e.g., on the top and on one or both side surfaces. Furthermore, the first metal layer 162 can cover the structured PE material body on at least two sides. In other words, the structured PE material body 120 can be encapsulated by the first metal layer 162 on, for example, two, three, or four sides.

[0109] The MottFET device 1400 can be equipped with the following external connections:

[0110] A control terminal 150 (G) of the MottFET device 1400 is connected to a control electrode 152, wherein the control electrode 152 is connected to the first PE material body 120_1 and the second PE material body 120_2, which are here designed as a common PE material body 120.

[0111] A first terminal 160_1 (C) of the MottFET device 1400 can be connected to a first electrode 162 of the first transistor cell 210, which is arranged between the PE material body 120 and the first PR material body 140_1, and to a second electrode 162 of the second transistor cell 220, which is arranged between the PE material body 120 and the second PR material body 140_2.

[0112] A second terminal 170_1 (S1) of the MottFET device 1400 can be connected to a second electrode 172_1 of the first transistor cell 210, wherein the second electrode 172_1 is arranged on the first PR material body 140_1.

[0113] A third terminal 170_2 (S2) of the MottFET device 1400 can be connected to a second electrode 172_2 of the second transistor cell 220, wherein the second electrode 172_2 is arranged on the second PR material body 140_2.

[0114] This means that the “three-dimensional” MottFET device 1400 can have a number of external connections equal to or greater than 4.

[0115] Similar to what was already mentioned in connection with the Fig. 11A, Fig. As described in Figure 11B, another transistor cell 1230 can be oriented, for example, in the third dimension (in this example in the -X direction). A fourth terminal 170_3 (S3) of the MottFET device 1400 can be connected to a second electrode of the transistor cell 1230, with the second electrode being located on the third PR material body 140_3.

[0116] In general, the at least two transistor cells 210, 220, 1230 described here should be oriented in at least two different spatial directions. For example, the third PR material body 140_3 is oriented in a spatial plane that is not parallel to any of the spatial planes in which the first PR material body 140_1 and the second PR material body 140_2 are oriented.

[0117] Fig. Figure 14 shows the connections of a MottFET device 1400 with two or three transistor cells 210, 220, 1230. All in Fig. However, the 14 transistor cells shown can be connected to separate terminals of the device in the same way as transistor cells 210, 220, and 1230. Furthermore, the MottFET device 1400 can be extended in the same way as described in Fig. 11B shown.

[0118] For better illustration, in Fig. Figure 14 shows the housing structure, which allows the strain exerted by the structured PE material body 120 (120_1, 120_2) to be exerted as a compressive force on the various PR material bodies 140_1, 140_2, 140_3, 140 of the transistor cells 210, 220, 1230. Housing structures as described above could be used.

[0119] In logic devices, for example, a large number of such Mott transistor cells 210, 220, 1230 (“Mott switches”) could use the same “bus” (i.e., the same PE material body 120, also called the “PE busbar”) that initiates the transition from insulator to metal in the various Mott switches. The use of a common PE busbar for a large number of transistor cells 210, 220,... as in the Fig. 2, Fig. 3A, Fig. 3B, Fig. 4, Fig. 6, Fig.7 (partially), 11A, 11B, 14 shown, is an (optional) feature that applies to all examples of this revelation.

[0120] The encapsulation scheme described above makes it possible to utilize the different surfaces of the structured PE material body 120, which allows more transistor cells to be packed into a single MottFET device 1400 (with at least two transistor cells 210, 220). EXAMPLES

[0121] The following examples relate to other aspects of the revelation: Example 1 is a piezoresistive transistor device with a first transistor cell. The first transistor cell comprises a first body made of piezoelectric material and a first body made of piezoresistive material. The first body made of piezoelectric material and the first body made of piezoresistive material are arranged in a stacked configuration, and the first electrical resistance of the first body made of piezoresistive material depends on a voltage applied across the first body made of piezoelectric material by means of a pressure exerted on the first body made of piezoresistive material. The piezoresistive transistor device comprises a second transistor cell. The second transistor cell comprises a second body made of piezoelectric material and a second body made of piezoresistive material.The second body made of piezoelectric material and the second body made of piezoresistive material are arranged in a stacked configuration. The resistance of the second body made of piezoresistive material is controlled by a pressure exerted on it by the second body made of piezoelectric material, which in turn depends on a voltage applied across the second body made of piezoelectric material. The piezoresistive transistor device includes a control terminal, a first load terminal, a second load terminal, and an internal electrical connection configured to connect the first and second resistances electrically in series or parallel. In Example 2, the object of Example 1 can optionally include the first body made of piezoelectric material and the second body made of piezoelectric material being designed as a common body made of piezoelectric material. In Example 3, the object from Example 1 can optionally include the first body made of piezoelectric material and the second body made of piezoelectric material being separated from each other. In Example 4, the subject of any preceding example may optionally include the connection being linked to a control electrode, the control electrode being linked to the first body made of piezoelectric material and the second body made of piezoelectric material. In Example 5, the subject of each preceding example may optionally include that, in the case where the internal electrical connection is configured to connect the first electrical resistance and the second electrical resistance in parallel, the first load terminal is connected to a first load electrode of the first transistor cell and a first load electrode of the second transistor cell, the first load electrode of the first transistor cell is positioned between the first body of piezoelectric material and the first body of piezoresistive material, and the first load electrode of the second transistor cell is positioned between the second body of piezoelectric material and the second body of piezoresistive material. In Example 6, the subject of Example 5 may optionally include that, in the case where the internal electrical connection is configured to connect the first electrical resistance and the second electrical resistance in parallel, the second load terminal is connected to a second load electrode of the first transistor cell and a second load electrode of the second transistor cell, the second load electrode of the first transistor cell is located on a side of the first body of piezoresistive material facing away from the first body of piezoelectric material, and the second load electrode of the second transistor cell is located on a side of the second body of piezoresistive material facing away from the second body of piezoelectric material. In Example 7, the subject of Example 5 or 6 may optionally include the first electrical resistance being a resistance to a load current flowing in a direction perpendicular to the first body of piezoresistive material, and the second electrical resistance being a resistance to a load current flowing in a direction perpendicular to the second body of piezoresistive material. In Example 8, the subject of any of Examples 1 to 4 may optionally include that, in the case that the internal electrical connection is configured to connect the first electrical resistor and the second electrical resistor in series, the first load terminal is connected to a first load electrode of the first transistor cell, which is positioned between the first body of piezoelectric material and the first body of piezoresistive material, and a second load electrode of the first transistor cell is connected to a first load electrode of the second transistor cell, wherein the first load electrode of the second transistor cell is not connected to the first load terminal. In Example 9, the subject of Example 8 can optionally include the second load terminal being connected to the second load electrode of the second transistor cell. In Example 10, the subject of Example 8 or 9 may optionally include the first and second load electrodes of the second transistor cell being arranged on a side of the second body made of piezoresistive material that faces away from the second body made of piezoelectric material. In Example 11, the subject of one of Examples 8 to 10 may optionally include the first electrical resistance being a resistance to a load current flowing in a direction perpendicular to the first body of piezoresistive material, and the second electrical resistance being a resistance to a load current flowing at least partially in a direction parallel to the second body of piezoresistive material. In Example 12, the subject of Example 8 or 9 may optionally include the first electrical resistance being a resistance to a load current flowing in a direction perpendicular to the first body of piezoresistive material, and the second electrical resistance being a resistance to a load current flowing in a direction perpendicular to the second body of piezoresistive material. In Example 13, the subject of any preceding example may optionally further comprise a housing structure with at least one cavity for receiving the first transistor cell and the second transistor cell, wherein the housing structure comprises an upper metal plate and a lower metal plate, the lower metal plate forming the control terminal of the piezoresistive transistor device and the upper metal plate forming the second load terminal of the piezoresistive transistor device. In Example 14, the subject of one of Examples 1 to 12 may optionally further comprise a housing structure with a first cavity accommodating the first transistor cell and a second cavity accommodating the second transistor cell, the cavities being arranged side by side with respect to a lateral dimension of the housing structure. In Example 15, the subject of Example 14 may optionally include the first body of piezoelectric material and the first body of piezoresistive material being aligned parallel to the lateral dimension of the housing and / or the second body of piezoelectric material and the second body of piezoresistive material being aligned parallel to the lateral dimension of the housing. In Example 16, the subject of Example 14 may optionally include the first body of piezoelectric material and the first body of piezoresistive material being oriented obliquely or perpendicularly to the lateral dimension of the housing and / or the second body of piezoelectric material and the second body of piezoresistive material being oriented obliquely or perpendicularly to the lateral dimension of the housing. In Example 17, the subject of one of the preceding examples may optionally include the fact that the first body made of piezoresistive material and the second body made of piezoresistive material are aligned in different spatial planes that are not parallel to each other. Example 18 is a piezoresistive transistor device comprising a first plurality of transistor cells and a second plurality of transistor cells. Each transistor cell includes a body of piezoelectric material and a body of piezoresistive material, wherein the body of piezoelectric material and the body of piezoresistive material are arranged in a stacked configuration, and the electrical resistance of the body of piezoresistive material depends on a voltage applied across the body of piezoelectric material by means of a pressure exerted by the body of piezoelectric material on the body of piezoresistive material.The piezoresistive transistor device further comprises a control terminal, a first load terminal, a second load terminal and an internal electrical connection configured to electrically connect the electrical resistances of the first plurality of transistor cells in series, electrically connect the electrical resistances of the second plurality of transistor cells in series and electrically connect these two series circuits in parallel. In Example 19, the subject of Example 18 may optionally include the piezoelectric material bodies of the first plurality of transistor cells being configured as a first common piezoelectric material body, the piezoelectric material bodies of the second plurality of transistor cells being configured as a second common piezoelectric material body, and the control terminal being connected to a first control electrode and a second control electrode, the first and second control electrodes being connected to the first common piezoelectric material body and the second common piezoelectric material body, respectively. In Example 20, the subject of Example 18 or 19 may optionally include the first load terminal being connected to one or more first load electrodes of a subset of transistor cells of the first plurality of transistor cells and to one or more first load electrodes of a subset of transistor cells of the second plurality of transistor cells, wherein the one or more first load electrodes are arranged on a side of the bodies of piezoresistive material facing the bodies of piezoelectric material. In Example 21, the subject of one of Examples 18 to 20 may optionally include the second load terminal being connected to one or more second load electrodes of a subset of transistor cells of the first plurality of transistor cells and to one or more second load electrodes of a subset of transistor cells of the second plurality of transistor cells, wherein the one or more second load electrodes are arranged on a side of the bodies of piezoresistive material facing away from the bodies of piezoelectric material. In Example 22, the subject of Examples 18 to 21 may optionally comprise a housing structure with a first cavity accommodating the first plurality of transistor cells and a second cavity accommodating the second plurality of transistor cells, the cavities being arranged side by side with respect to a lateral dimension of the housing structure. In Example 23, the subject of Example 22 may optionally include the first plurality of transistor cells being accommodated in the first cavity, wherein the bodies of piezoelectric material and the bodies of piezoresistive material are oriented obliquely or perpendicularly to the lateral dimension of the housing, and / or the second plurality of transistor cells being accommodated in the second cavity, wherein the bodies of piezoelectric material and the bodies of piezoresistive material are oriented obliquely or perpendicularly to the lateral dimension of the housing. In Example 24, the subject of one of Examples 18 to 23 may optionally include the fact that the piezoresistive transistor device is a power component. In Example 25, the subject of Example 24 may optionally include the piezoresistive transistor device having a threshold voltage in a range between 1.2 V and 30 V. Example 26 is an electronic power module comprising the piezoresistive transistor device from Example 24 or 25, a carrier on which the piezoresistive transistor device is mounted, and a heat sink attached to the carrier. In Example 27, the object from Example 26 can optionally include a temperature sensor mounted on the carrier. Example 28 is a piezoresistive transistor device with a first transistor cell. The first transistor cell comprises a body made of piezoelectric material and a first body made of piezoresistive material. The body made of piezoelectric material and the first body made of piezoresistive material are arranged in a stacked configuration. The first electrical resistance of the first body made of piezoresistive material depends on a voltage applied across the body made of piezoelectric material by means of a pressure exerted on the first body made of piezoresistive material. The piezoresistive transistor device also comprises a second transistor cell. The second transistor cell comprises the body made of piezoelectric material and a second body made of piezoresistive material.The first body, made of piezoelectric material, and the second body, made of piezoresistive material, are arranged in a stacked configuration. The electrical resistance of the second body, made of piezoresistive material, is determined by the pressure exerted on it by the first body, which in turn depends on a voltage applied across the second body. The first and second bodies are oriented in different spatial planes that are not parallel to each other. In Example 29, the subject matter of Example 28 may optionally further comprise a control terminal of the piezoresistive transistor device connected to a control electrode, the control electrode being connected to the body of piezoelectric material; a first terminal of the piezoresistive transistor device, the first terminal being connected to a first electrode of the first transistor cell arranged between the body of piezoelectric material and the first body of piezoresistive material, and to a second electrode of the second transistor cell arranged between the body of piezoelectric material and the second body of piezoresistive material;a second terminal of the piezoresistive transistor device, wherein the second terminal is connected to a second electrode of the first transistor cell, the second electrode of the first transistor cell being arranged on the first body made of piezoresistive material; and a third terminal of the piezoresistive transistor device, wherein the third terminal is connected to a second electrode of the second transistor cell, the second electrode of the second transistor cell being arranged on the second body made of piezoresistive material. In Example 30, the object of Example 28 or 29 may optionally include a third transistor cell comprising the piezoelectric body and a third piezoresistive body, the piezoelectric body and the third piezoresistive body being arranged in a stacked configuration. The electrical resistance of the third piezoresistive body is dependent on the voltage applied across the piezoelectric body by means of a pressure exerted on it by the piezoelectric body. The third piezoresistive body is oriented in a spatial plane that is not parallel to any of the spatial planes in which the first and second piezoresistive bodies are oriented.

[0122] Although specific embodiments have been presented and described herein, the person skilled in the art will recognize that the specific embodiments shown and described can be replaced by a multitude of alternative and / or equivalent implementations without departing from the scope of the present invention. This application is intended to cover all adaptations or variations of the embodiments described herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] Piezoresistive transistor device comprising: a first transistor cell with a first body made of piezoelectric material, and a first body made of piezoresistive material, wherein the first body of piezoelectric material and the first body of piezoresistive material are arranged in a stacked configuration, and a first electrical resistance of the first body of piezoresistive material depends on a voltage applied across the first body of piezoelectric material by means of a pressure exerted by the first body of piezoelectric material on the first body of piezoresistive material; a second transistor cell with a second body made of piezoelectric material, and a second body made of piezoresistive material, wherein the second body of piezoelectric material and the second body of piezoresistive material are arranged in a stacked configuration, and a second electrical resistance of the second body of piezoresistive material depends on a voltage applied across the second body of piezoelectric material by means of a pressure exerted by the second body of piezoelectric material on the second body of piezoresistive material; a control terminal of the piezoresistive transistor device; a first load terminal of the piezoresistive transistor device; a second load terminal of the piezoresistive transistor device; and an internal electrical connection of the piezoresistive transistor device configured to electrically connect the first electrical resistor and the second electrical resistor in series or parallel. [2] A piezoresistive transistor device according to claim 1, wherein the first body of piezoelectric material and the second body of piezoelectric material are formed as a common body of piezoelectric material. [3] A piezoresistive transistor device according to claim 1, wherein the first body of piezoelectric material and the second body of piezoelectric material are separated from each other. [4] A piezoresistive transistor device according to any one of the preceding claims, wherein the control terminal is connected to a control electrode, the control electrode being connected to the first body of piezoelectric material and the second body of piezoelectric material. [5] Piezoresistive transistor device according to one of the preceding claims, wherein in the case that the internal electrical connection is configured to connect the first electrical resistor and the second electrical resistor in parallel, the first load terminal is connected to a first load electrode of the first transistor cell and a first load electrode of the second transistor cell, the first load electrode of the first transistor cell is arranged between the first body of piezoelectric material and the first body of piezoresistive material, and the first load electrode of the second transistor cell is arranged between the second body of piezoelectric material and the second body of piezoresistive material. [6] Piezoresistive transistor device according to one of the preceding claims, wherein in the case that the internal electrical connection is configured to connect the first electrical resistor and the second electrical resistor in parallel, the second load terminal is connected to a second load electrode of the first transistor cell and a second load electrode of the second transistor cell, the second load electrode of the first transistor cell is arranged on a side of the first body of piezoresistive material facing away from the first body of piezoelectric material, and the second load electrode of the second transistor cell is arranged on a side of the second body of piezoresistive material facing away from the second body of piezoelectric material. [7] Piezoresistive transistor device according to claim 5 or 6, wherein the first electrical resistance is a resistance to a load current flowing in a direction perpendicular to the first body of piezoresistive material, and the second electrical resistance is a resistance to a load current flowing in a direction perpendicular to the second body of piezoresistive material. [8] The piezoresistive transistor device according to any one of claims 1 to 4, wherein in the case where the internal electrical connection is configured to connect the first electrical resistor and the second electrical resistor in series, the first load terminal is connected to a first load electrode of the first transistor cell disposed between the first body of piezoelectric material and the first body of piezoresistive material, and a second load electrode of the first transistor cell is connected to a first load electrode of the second transistor cell, the first load electrode of the second transistor cell not being connected to the first load terminal. [9] A piezoresistive transistor device according to claim 8, wherein the second load terminal is connected to the second load electrode of the second transistor cell. [10] A piezoresistive transistor device according to claim 8 or 9, wherein the first and second load electrodes of the second transistor cell are arranged on a side of the second body of piezoresistive material facing away from the second body of piezoelectric material. [11] Piezoresistive transistor device according to one of claims 8 to 10, wherein the first electrical resistance is a resistance to a load current flowing in a direction perpendicular to the first body of piezoresistive material, and the second electrical resistance is a resistance to a load current flowing at least partially in a direction parallel to the second body of piezoresistive material. [12] Piezoresistive transistor device according to claim 8 or 9, wherein the first electrical resistance is a resistance to a load current flowing in a direction perpendicular to the first body of piezoresistive material, and the second electrical resistance is a resistance to a load current flowing in a direction perpendicular to the second body of piezoresistive material. [13] A piezoresistive transistor device according to any one of the preceding claims, further comprising a housing structure having at least one cavity for receiving the first transistor cell and the second transistor cell, the housing structure comprising an upper metal plate and a lower metal plate, the lower metal plate forming the control terminal of the piezoresistive transistor device and the upper metal plate forming the second load terminal of the piezoresistive transistor device. [14] A piezoresistive transistor device according to any one of claims 1 to 12, further comprising: a package structure having a first cavity accommodating the first transistor cell and a second cavity accommodating the second transistor cell, the cavities being arranged adjacent to each other with respect to a lateral dimension of the package structure. [15] A piezoresistive transistor device according to claim 14, wherein the first body of piezoelectric material and the first body of piezoresistive material are aligned parallel to the lateral dimension of the housing and / or the second body of piezoelectric material and the second body of piezoresistive material are aligned parallel to the lateral dimension of the housing. [16] Piezoresistive transistor device according to claim 14, wherein the first body of piezoelectric material and the first body of piezoresistive material are aligned obliquely or perpendicularly to the lateral dimension of the housing and / or the second body of piezoelectric material and the second body of piezoresistive material are aligned obliquely or perpendicularly to the lateral dimension of the housing. [17] A piezoresistive transistor device according to any one of the preceding claims, wherein the first body of piezoresistive material and the second body of piezoresistive material are aligned in different spatial planes that are not parallel to each other. [18] Piezoresistive transistor device comprising: a first plurality of transistor cells and a second plurality of transistor cells, each transistor cell comprising a body made of piezoelectric material, and a body made of piezoresistive material, where the body of piezoelectric material and the body of piezoresistive material are arranged in a stacked configuration, and an electrical resistance of the body made of piezoresistive material by means of a pressure exerted by the body made of piezoelectric material on the body made of piezoresistive material depends on a voltage applied across the body made of piezoelectric material; a control terminal of the piezoresistive transistor device; a first load terminal of the piezoresistive transistor device; a second load terminal of the piezoresistive transistor device; and an internal electrical connection of the piezoresistive transistor device configured to electrically connect the electrical resistances of the first plurality of transistor cells in series, to electrically connect the electrical resistances of the second plurality of transistor cells in series, and to electrically connect these two series circuits in parallel. [19] Piezoresistive transistor device according to claim 18, wherein the bodies of piezoelectric material of the first plurality of transistor cells are formed as a first common body of piezoelectric material; the bodies of piezoelectric material of the second plurality of transistor cells are formed as a second common body of piezoelectric material; and the control terminal is connected to a first control electrode and a second control electrode, wherein the first and second control electrodes are connected to the first common body of piezoelectric material and to the second common body of piezoelectric material, respectively. [20] A piezoresistive transistor device according to claim 18 or 19, wherein the first load terminal is connected to one or more first load electrodes of a subset of transistor cells of the first plurality of transistor cells and to one or more first load electrodes of a subset of transistor cells of the second plurality of transistor cells, wherein the one or more first load electrodes are arranged on a side of the bodies of piezoresistive material that faces the bodies of piezoelectric material. [21] Piezoresistive transistor device according to one of claims 18 to 20, wherein the second load terminal is connected to one or more second load electrodes of a subgroup of transistor cells of the first plurality of transistor cells and to one or more second load electrodes of a subgroup of transistor cells of the second plurality of transistor cells, wherein the one or more second load electrodes are arranged on a side of the piezoresistive material bodies facing away from the bodies of piezoelectric material. [22] A piezoresistive transistor device according to any one of claims 18 to 21, further comprising: a package structure having a first cavity accommodating the first plurality of transistor cells and a second cavity accommodating the second plurality of transistor cells, the cavities being arranged adjacent to each other with respect to a lateral dimension of the package structure. [23] Piezoresistive transistor device according to claim 22, wherein the first plurality of transistor cells are received in the first cavity, the bodies of piezoelectric material and the bodies of piezoresistive material being oriented obliquely or perpendicularly to the lateral dimension of the housing, and / or the second plurality of transistor cells are received in the second cavity, the bodies of piezoelectric material and the bodies of piezoresistive material being oriented obliquely or perpendicularly to the lateral dimension of the housing. [24] A piezoresistive transistor device according to any one of the preceding claims, wherein the piezoresistive transistor device is a power device. [25] The piezoresistive transistor device of claim 24, wherein the piezoresistive transistor device has a threshold voltage in a range between 1.2 V and 30 V. [26] Electronic power module comprising: the piezoresistive transistor device according to claim 24 or 25; a carrier on which the piezoresistive transistor device is mounted; and a heat sink attached to the carrier. [27] The electronic power module of claim 26, further comprising: a temperature sensor mounted on the carrier. [28] Piezoresistive transistor device comprising: a first transistor cell with a body made of piezoelectric material, and a first body made of piezoresistive material, wherein the body of piezoelectric material and the first body of piezoresistive material are arranged in a stacked configuration, and a first electrical resistance of the first body of piezoresistive material depends on a voltage applied across the body of piezoelectric material by means of a pressure exerted by the body of piezoelectric material on the first body of piezoresistive material; a second transistor cell with the body made of piezoelectric material, and a second body made of piezoresistive material, where the body of piezoelectric material and the second body of piezoresistive material are arranged in a stacked configuration, and a second electrical resistance of the second body of piezoresistive material depends on the voltage applied across the body of piezoelectric material by means of a pressure exerted by the body of piezoelectric material on the second body of piezoresistive material; wherein the first body made of piezoresistive material and the second body made of piezoresistive material are aligned in different spatial planes that are not parallel to each other. [29] A piezoresistive transistor device according to claim 28, further comprising: a control terminal of the piezoresistive transistor device connected to a control electrode, the control electrode being connected to the body of piezoelectric material; a first terminal of the piezoresistive transistor device, the first terminal being connected to a first electrode of the first transistor cell disposed between the body of piezoelectric material and the first body of piezoresistive material, and to a second electrode of the second transistor cell disposed between the body of piezoelectric material and the second body of piezoresistive material; a second terminal of the piezoresistive transistor device, the second terminal being connected to a second electrode of the first transistor cell, the second electrode of the first transistor cell being arranged on the first body of piezoresistive material; and a third terminal of the piezoresistive transistor device, the third terminal being connected to a second electrode of the second transistor cell, the second electrode of the second transistor cell being arranged on the second body of piezoresistive material. [30] A piezoresistive transistor device according to claim 28 or 29, further comprising a third transistor cell comprising: the body made of piezoelectric material, and a third body made of piezoresistive material, where the body of piezoelectric material and the third body of piezoresistive material are arranged in a stacked configuration, and a third electrical resistance of the third body of piezoresistive material depends on the voltage applied across the body of piezoelectric material by means of a pressure exerted by the body of piezoelectric material on the third body of piezoresistive material, wherein the third body made of piezoresistive material is aligned in a spatial plane that is not parallel to any of the spatial planes in which the first body made of piezoresistive material and the second body made of piezoresistive material are aligned.

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