DISPLAY DEVICE

Abstract

Display device comprising: a display panel (100) comprising a display area (120) and a non-display area (130) adjacent to the display area (120) and containing gate lines (GL); a left gate drive (200a) provided in a first non-display area (131) of the non-display area (130) to output left gate pulses (L_GP) and left gate off signals (L_Goff) to the gate lines (GL); and a right gate drive (200b) provided in a second non-display area (132) of the non-display area (130) to output right gate pulses (R_GP) and right gate off signals (R_Goff) to the gate lines (GL), wherein the left gate drive (200a) comprises an nth left stage (L_Stage n) that outputs an nth left gate pulse (L_GPn), and the right gate drive (200b) comprises an nth right stage (R_Stage n) that outputs an nth right gate pulse (R_GPn), where n is a natural number,wherein the nth left stage (L_Stage n) of the left gate drive (200a) comprises an nth left Q node and the nth right stage (R_Stage n) of the right gate drive (200b) comprises an nth right Q node, wherein an output of the nth left gate pulse (L_GPn) and the nth right gate pulse (R_GPn) is controlled by the nth left Q node and the nth right Q node, and wherein the nth left stage (L_Stage n) comprises an nth left ripple transistor (L_Trpn) for removing ripple occurring in the nth left Q node of the nth left stage and the nth right stage (R_Stage n) comprises an nth right ripple transistor (R_Trpn) to remove a ripple occurring in the nth right Q node of the nth right stage includes,wherein the nth left stage (L_Stage n) comprises a left signal generator (210a) and a left signal output unit (220a) and the nth right stage (R_Stage n) comprises a right signal generator (210b) and a right signal output unit (220b), and wherein a gate-off signal (Goff) is alternately output by the left stage and the right stage, which are provided on both sides of a gate line (GL), in order to continuously output the gate-off signal (Goff) to the gate line.

Description

This application claims priority over Korean patent application No. 10-2021-0186121, filed on December 23, 2021 in the Republic of Korea. BACKGROUND OF THE INVENTION Field of invention The present invention relates to a display device. Discussion of the state of the art Display devices include liquid crystal display devices (LCD devices) and light-emitting display devices. Each of these display devices can include a display panel that shows an image. The display devices include a gate control system, which contains stages for outputting gate signals to gate lines contained in the display panel. A gate control system outputs gate-on and gate-off signals to the gate lines of the display panel. During a frame, each gate line is activated once by applying a gate-on signal. Other control schemes for controlling multiple gate lines during a single frame are possible. The time during which a gate drive stage outputs a gate-off signal can be longer than the time during which a gate pulse (gate-on signal) is output. While the gate-off signal is being output, a gate clock for outputting the gate pulse can be continuously supplied to the stage, potentially creating ripple that impairs the stage's control. To remove the adverse effect of the ripple, a transistor could be used to remove the ripple in the prior art. However, a transistor for removing ripple is an additional component that requires more space. Furthermore, the ripple-removal transistor can be damaged, and removing the ripple can be difficult if the transistor is damaged. Additionally, a dummy transistor must be added to determine the degree of damage to the ripple-removal transistor, and the voltage applied to the ripple-removal transistor must be varied based on the degree of damage. As a result, several additional components may be required. KR 10 2007 0 080 161 A describes a liquid crystal display with a gate driver formed on the panel by thin-film processes, which controls several gate and data lines as well as pixels and includes a pre-load function. US 2008 / 0 136 756 A1 describes a liquid crystal display device with a gate driver shift register, whose symmetrically divided circuit parts drive each gate line from both ends during ripple-through scanning, and a timing controller that adjusts the load signal and thus the data output time for the currently activated image line based on a delay feedback signal. US 2018 / 0 122 322 A1 describes a gate driver with cascaded stages, each of which provides a voltage to the next stage or to a gate line of a display panel via two outputs, wherein each stage includes a first diode between the clock input and the first output and is used in a display device. SUMMARY OF THE REVELATION Accordingly, the present invention is directed towards the creation of a display device that essentially prevents one or more problems arising from limitations and disadvantages of the prior art. One object of the present invention is to provide a display device in which the effect of removing the ripple during the output of the gate-off signal is reduced. According to the invention, it is proposed to provide a left ripple transistor, which is provided in a left stage, and a right ripple transistor, which is provided in a right stage of the gate drive. The left ripple transistor is provided in a left stage to remove the ripple occurring in a Q node of the left stage, and the right ripple transistor is provided in the right stage to remove the ripple occurring in a Q node of the right stage and to perform a turn-on and turn-off operation repeatedly and simultaneously. The problem is solved by the features of the independent claim. Preferred embodiments are specified in the dependent claims. To achieve these and other advantages, and in accordance with the purpose of the invention as embodied herein and generally described, a display device is provided comprising a display panel with a display area and a non-display area surrounding the display area, which contains gate lines; a left-gate drive provided in a first non-display area of ​​the non-display area to output left-gate pulses and left-gate off signals to the gate lines; and a right-gate drive provided in a second non-display area of ​​the non-display area to output right-gate pulses and right-gate off signals to the gate lines, wherein the left-gate drive includes an nth left stage that outputs an nth left-gate pulse, and the right-gate drive includes an nth right stage that outputs an nth right-gate pulse (where n is a natural number).Outputs of the nth left gate pulse and the nth right gate pulse are controlled by Q nodes contained in the nth left stage and the nth right stage, respectively, and an nth left ripple transistor provided in the nth left stage to remove the ripple occurring at the nth left Q node of the nth left stage, and an nth right ripple transistor provided in the nth right stage to remove the ripple occurring at the nth right Q node, repeatedly perform a turn-on and a turn-off operation. According to the invention, the nth left stage comprises a left signal generator and a left signal output unit, and the nth right stage comprises a right signal generator and a right signal output unit, wherein a gate-off signal is alternately output by the left stage and the right stage, which are provided on both sides of a gate line, in order to continuously output the gate-off signal to the gate line. The left and right stages can be connected to the same gate line. The left and right stages alternately output a gate-off signal to the gate line. Thus, the gate-off signal is continuously supplied to the gate line from both sides. The left and right stages can each contain a ripple transistor. The ripple transistors of the left and right stages are controlled so that they continuously output a gate-off signal to the gate line during the gate-off lead times. It should be understood that both the preceding general description and the following detailed description of the present revelation are exemplary and explanatory and serve to further explain the claimed revelation. [→Page 3] BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included for a further understanding of the invention and are integrated into the application and form part thereof, depict embodiments and, together with the description, serve to explain the principle of the invention; they show: Fig. 1 a diagram representing a configuration of a display device of an embodiment of the invention; Figs. 2A and 2B diagrams showing examples of a pixel structure applied to the display device of an embodiment of the present invention; Fig. 3 a diagram representing a control unit structure applied to the display device of an embodiment of the present invention; Fig. 4 a diagram representing a structure of each of the gate controls applied to the display device of an embodiment of the present invention; Fig. 5 a diagram schematically representing a structure of each of the gate controls shown in Fig.Figure 4 represents the stages shown; Figure 6 is a diagram accurately representing the structure of each of the stages shown in Figure 4; Figure 7 is a diagram showing waveforms applied to a display device of an embodiment of the invention; Figure 8 is a diagram showing a method for outputting a gate-off signal in a display device of an embodiment of the present invention; Figure 9 is another diagram accurately representing the structure of each of the stages shown in Figure 4; and Figure 10 is a diagram showing waveforms applied to the stages shown in Figure 9. DETAILED DESCRIPTION OF THE EXECUTION FORMS Reference will now be made in detail to the exemplary embodiments of the present invention, for which examples are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used throughout the drawings to refer to identical or similar parts. The advantages and features of the present invention and methods for its implementation are illustrated by the following embodiments, which are described with reference to the accompanying drawings. However, the present invention can be implemented in various forms and should not be considered limited to the embodiments presented here. Rather, these embodiments are provided to ensure that this invention is thorough and complete and fully conveys to those skilled in the art the scope of protection of the invention as defined by the independent claims. A shape, size, ratio, angle, and number disclosed in the drawings to describe embodiments of the present invention are merely examples, and therefore the present invention is not limited to the details shown. The same reference numerals refer to the same elements throughout. In the following description, if a precise description of the relevant known function or configuration would be determined to unnecessarily obscure the important point of the present invention, the precise description will be omitted. When the terms “comprise,” “have,” and “include” are used in this specification, a further part may be added unless “only” is used. Singular terms may include the plural forms unless otherwise indicated. When interpreting an element, the element is interpreted as containing an error or tolerance range, even if no explicit description of such an error or tolerance range exists. When describing a positional relationship, for example, when a positional relationship between two parts is described as "on", "above", "below" and "next to", one or more other parts may be positioned between the two parts unless a more restrictive term such as "immediately" or "directly" is used. When describing a temporal relationship, for example, when the temporal sequence is described as "after", "subsequent", "next" and "before", a non-continuous case may be included unless a more restrictive term such as "immediately", "as soon as" or "directly" is used. It is to be understood that, although the terms "first," "second," etc., may be used here to describe different elements, these elements should not be restricted by these terms. These terms are used only to distinguish one element from another. A first element could, for example, be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of protection of the present invention. In describing elements of this disclosure, the terms “first”, “second”, “A”, “B”, “(a)”, “(b)”, etc., may be used. These terms serve to distinguish the corresponding elements from the other elements, and the basis, sequence, or number of the corresponding elements should not be limited by these terms. The expression that an element is “connected”, “coupled”, or “attached” to another element or layer means that the element or layer may not only be directly connected or attached to another element or layer, but may also be indirectly connected or attached to another element or layer, with one or more elements or layers being “arranged” or “inserted” between the elements or layers, unless otherwise specified. The term "at least one" is to be understood as including any or all combinations of one or more of the listed elements. For example, the meaning of "at least one of a first, a second, and a third element" refers to the combination of all elements that can be derived from two or more of the first, the second, and the third elements, as well as the first, the second, or the third element. Features of different embodiments of the present invention can be partially or completely coupled or combined with one another, and they can interact and be controlled technically in various ways, as those skilled in the art can reasonably understand. The embodiments of the present invention can be carried out independently of one another, or they can be carried out together in a relationship of mutual dependence. The embodiments of the present invention are described in detail below with reference to the accompanying drawings. Furthermore, all components of each display device of all embodiments of the present invention are operationally coupled and configured. Fig. 1 is a diagram illustrating a configuration of a display device of an embodiment of the present invention. Figs. 2A and 2B are diagrams illustrating examples of a pixel structure applied to a display device of the present invention. Fig. 3 is a diagram illustrating a control unit structure applied to a display device of an embodiment of the present invention. The display device of the present invention can configure various electronic devices. These electronic devices can include, for example, smartphones, tablet personal computers (tablet PCs), televisions (TVs), and monitors. The display device of the present invention, as shown in Fig. 1, can include a display panel 100 with a display area 120 that shows an image and a non-display area 130 located outside the display area 120; several gate controllers 200a and 200b that supply a gate signal to the several gate lines GL1 to GLg provided in the display area 120 of the display panel 100; a data controller 300 that supplies data voltages to several data lines DL1 to DLd provided in the display panel 100; a control unit 400 that controls the control of the gate controllers 200a and 200b and the data controller 300; and a power supply 500 that supplies the control unit 400, the gate controllers 200a and 200b, the data controller 300, and The display board is supplied with power by 100. Initially, the display panel 100 can contain the display area 120 and the non-display area 130. The gate lines GL1 to GLg, the data lines DL1 to DLd, and the pixels 110 can be located within the display area 120. Accordingly, the display area 120 can display an image. Here, g and d can each be a natural number, e.g., a positive integer. In particular, g can be an even number. The non-display area 130 can surround or partially surround the display area 120. The display panel 100 can be a liquid crystal display panel containing the pixel 110 shown in Fig. 2A, or it can be a light-emitting display panel containing the pixel 110 shown in Fig. 2B. If, for example, the display panel 100 is the liquid crystal display panel as shown in Fig. 2A, the pixel 110 contained in the display panel 100 includes a pixel drive circuit (PDC) comprising a switching transistor Tsw1 and a common electrode, as well as a liquid crystal layer. The liquid crystal layer may be contained within an emission region. In Fig. 2, Clc can represent the liquid crystal located between the common electrode and a pixel electrode connected to the switching transistor Tsw1. If, for example, the display panel 100 is a light-emitting display panel, as shown in Fig. 2B, the pixel 110 contained in the display panel 100 includes a pixel control circuit PDC, which includes a switching transistor Tsw1, a storage capacitor Cst, a drive transistor Tdr and a detection transistor Tsw2, as well as an emission area which includes a light-emitting device ED. A structure of pixel 110 of the liquid crystal display panel and a structure of pixel 110 of the light-emitting display panel are not limited to the structure shown in Fig. 2A and Fig. 2B and can therefore be implemented as different types. For example, the display device of the present invention can be an LCD device containing the liquid crystal display panel, or it can be a light-emitting display device containing the light-emitting display panel, but is not limited to this and can be a display device containing various types of display panels. Since the invention mainly deals with improvements to the gate control and both types of display panels are supplied with gate signals, the invention can be applied to both types of display panels. For the sake of simplicity, a display device containing a light-emitting display panel is described below as an example of the present invention. The data controller 300 can be mounted on a chip-on-film attached to the display panel 100. In this case, the data controller 300 can be connected to the control unit 400, which is mounted on a main substrate, via the data lines DL1 to DLd contained in the display panel 100. The data control unit 300 can be installed directly in the display panel 100 and then connected to the control unit 400, which is provided in the main substrate. The data control unit 300 can be implemented as an integrated circuit (IC) together with the control unit 400. In this case, the IC can be mounted on the chip-on-film or can be directly integrated into the display panel 100. The control unit 400 can realign the input video data Ri, Gi and Bi transmitted by an external system using a time synchronization signal TSS transmitted by the external system and can generate data control signals DCS to be supplied to the data control 300 and gate control signals GCS to be supplied to the gate controls 200a and 200b. For this purpose, as shown in Fig. 3, the control unit 400 can include a data aligner 430, which realigns the input video data Ri, Gi and Bi to generate image data Data, and supplies the image data Data to the data control unit 300; a control signal generator 420, which generates the gate control signal GCS and the data control signal DCS using the time synchronization signal TSS; an input unit 410, which receives the time synchronization signal TSS and the input video data Ri, Gi and Bi transmitted by the external system and sends the time synchronization signal TSS and the input video data Ri, Gi and Bi to the data aligner 430 and the data control unit 300, respectively.the control signal generator 420 transmits, and an output unit 440 which supplies the image data Data, generated by the data aligner 430, and the data control signal DCS, generated by the control signal generator 420, to the data control 300 and supplies the gate control signals GCS, generated by the control signal generator 420, to the gate controls 200a and 200b. The external system can perform a function to control the control unit 400 and an electronic device. For example, if the electronic device is a television, the external system can receive various audio, video, and text information via a communication network and transmit the received video information to the control unit 400. In this case, the video information can include the input video data Ri, Gi, and Bi. The power supply 500 can generate different power levels and supply the generated power to the control unit 400, the gate controls 200a and 200b, the data control 300 and the display panel 100. Finally, the gate drive 200 can be implemented as an IC and can be located in the non-display area 130. Alternatively, the gate drive 200 can be embedded directly in the non-display area 130 using a gate-in-panel (GIP) type. If the GIP type is used, the transistors that configure the gate drive 200 can be provided in the non-display area via the same process as the transistors contained in each pixel 110. When the gate pulse generated by each of the gate drives 200a and 200b is applied to a gate of the switching transistor Tsw1 contained in pixel 110, the switching transistor Tsw1 can be switched on. When the switching transistor Tsw1 is switched on, a data voltage supplied via a data line DL can be supplied to pixel 110. When a gate-off signal generated by each of the gate drives 200a and 200b is applied to the switching transistor Tsw1, the switching transistor Tsw1 can be switched off. When the switching transistor Tsw1 is switched off, the data voltage Vdata can no longer be supplied to pixel 110. The gate signal GS supplied to the gate line GL can contain a gate pulse and a gate-off signal. According to the invention, as shown in Fig. 1, two gate controls 200a and 200b are provided. A gate control 200a is provided in a first non-display area 131, which is located on the left side of the display panel 100, e.g., on the left side of the gate lines GL, in the non-display area 130. In the following description, a gate control provided in the first non-display area 131 can simply be referred to as a left gate control 200a. The other gate control 200n is provided in a second non-display area 132, which is located on the right side of the display panel 100, e.g., on the left side of the gate lines GL, in non-display area 130. In the following description, a gate control provided in the second non-display area 132 may simply be referred to as a right gate control 200b. In this case, the second non-display area 132 can be positioned opposite the first non-display area 131, but is not limited to this. For example, the positions of the first non-display area 131 and the second non-display area 132 can be modified based on the type of gate lines provided. Furthermore, in the following description, a left side and a right side can refer to one side and the other side of a gate line and are therefore not limited to a left and a right side. They can also be located on the upper and lower sections of the display panel in the non-display area or any other section. Thus, the left and right gate drives could also be referred to as the first and second gate drives. The exact structures and functions of the left gate drive 200a and the right gate drive 200b are described below with reference to Figures 4, 5, 6, 7, 8, 9 to 10. In the following, the term "gate drive 200" is used interchangeably to describe both the left gate drive 200a and the right gate drive 200b. Fig. 4 is a diagram showing a structure of each of the gate controls applied to a display device of an embodiment of the present invention. In Fig. 4, the reference symbols L_GCS and R_GCS refer to a left gate control signal, which is supplied to the left gate control 200a, and a right gate control signal, which is supplied to the right gate control 200b. The left gate control signal L_GCS and the right gate control signal R_GCS can be generated by the control signal generator 420. As described above, the display panel 100 can contain the display area 120 and the non-display area 130 that at least partially surrounds the display area 120, and the gate lines GL1 to GLg can be included in the display panel 100. The left gate drive 200a can be located in the first non-display area 131 of the non-display area 130 and can output left gate pulses L_GP1 to L_GPg and left gate off signals L_Goff1 to L_Goffg to the gate lines GL1 to GLg. In Fig. 4, the reference symbols L_GS1 to L_GSg can refer to the first to g-th left gate signals. For example, the first left gate signal L_GS1 can contain a first left gate pulse L_GP1 and a first left gate off signal L_Goff1, and the g-th left gate signal L_GSg can contain a g-th left gate pulse L_GPg and a g-th left gate off signal L_Goffg. The right gate drive 200b can be located in the second non-display area 132 of the non-display area 130 and can output right gate pulses R_GP1 to R_GPg and right gate off signals R_Goff1 to R_Goffg to the gate lines GL1 to GLg. In Fig. 4, the reference symbols R_GS1 to R_GSg can refer to the first to g-th right gate signals. For example, the first right gate signal R_GS1 can contain a first right gate pulse R_GP1 and a first right gate off signal R_Goff1, and the g-th right gate signal R_GSg can contain a g-th right gate pulse R_GPg and a g-th right gate off signal R_Goffg. Furthermore, at least one gate line GL1 can be provided on or assigned to the first gate line GL1 in the non-display area 130, and at least one gate line can also be provided on or assigned to the g-th gate line GLg in the non-display area 130. As shown in Fig. 1, on the display panel 100 two dummy gate lines GL-1 and GL-2 are provided on (above in the top view) the first gate line GL1, and two dummy gate lines GL+1 and GL+2 are provided below (below in the top view) the g-th gate line GLg. Furthermore, a dummy gate line GLn-1 could be located above gate line GLn and a dummy gate line GLn+1 below gate line GLn. However, the arrangement of the one or more dummy gate lines is not restricted, and the one or more dummy gate lines could also be located elsewhere (above or below the respective gate line GLn in the sectional view). In this case, the left gate control 200a and the right gate control 200b can also output gate pulses and gate off signals to one or more dummy gate lines. The left gate drive 200a can contain the first to the gth left gate stages L_Stage 1 to L_Stage g. Each of the first to the gth left gate stages L_Stage 1 to L_Stage g can output at least one gate pulse. If all gate pulses are to be described in the following description, the order of the gate pulses is not required, or it is not necessary to restrict a gate drive that outputs a gate pulse, then a gate pulse can be used as a simple expression. If a generic name is required for all stages, or the order of the gate pulses is not required, then a stage can be used as a simple expression. If a generic name is required for all gate-off signals, or the order of the gate-off signals is not required, then a gate-off signal can be used as a simple expression.Furthermore, in the following description, a stage that outputs an nth left-gate pulse L_GPn and an nth left-gate off-signal L_Goffn can be referred to as an nth left-stage L_Stage n. Here, n can be a natural number less than or equal to g. For example, n can be a positive integer. The right-gate drive 200b can contain the first to g-th right-gate stages R_Stage 1 to R_Stage g. Each of the first to g-th right-gate stages R_Stage 1 to R_Stage g can output at least one gate pulse. In the following description, a stage that outputs an n-th right-gate pulse R_GPn and an n-th right-gate off signal R_Goffn can be referred to as an n-th right-gate stage R_Stage n. The present invention is described below with reference to the nth left stage L_Stage n and the nth right stage R_Stage n. The following descriptions of the nth left stage L_Stage n and the nth right stage R_Stage n can be applied equally to the other stages. Fig. 5 is a diagram that schematically represents a structure of each of the stages shown in Fig. 4, and in particular is a diagram that schematically represents the nth left stage L_Stage n and the nth right stage R_Stage n. Each stage can contain multiple transistors. Each stage can receive multiple gate control signals (GCS). Each stage can generate gate pulses using different types of signals and voltages and can sequentially supply the gate pulses to the gate lines GL1 to GLg. Each stage of the L and R stages can contain a signal generator 210a and a signal output stage 220a. According to the invention, the signal generator 210a includes a ripple transistor Trpn. For this purpose, as shown in Fig. 5, the nth left stage L_Stage n can include an nth left signal generator 210a, which includes an nth left ripple transistor L_Trpn and an nth left signal output unit 220a, which outputs an nth left gate off signal L_Goffn and an nth left gate pulse L_GPn based on an nth left control signal generated by the nth left signal generator 210a. The nth right stage R_Stage n can contain an nth right signal generator 210b, which includes an nth right ripple transistor R_Trpn and an nth right signal output unit 220b, which outputs an nth right gate off signal R_Goffn and an nth right gate pulse R_GPn based on an nth right control signal generated by nth right signal generator 210b. In this case, the nth left gate off signal L_Goffn and the nth right gate off signal R_Goffn can be alternately output to an nth gate line GLn. The nth left signal output unit 220a can include an nth left pull-up transistor L_Tun, which outputs the nth left gate pulse L_GPn, and an nth left pull-down transistor L_Tdn, which outputs the nth left gate off signal L_Goffn. A capacitor C for stabilizing an output can be provided between an output terminal and a gate of the nth left pull-up transistor L_Tun. The nth left signal generator 210a can generate signals to control the nth left pull-up transistor L_Tun and the nth left pull-down transistor L_Tdn. The nth right-hand signal output unit 220b can include an nth right-hand pull-up transistor R_Tun, which outputs the nth right-hand gate pulse R_GPn, and an nth right-hand pull-down transistor R_Tdn, which outputs the nth right-hand gate off signal R_Goffn. A capacitor C for stabilizing an output can be provided between an output terminal and a gate of the nth right-hand pull-up transistor R_Tun. The nth right signal generator 210b can generate signals to control the nth right pull-up transistor R_Tun and the nth right pull-down transistor R_Tdn. First, the nth left-hand signal generator 210a can contain several transistors. In Fig. 5, to describe a basic structure and function of the nth left-hand signal generator 210a of the present invention, the nth left-hand signal generator 210a contains three transistors Tst, Trs, and L_Trpn and an inverter IN. An example of the nth left-hand signal generator 210a applied to the present invention is shown schematically in Fig. 5. A start transistor Tst can be switched on by a start signal Vst and can supply a high voltage VD to the left signal output unit 220a via an nth left Q node L_Qn. The high voltage VD passing through the start transistor Tst can be shifted by the inverter IN to a voltage lower than the high voltage and can be applied to an nth left Qb node L_Qbn. Thus, the inverter IN shifts the voltage levels. When the start transistor Tst is switched on and a reset transistor Trs is switched on by a reset signal Rest, a low voltage GVSS can be applied to the nth left Qb node L_Qbn via the reset transistor Trs. The low voltage GVSS can be shifted by the inverter IN to a voltage higher than the initial low voltage and applied to the nth left Qb node L_Qbn. The inverter IN can be implemented in various structures, each containing at least one transistor, to perform the function described above. A first terminal of the nth left ripple transistor L_Trpn can be connected to the nth left Q node L_Qn, a second terminal of the nth left ripple transistor L_Trpn can be connected to a first voltage terminal, and a gate of the nth left ripple transistor L_Trpn can be connected to a gate of the nth left pull-down transistor L_Tdn, which controls an output of the nth left gate off signal L_Goffn. Here, the first voltage terminal can be supplied with the low voltage GVSS. For example, the first voltage terminal can be supplied with the low voltage GVSS to switch off the nth left pull-up transistor L_Tun. A gate of the nth left ripple transistor L_Trpn and a gate of the nth left pull-down transistor L_Tdn can be connected to a terminal to which an nth left ripple clock L_DCLK(n) is supplied. Accordingly, the gate of the nth left ripple transistor L_Trpn and the gate of the nth left pull-down transistor L_Tdn can be supplied with the nth left ripple clock L_DCLK(n). Secondly, the nth right-hand signal generator 210b can contain several transistors. In order to describe a basic structure and function of the nth right-hand signal generator 210b of the present invention, which is used in the present invention, the nth right-hand signal generator 210b, which contains three transistors Tst, Trs and L_Trpn and an inverter IN, is shown in Fig. 5. For example, an example of the nth right-hand signal generator 210b applied to the present invention is shown schematically in Fig. 5. A start transistor Tst can be switched on by the start signal Vst and can supply the high voltage VD to the right signal output unit 220b via an nth right Q node R_Qn. When the start transistor Tst is switched off and a reset transistor Trs is switched on by the reset signal Rest, a low voltage can be applied to the nth right Q-node R_Qn via the reset transistor Trs GVSS. The inverter IN can be implemented in various structures, each containing at least one transistor. A first terminal of the nth right ripple transistor R_Trpn can be connected to the nth right Q node R_Qn, a second terminal of the nth right ripple transistor R_Trpn can be connected to the first voltage terminal, and a gate of the nth right ripple transistor R_Trpn can be connected to a terminal to which an nth right ripple clock R_DCLK(n) is supplied. Therefore, the nth right ripple clock R_DCLK(n) can be supplied to the gate of the nth right ripple transistor R_Trpn. As described above, the gate of the nth left ripple transistor L_Trpn can be connected to a gate of the nth left pull-down transistor L_Tdn, which controls an output of the nth left gate off signal L_Goffn. The gate of the nth right ripple transistor R_Trpn need not be connected to the gate of the nth right pull-down transistor R_Tdn, which controls an output of the nth right gate off signal R_Goffn. The gate of the nth right pull-down transistor R_Tdn can be connected to the gate of an n+1th right ripple transistor contained in a stage (for example, an n+1th right stage) adjacent to an nth right stage R_Stage n. In this case, the gate of the nth right ripple transistor R_Trpn can be connected to the gate of an n-1th right pull-down transistor contained in a preceding stage (for example, an n-1th right stage) with respect to the nth right stage R_Stage n. To provide an additional description, the outputs of the nth left gate off signal L_Goffn and the nth right gate off signal R_Goffn can be controlled by Qb nodes contained in the nth left stage L_Stage n and the nth right stage R_Stage n, respectively. In this case, a gate of an nth left ripple transistor L_Trpn and an nth left Qb node L_Qbn contained in the nth left stage L_Stage n can be connected together, and an nth right Qb node R_Qbn contained in the nth right stage R_Stage n can be connected to a gate of an n+1th right ripple transistor contained in an n+1th right stage. Thirdly, the nth left signal output unit 220a can contain an nth left pull-up transistor L_Tun which outputs an nth left gate pulse L_GPn, and a gate of the nth left pull-up transistor L_Tun can be connected to an nth left Q node L_Qn. The nth left signal output unit 220a can contain an nth left pull-down transistor L_Tdn which outputs an nth left gate off signal L_Goffn, and a gate of the nth left pull-down transistor L_Tdn can be connected to a gate of an nth left ripple transistor L_Trpn. Fourth, the nth right signal output unit 220b can contain an nth right pull-up transistor R_Tun which outputs an nth right gate pulse R_GPn, and a gate of the nth right pull-up transistor R_Tun can be connected to an nth right Q node R_Qn. The nth right signal output unit 220b can contain an nth right pull-down transistor R_Tdn which outputs an nth right gate off signal R_Goffn, and a gate of the nth right pull-down transistor R_Tdn can be connected to a gate of an n+1th right ripple transistor which is contained in a stage (for example, an n+1th right stage) next to the nth right stage R_Stage n. Fig. 6 is a diagram that accurately represents the structure of each of the stages shown in Fig. 4. The basic structure of each of the n-1th to n+1th left stages L_Stage n-1 to L_Stage n+1 and the n-1th to n+1th right stages R_Stage n-1 to R_Stage n+1 can be the same as the basic structure of each of the nth left stage L_Stage n and the nth right stage R_Stage n described above with reference to Fig. 5. Therefore, descriptions that are the same as or similar to those given above with reference to Fig. 5 have been omitted or are given briefly below. First, the n-1th to n+1th left stages L_Stage n-1 to L_Stage n+1 shown in Fig. 6 can be implemented as the same type. Therefore, a structure of the nth left stage L_Stage n is described below. In contrast to the nth left stage shown in Fig. 5, the structure of an inverter IN shown in detail is depicted in the nth left stage L_Stage n shown in Fig. 6. For example, the inverter IN of the nth left stage L_Stage n shown in Fig. 6 can contain the first to fourth transistors T1 to T4. A first terminal and gate of the first transistor T1 can be connected to a terminal into which an nth left ripple clock L_DCLK(n) is input, and a second terminal of this can be connected to a first terminal of the second transistor T2. The first terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1, one gate of it can be connected to an nth left Q-node L_Qn, and a second terminal of it can be connected to a terminal to which the low voltage GVSS is supplied. A first terminal of the third transistor T3 can be connected to the terminal into which the nth left ripple clock L_DCLK(n) is input, a second terminal of it can be connected to a first terminal of the fourth transistor T4, and a gate of it can be connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2. The first terminal of the fourth transistor T4 can be connected to the second terminal of the third transistor T3, one gate of it can be connected to the nth left Q node L_Qn, and a second terminal of it can be connected to the terminal to which the low voltage GVSS is supplied. The inverter IN of the nth left stage L_Stage n can be implemented in different types in addition to the structure described above. A first terminal and a gate of a start transistor Tst of the nth left stage L_Stage n can be supplied with an n-1th left gate signal L_GS(n-1), which is output by a preceding stage (for example the n-1th left stage L_Stage n-1). An n+1-th left gate signal L_GS(n+1) output by a subsequent stage (for example, the n+1-th left stage L_Stage n+1) can be input into a gate of a reset transistor Trs of the n-th left stage L_Stage n. A structure and feature of each of the other elements of the nth left stage L_Stage n, except for the differences described above, may be the same as a structure and feature of the nth left stage described above with reference to Fig. 5, and therefore exact descriptions of them have been omitted. Secondly, the n-1th to n+1th right stages R_Stage n-1 to R_Stage n+1 shown in Fig. 6 can be implemented as the same type. Therefore, a structure of the nth right stage R_Stage n is described below. In comparison to the nth right stage shown in Fig. 5, the structure of an inverter IN shown in Fig. 6 is presented in detail. For example, the inverter IN of the nth right stage R_Stage n shown in Fig. 6 can contain the first to fourth transistors T1 to T4. A first terminal and gate of the first transistor T1 can be connected to a terminal into which an nth right ripple clock R_DCLK(n) is input, and a second terminal of this can be connected to a first terminal of the second transistor T2. The first terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1, one gate of it can be connected to an nth right Q-node R_Qn, and a second terminal of it can be connected to a terminal to which the low voltage GVSS is supplied. A first terminal of the third transistor T3 can be connected to the terminal into which the nth right ripple clock R_DCLK(n) is input, a second terminal of this can be connected to a first terminal of the fourth transistor T4, and a gate of this can be connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2. The first terminal of the fourth transistor T4 can be connected to the second terminal of the third transistor T3, one gate of it can be connected to the nth right Q node R_Qn, and a second terminal of it can be connected to the terminal to which the low voltage GVSS is supplied. The inverter IN of the nth right stage R_Stage n can be implemented in different types in addition to a structure described above. In this case, an arrangement structure of the first to fourth transistors T1 to T4, which are contained in the inverter IN of the nth right stage R_Stage n, can be the same as an arrangement structure of the first to fourth transistors T1 to T4, which are contained in the inverter IN of the nth left stage L_Stage n. A first terminal and a gate of a start transistor Tst of the nth right stage R_Stage n can be supplied with an n-1th right gate signal R_GS(n-1), which is output by a preceding stage (for example the n-1th right stage R_Stage n-1). An n+1-th right gate signal R_GS(n+1) output by a subsequent stage (for example, the n+1-th right stage R_Stage n+1) can be input into a gate of a reset transistor Trs of the n-th right stage R_Stage n. A structure and feature of each of the other elements of the nth right stage R_Stage n, except for the differences described above, may be the same as a structure and feature of the nth right stage described above with reference to Fig. 5, and therefore exact descriptions of them have been omitted. Below, a control method for a display device of an embodiment of the present invention is described with reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 to Fig. 8. Fig. 7 is a diagram showing waveforms applied to a display device of an embodiment of the present invention, and Fig. 8 is a diagram illustrating a method for outputting a gate-off signal in a display device of an embodiment of the present invention. The present invention is described below with reference to an nth left stage L_Stage n and an nth right stage R_Stage n. In the following description, descriptions that are identical or similar to those given above with reference to Figs. 1, 2, 3, 4, 5 to 6 are omitted or given briefly. Initially, in a first process A, an n-1th gate signal GSn-1 with a high level can be input as a start signal for both the nth left stage L_Stage n and the nth right stage R_Stage n. Therefore, an nth left Q-node L_Qn and an nth right Q-node R_Qn can be loaded. In a second process B, an nth left-gate clock L_SCCLK(n) and an nth right-gate clock R_SCCLK(n) can have a high level. For example, the phase of the nth left-gate clock L_SCCLK(n) can be the same as that of the nth right-gate clock R_SCCLK(n). Therefore, in Fig. 7, the nth left-gate clock L_SCCLK(n) and the nth right-gate clock R_SCCLK(n) are represented as a single nth-gate clock SCCLK(n). If it is not necessary in the following description to distinguish the nth left-gate clock L_SCCLK(n) from the nth right-gate clock R_SCCLK(n), the nth-gate clock SCCLK(n) can be used. Therefore, the level of the nth left Q node L_Qn and the nth left gate clock L_SCCLK(n) can be increased, and thus the nth left pull-up transistor L_Tun can be switched on. Accordingly, an nth gate pulse GPn can be output to the nth gate line GLn via the nth left pull-up transistor L_Tun. In this case, the nth gate pulse GPn can be output from the nth right stage R_Stage n based on the same procedure. Then, in a third process C, an n+1th gate signal GSn+1 with a high level can be applied as a reset signal to both the nth left stage L_Stage n and the nth right stage R_Stage n. Accordingly, the nth left pull-up transistor L_Tun can be switched off. In this case, the nth right pull-up transistor R_Tun can also be switched off. Then, in the third process C, an n+1-th right ripple clock R_DCLK(n+1) with a high level can be input from an n+1-th right stage R_Stage n+1 into an n-th right Qb node R_Qbn. Accordingly, an n_1-th right gate off signal R_Goffn_1st can be output from the n-th right stage R_Stage n to the n-th gate line GLn. The n_1-th right gate off signal R_Goffn_1st can configure an n-th right gate off signal R_Goffn. Since in this case the nth left ripple clock L_DCLK(n) is input at a low level into the nth right stage R_Stage n, it may not be possible to output a gate-off signal from the nth right stage R_Stage n. Then, in a fourth process D, the nth left ripple clock L_DCLK(n) can be input at a high level into an nth left Qb node L_Qbn. Accordingly, an n_2th left gate off signal L_Goffn_2st can be output from the nth left stage L_Stage n to the nth gate line GLn. The n_2th left gate off signal L_Goffn_2nd can configure an nth left gate off signal L_Goffn. In this case, a low level can be continuously supplied to an nth left Q-node L_Qn. The nth left gate clock L_SCCLK(n), which has a high level, can be applied to the first terminal of the nth left pull-up transistor L_Tun. Consequently, ripple can occur in the nth left Q node due to the high level of the nth left gate clock L_SCCLK(n). Since in this case the nth left ripple clock L_DCLK(n) is fed to the nth left Qb node L_Qbn at a high level, the nth left ripple transistor L_Trpn can be switched on. Accordingly, the ripple occurring in the nth left Q node L_Qn can be shunted via the nth left ripple transistor L_Trpn to a terminal to which the low voltage GVSS is supplied. In this case, the right nth ripple transistor R_Trpn can be driven using the same method as the nth left ripple transistor L_Trpn. Accordingly, the ripple occurring in the nth right Q node R_Qn can be routed via the nth right ripple transistor R_Trpn to a terminal supplied with the low voltage GVSS. Since, for example, the phase of the nth left ripple clock L_DCLK(n) is equal to that of the nth right ripple clock R_DCLK(n) and the phase of the nth left gate clock L_SCCLK(n) is equal to that of the nth right gate clock R_SCCLK(n), as described above, the same operation can be performed by the nth left stage L_Stage n and the nth right stage R_Stage n. Then, in a fifth process E, the n+1-th right ripple clock R_DCLK(n+1) can be input at a high level from the n+1-th right stage R_Stage n+1 into the n-th right Qb node R_Qbn. Therefore, an n_3 right gate off signal R_Goffn_3rd can be output from the nth right stage R_Stage n to the nth gate line GLn. The n_3 right gate off signal R_Goffn_3rd can configure the nth right gate off signal R_Goffn. Finally, in a sixth process F, the nth left ripple clock L_DCLK(n) can be input at a high level into the nth left Qb node L_Qbn. Therefore, an n_4th left gate off signal L_Goffn_4th can be output from the nth left stage L_Stage n to the nth gate line GLn. The n_4th left gate off signal L_Goffn_4th can configure the nth left gate off signal L_Goffn. In this case, a low level can be applied to the nth left Q node L_Qn. However, the nth left gate clock L_SCCLK(n), which has a high level, can be applied to the first terminal of the nth left pull-up transistor L_Tun. Consequently, ripple can occur in the nth left Q node because the nth left gate clock L_SCCLK(n) has a high level. Since in this case the nth left ripple clock L_DCLK(n) is fed to the nth left Qb node L_Qbn at a high level, the nth left ripple transistor L_Trpn can be switched on. Therefore, the ripple occurring in the nth left Q node L_Qn can be shunted via the nth left ripple transistor L_Trpn to a terminal to which the low voltage GVSS is supplied. In this case, the right nth ripple transistor R_Trpn can be driven using the same method as the nth left ripple transistor L_Trpn. Accordingly, the ripple occurring in the nth right Q node R_Qn can be routed via the nth right ripple transistor R_Trpn to a terminal supplied with the low voltage GVSS. The third to sixth processes C to F can be repeated until another nth gate pulse is output by the nth left stage L_Stage n and the nth right stage R_Stage n, and thus the nth gate off signal can be continuously output to the nth gate line GLn. For example, the processes described above can output nth gate pulses GPn from the nth left stage L_Stage n and the nth right stage R_Stage n to the nth gate line GLn. Furthermore, as shown in Fig. 8, the n_1-th right gate off signal R_Goffn_1st and the n_3-th right gate off signal R_Goffn_3rd can be output from the n-th right stage R_Stage n to the n-th gate line GLn, and the n_2-th left gate off signal L_Goffn_2nd and the n_4-th left gate off signal L_Goffn_4th can be output from the n-th left stage L_Stage n to the n-th gate line GLn. In this case, the n_1-th right gate off signal R_Goffn_1st, the n_3-th right gate off signal R_Goffn_3rd, the n_2-th left gate off signal L_Goffn_2nd and the n_4-th left gate off signal L_Goffn_4th can configure the n-th gate off signal Goffn, which is fed to the n-th gate line GLn. In this case, for the sake of simplicity, Fig. 8 shows the n_1th right gate off signal R_Goffn_1st, the n_3th right gate off signal R_Goffn_3rd, the n_2th left gate off signal L_Goffn_2nd, and the n_4th left gate off signal L_Goffn_4th represented as a high-level pulse waveform. However, in the embodiment described above, the n_1th right gate off signal R_Goffn_1st, the n_3th right gate off signal R_Goffn_3rd, the n_2th left gate off signal L_Goffn_2nd, and the n_4th left gate off signal L_Goffn_4th can essentially be continuous, low-level signals. For example, the nth left stage L_Stage n and the nth right stage R_Stage n can successively output the nth gate-off signal Goffn to the nth gate line GLn. Similarly, the nth gate-off signal Goffn can be continuously output to the nth gate line GLn. In the present disclosure, the outputs of the nth left gate pulse L_GPn and the nth right gate pulse R_GPn can be controlled by the Q-nodes contained in the nth left stage L_Stage n and the nth right stage R_Stage n. In this case, the nth left ripple transistor L_Trpn, which is provided in the nth left stage L_Stage n to remove the ripple occurring in the nth left Q node L_Qn of the nth left stage L_Stage n, and the nth right ripple transistor R_Trpn, which is provided in the nth right stage R_Stage n to remove the ripple occurring in the nth right Q node R_Qn of the nth right stage R_Stage n, can simultaneously and continuously perform a turn-on operation and a turn-off operation. Since both the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn undergo a turn-on and a turn-off cycle repeatedly, the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn cannot be attenuated, and the rate at which the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn are attenuated can be reduced. Accordingly, the reliability of the indicator device of the present disclosure, which includes the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn, can be improved. The following describes features of the present disclosure. Firstly, in the present disclosure, a phase of the nth left gate clock L_SCCLK(n) supplied to the nth left stage L_Stage n to generate the nth left gate pulse L_GPn can be equal to that of the nth left ripple clock L_DCLK(n) supplied to drive the nth left ripple transistor L_Trpn, and a phase of the nth right gate clock R_SCCLK(n) supplied to the nth right stage R_Stage n to generate the nth right gate pulse R_GPn can be equal to that of the nth right ripple clock R_DCLK(n) supplied to drive the nth right ripple transistor R_Trpn. For example, the nth left ripple transistor L_Trpn can be turned on by the nth left gate clock L_SCCLK(n), which is high only when a ripple occurs in the nth left Q node L_Qn, and the nth right ripple transistor R_Trpn can be turned on by the nth right gate clock R_SCCLK(n), which is high only when a ripple occurs in the nth right Q node R_Qn. Accordingly, as described above, the rate at which the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn are attenuated can be reduced. Secondly, one phase of the nth left ripple clock L_DCLK(n), which is supplied to drive the nth left ripple transistor L_Trpn, can be equal to that of the nth right ripple clock R_DCLK(n), which is supplied to drive the nth right ripple transistor R_Trpn. For example, the nth left ripple clock L_DCLK(n) can be fed to a gate of the nth left ripple transistor L_Trpn, the nth right ripple clock R_DCLK(n) can be fed to a gate of the nth right ripple transistor R_Trpn, and a phase of the nth left ripple clock L_DCLK(n) can be the same as that of the nth right ripple transistor R_Trpn. Therefore, the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn can simultaneously perform a turn-on operation and a turn-off operation. Thirdly, when the nth left ripple transistor L_Trpn is switched on, the nth left gate off signal L_Goffn can be output from the nth left stage L_Stage n to the nth gate line GLn, and when the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn are switched off, the nth right gate off signal R_Goffn can be output from the nth right stage R_Stage n to the nth gate line GLn. For example, the nth left gate off signal L_Goffn, which is output by the nth left stage L_Stage n, and the nth right gate off signal R_Goffn, which is output by the nth right stage R_Stage n, can be alternately output to the nth gate line GLn. To provide an additional description, in the present invention, since a gate-off signal is alternately output by two stages provided on either side of a gate line, the gate-off signal can be continuously supplied to the gate line. Therefore, the gate line cannot be floating, so that the switching transistors connected to the gate line cannot be driven anomalously. Accordingly, the reliability of a display device can be increased. Fig. 9 is another diagram that accurately represents a structure of each of the stages shown in Fig. 4. A basic structure of each of the n-1 to n+1 left stages L_Stage n-1 to L_Stage n+1 and the n-1 to n+1 right stages R_Stage n-1 to R_Stage n+1 shown in Fig. 9 may be the same as a basic structure of both the nth left stage L_Stage n and the nth right stage R_Stage n described above with reference to Fig. 5. Therefore, descriptions that are the same as or similar to those given above with reference to Figs. 5 and 6 are omitted or given briefly below, and in particular, the features of the stages shown in Fig. 9 are briefly described. In Fig. 9, n may be a natural number less than or equal to g / 2 and may be an even number. Firstly, a structure of an nth left signal generator 210a of the nth left stage L_Stage n shown in Fig. 9 can be the same as that of the nth left signal generator 210a of the nth left stage L_Stage n shown in Fig. 6. Secondly, the nth left signal output unit 220a shown in Fig. 6 can only contain the nth left pull-up transistor L_Tun. However, an nth left signal output unit 220a shown in Fig. 9 can contain an nth left pull-up transistor L_Tun and an n_2th left pull-up transistor L_Tun_2. In describing the nth left signal output unit 220a shown in Fig. 9, the nth left pull-up transistor L_Tun can be referred to as an n_1th left pull-up transistor L_Tun_1. For example, a gate of the n_tth left pull-up transistor L_Tun_1 shown in Fig. 9 can be connected to an nth left Q node. A gate of the n_2th left pull-up transistor L_Tun_2 can also be connected to the nth left Q node. Thirdly, the nth left signal output unit 220a shown in Fig. 6 can only contain the nth left pull-down transistor L_Tdn. The nth left signal output unit 220a shown in Fig. 9 can, however, contain an nth left pull-down transistor L_Tdn and an n_2th left pull-down transistor L_Tdn_2. The n_2th left pull-down transistor L_Tdn_2 can be connected to the nth left pull-up transistor L_Tun. In describing the nth left signal output unit 220a shown in Fig. 9, the nth left pull-down transistor L_Tdn can be referred to as the n_1th left pull-down transistor L_Tdn_1. For example, a gate of the n_tth left pull-down transistor L_Tdn_1 shown in Fig. 9 can be connected to an nth left Qb node L_Qbn. A gate of the n_2th left pull-down transistor L_Tdn_2 can also be connected to the nth left Qb node L_Qbn. Therefore, the gate of the n_2th left pull-down transistor L_Tdn_2 can also be connected to a gate of an nth left ripple transistor L_Trpn. Fourthly, a structure of an nth right signal generator 210b of the nth right stage R_Stage n shown in Fig. 9 can be the same as that of the nth right signal generator 210b of the nth right stage R_Stage n shown in Fig. 6. Fifthly, the nth right signal output unit 220b shown in Fig. 6 can only contain the nth right pull-up transistor R_Tun. However, the nth right signal output unit 220b shown in Fig. 9 can contain an nth right pull-up transistor R_Tun and an n_2th right pull-up transistor R_Tun_2. In describing the nth right-hand signal output unit 220b shown in Fig. 9, the nth right-hand pull-up transistor R_Tun can be referred to as an n_1-th right-hand pull-up transistor R_Tun_1. For example, a gate of the n_t-th right-hand pull-up transistor R_Tun_1 shown in Fig. 9 can be connected to an nth right-hand Q node R_Qn. A gate of the n_2-th right pull-up transistor R_Tun_2 can also be connected to the n-th right Q-node R_Qn. Sixth, the nth right signal output unit 220b shown in Fig. 6 can only contain the nth right pull-down transistor R_Tdn. The nth right-hand signal output unit 220b shown in Fig. 9 can, however, contain an nth right-hand pull-down transistor R_Tdn and an n_2th right-hand pull-down transistor R_Tdn_2. The n_2th right-hand pull-down transistor R_Tdn_2 can be connected to the n_2th right-hand pull-up transistor R_Tun_2. In describing the nth right-hand signal output unit 220b shown in Fig. 9, the nth right-hand pull-down transistor R_Tdn can be referred to as the n_1th right-hand pull-down transistor R_Tdn_1. In this case, a gate of the n_1th right-hand pull-down transistor R_Tdn_1 shown in Fig. 9 can be connected to a gate of an n+1th right-hand ripple transistor R_Trpn+1, which is contained in an n+1th stage. A gate of the n_2-th right pull-down transistor R_Tdn_2 can be connected to a gate of an n-1-th right ripple transistor R_Trpn-1, which is contained in an n-1-th right stage R_Stage n-1. For example, the nth left stage L_Stage n and nth right stage R_Stage n shown in Fig. 9 can be connected to two gate lines GL2n-1 and GL2n and can output a gate pulse and a gate off signal to each of the two gate lines GL2n-1 and GL2n. Below, a control method for a display device of an embodiment of the present invention, which includes the stages shown in Fig. 9, is described with reference to Fig. 9 and Fig. 10. Fig. 10 is a diagram showing waveforms applied to the stages illustrated in Fig. 9. The present invention is described below with reference to an nth left stage L_Stage n and an nth right stage R_Stage n. In the following description, descriptions that are identical or similar to those given above with reference to Figs. 1, 2, 3, 4, 5, 6, 7, 8 to 9 are omitted or given briefly. Firstly, in a first process H, an n-1th gate signal GSn-1 with a high level can be input as a start signal for both the nth left stage L_Stage n and the nth right stage R_Stage n. Therefore, an nth left Q-node L_Qn and an nth right Q-node R_Qn can be loaded. In a second process I, an nth left-gate clock L_SCCLK(n) and an n+1th left-gate clock L_SCCLK(n+1) can be sequentially shifted to a high level, and an nth right-gate clock R_SCCLK(n) and an n+1th right-gate clock R_SCCLK(n+1) can be sequentially shifted to a high level. For example, the phase of the nth left-gate clock L_SCCLK(n) can be equal to that of the nth right-gate clock R_SCCLK(n), and the phase of the n+1th left-gate clock L_SCCLK(n+1) can be equal to that of the n+1th right-gate clock R_SCCLK(n+1). Therefore, in Fig. 9, the nth left gate clock L_SCCLK(n) and the nth right gate clock R_SCCLK(n) are represented as the nth gate clock SCCLK(n), and the n+1th left gate clock L_SCCLK(n+1) and the n+1th right gate clock R_SCCLK(n+1) are represented as the n+1th gate clock SCCLK(n+1).In the following description, if it is not necessary to distinguish the nth left gate clock L_SCCLK(n) from the nth right gate clock R_SCCLK(n), the nth gate clock SCCLK(n) can be used, and if it is not necessary to distinguish the n+1th left gate clock L_SCCLK(n+1) from the n+1th right gate clock R_SCCLK(n+1), the n+1th gate clock SCCLK(n+1) can be used. Therefore, a level of the nth left Q node L_Qn can be increased together with the nth left gate clock L_SCCLK(n) and the n+1th left gate clock L_SCCLK(n+1), and thus the n_1th left pull-up transistor L_Tun_1 and the n_2th left pull-up transistor L_Tun_2 can be turned on. Accordingly, a 2n-1 gate pulse GP2n-1 and a 2n-1 gate pulse GP2n can be output successively via the nth left pull-up transistor L_Tun to the 2n-1 gate line GL2n-1 and the 2n-1 gate line GL2n. In this case, the 2n-1th gate pulse GP2n-1 and the 2n-th gate pulse GP2n can be output from the nth right stage R_Stage n based on the same procedure. Then, in a third process J, an n+1th gate signal GSn+1 with a high level can be input as a reset signal into both the nth left stage L_Stage n and the nth right stage R_Stage n. Accordingly, the n_1th left pull-up transistor L_Tun_1 and the n_2th left pull-up transistor L_Tun_2 can be switched off. In this case, the n_1-th right pull-up transistor R_Tun_1 and the n_2-th right pull-up transistor R_Tun_2 can also be switched off. Then, in the third process J, an n+1-th right ripple clock R_DCLK(n+1) with a high level can be input from an n+1-th right stage R_Stage n+1 into an n-th right Qb node R_Qbn. Therefore, a 2n-1_1-th right gate off signal R_Goff2n-1_1st can be output from the n-th right stage R_Stage n to a 2n-1-th gate line GL2n-1. The 2n-1_1-th right gate off signal R_Goff2n-1_1st can configure a 2n-1-th right gate off signal. In this case, an n-1th right ripple clock R_DCLK(n-1) at a high level can be input from the n-1th right stage R_Stage n-1 into an n-2th right Qb node R_Qbn_2. Therefore, a 2n-1th right gate off signal R_Goff2n_1st can be output from the nth right stage R_Stage n to the 2nth gate line GL2n. The 2n-1th right gate off signal R_Goff2n_1st can configure a 2nth right gate off signal. Since in this case the nth left ripple clock L_DCLK(n) is supplied to the nth left stage R_Stage n at a low level, it may not be possible to output a gate-off signal from the nth left stage R_Stage n. Then, in a fourth process K, the nth left ripple clock L_DCLK(n) can be input at a high level into the nth left Qb node L_Qbn. Therefore, a 2n-1_2th left gate off signal L_Goff2n-1_2nd can be output from the nth left stage R_Stage n to the 2n-1th gate line GL2n-1. The 2n-1_2th left gate off signal L_Goff2n-1_2nd can configure a 2n-1th left gate off signal. In this case, a 2n_2-th left gate off signal L_Goff2n_2nd can be output from the nth left stage R_Stage n to the 2n-th gate line GL2n. The 2n_2-th left gate off signal L_Goff2n_2nd can configure a 2n-th left gate off signal. In this case, a low level can be continuously applied to the nth left Q node L_Qn. However, the nth left gate clock L_SCCLK(n) and the n+1th left gate clock L_SCCLK(n+1), each with a high level, can be successively applied to the first terminal of the n_1th left pull-up transistor L_Tun_1 and the n_2th left pull-up transistor L_Tun_2, respectively. Consequently, because the nth left gate clock L_SCCLK(n) and the n+1th left gate clock L_SCCLK(n+1) each have a high level, ripple can occur at the nth left Q node L_Qn. Since in this case the nth left ripple clock L_DCLK(n) is fed to the nth left Qb node L_Qbn at a high level, the nth left ripple transistor L_Trpn can be switched on. Therefore, the ripple occurring in the nth left Q node L_Qn can be shunted via the nth left ripple transistor L_Trpn to a terminal to which the low voltage GVSS is supplied. In this case, the right nth ripple transistor R_Trpn can be driven using the same method as the nth left ripple transistor L_Trpn. Accordingly, the ripple occurring in the nth right Q node R_Qn can be routed via the nth right ripple transistor R_Trpn to a terminal supplied with the low voltage GVSS. Then, in a fifth process L, the n+1-th right ripple clock R_DCLK(n+1) can be input at a high level from the n+1-th right stage R_Stage n+1 into an n_1-th right Qb node R_Qbn_1. Therefore, a 2n-1_3-th right gate off signal R_Goff2n-1_3rd can be output from the n-th right stage R_Stage n to the 2n-1-th gate line GL2n-1. The 2n-1_3-th right gate off signal R_Goff2n-1_3rd can configure a 2n-1-th right gate off signal. In this case, the n-1th right ripple clock R_DCLK(n-1) can be input at a high level from the n-1th right stage R_Stage n-1 to the n-2th right Qb node R_Qbn_2. Therefore, a 2n-3th right gate off signal R_Goff2n_3rd can be output from the n-th right stage R_Stage n to the 2n-th gate line GL2n. The 2n-3th right gate off signal R_Goff2n_3rd can configure a 2n-th right gate off signal. Finally, in a sixth process M, the nth left ripple clock L_DCLK(n) can be input at a high level into the nth left Qb node L_Qbn. Therefore, a 2n-1_4th left gate off signal L_Goff2n-1_4th can be output from the nth left stage L_Stage n to the 2n-1th gate line GL2n-1. The 2n-1_4th left gate off signal L_Goff2n-1_4th can configure a 2n-1th gate off signal. Furthermore, a 2n_4th left gate off signal L_Goff2n_4th can be output from the nth left stage to the 2nth gate line GL2n. The 2n_4th left gate off signal L_Goff2n_4th can configure a 2nth left gate off signal. In this case, a low level can be continuously applied to the nth left Q node L_Qn. However, the nth left gate clock L_SCCLK(n) with a high level can be applied to a first terminal of the n_1th left pull-up transistor L_Tun_1, and the n+1th left gate clock L_SCCLK(n+1) with a high level can be applied to a first terminal of the n_2th left pull-up transistor L_Tun_2. Consequently, because the nth left gate clock L_SCCLK(n) and the n+1th left gate clock L_SCCLK(n+1) each have a high level, ripple can occur at the nth left Q node L_Qn. Since in this case the nth left ripple clock L_DCLK(n) is fed to the nth left Qb node L_Qbn at a high level, the nth left ripple transistor L_Trpn can be switched on. Therefore, the ripple occurring in the nth left Q node L_Qn can be shunted via the nth left ripple transistor L_Trpn to a terminal to which the low voltage GVSS is supplied. In this case, the right nth ripple transistor R_Trpn can be driven using the same method as the nth left ripple transistor L_Trpn. Accordingly, the ripple occurring in the nth right Q node R_Qn can be routed via the nth right ripple transistor R_Trpn to a terminal supplied with the low voltage GVSS. The third to sixth processes J to M can be repeated until another nth gate pulse is output from the nth left stage L_Stage n and the nth right stage R_Stage n, and thus the 2n-1th gate off signal can be continuously output to the 2n-1th gate line GL2n-1, and the 2nth gate off signal can be continuously output to the 2nth gate line GL2n. In this case, the 2n-1_1-th right gate off signal R_Goff2n-1_1st, the 2n-1_3-th right gate off signal R_Goff2n-1_3rd, the 2n-1_2-th left gate off signal L_Goff2n-1_2nd and the 2n-1_4-th left gate off signal L_Goff2n-1_4th can configure a 2n-1-th gate off signal that is fed to the 2n-1-th gate line. For example, the nth left stage L_Stage n and the nth right stage R_Stage n can successively output the n-1th gate-off signal to the 2n-1th gate line GL2n-1. Similarly, the 2n-1th gate-off signal can be continuously output to the 2n-1th gate line GL2n-1. In this case, the 2n_1-th right gate off signal R_Goff2n_1st, the 2n_3-th right gate off signal R_Goff2n_3rd, the 2n_2-th left gate off signal L_Goff2n_2nd and the 2n_4-th left gate off signal L_Goff2n_4th can configure a 2n-th gate off signal that is fed to the 2n-th gate line. For example, the nth left stage L_Stage n and the nth right stage R_Stage n can successively output the 2nth gate-off signal to the 2nth gate line GL2n. Similarly, the 2nth gate-off signal can be continuously output to the 2nth gate line GL2n. In this case, the nth left ripple transistor L_Trpn, which is provided in the nth left stage L_Stage n to remove the ripple occurring in the nth left Q node L_Qn of the nth left stage L_Stage n, and the nth right ripple transistor R_Trpn, which is provided in the nth right stage R_Stage n to remove the ripple occurring in the nth right Q node R_Qn of the nth right stage R_Stage n, can simultaneously and continuously perform a turn-on operation and a turn-off operation. Since both the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn repeat a turn-on and a turn-off cycle, the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn cannot be attenuated, and the rate at which the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn are attenuated can be reduced. Accordingly, the reliability of the indicator device of the present invention, which contains the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn, can be improved. According to the present invention, a ripple transistor can repeat a turn-on and a turn-off process based on a ripple clock to remove the ripple occurring in a Q node. Accordingly, degradation of the ripple transistor can be prevented, and thus the reliability of a display device can be improved. According to the present disclosure, the phase of a gate clock applied to a pull-up transistor connected to the Q node can be the same as that of a ripple clock used to drive the ripple transistor. Therefore, even when the gate clock is applied to the pull-up transistor, no anomalous signal caused by the ripple can be applied to the Q node. Consequently, the pull-up transistor connected to the Q node cannot operate anomalously, thus improving the reliability of a display device. According to the present invention, since a gate-off signal is alternately output by two stages provided on both sides of a gate line, the gate-off signal can be continuously supplied to the gate line. Therefore, the gate line cannot be floating, so that the switching transistors connected to the gate line cannot be driven anomalously. Consequently, the reliability of a display device can be increased. The features, structures and effects of the present invention described above are included in at least one embodiment of the present invention, but are not limited to only one embodiment. It will be obvious to those skilled in the art that various modifications and variations of the present invention can be made without departing from the scope of protection of the disclosures. It is therefore intended that the present disclosure covers the modifications and variations of this disclosure, provided they fall within the scope of protection of the appended claims and their equivalents.

Claims

Display device comprising: a display panel (100) comprising a display area (120) and a non-display area (130) adjacent to the display area (120) and containing gate lines (GL); a left gate drive (200a) provided in a first non-display area (131) of the non-display area (130) to output left gate pulses (L_GP) and left gate off signals (L_Goff) to the gate lines (GL); and a right gate drive (200b) provided in a second non-display area (132) of the non-display area (130) to output right gate pulses (R_GP) and right gate off signals (R_Goff) to the gate lines (GL), wherein the left gate drive (200a) comprises an nth left stage (L_Stage n) that outputs an nth left gate pulse (L_GPn), and the right gate drive (200b) comprises an nth right stage (R_Stage n) that outputs an nth right gate pulse (R_GPn), where n is a natural number,wherein the nth left stage (L_Stage n) of the left gate drive (200a) comprises an nth left Q node and the nth right stage (R_Stage n) of the right gate drive (200b) comprises an nth right Q node, wherein an output of the nth left gate pulse (L_GPn) and the nth right gate pulse (R_GPn) is controlled by the nth left Q node and the nth right Q node, and wherein the nth left stage (L_Stage n) comprises an nth left ripple transistor (L_Trpn) for removing ripple occurring in the nth left Q node of the nth left stage and the nth right stage (R_Stage n) comprises an nth right ripple transistor (R_Trpn) to remove a ripple occurring in the nth right Q node of the nth right stage includes,wherein the nth left stage (L_Stage n) comprises a left signal generator (210a) and a left signal output unit (220a) and the nth right stage (R_Stage n) comprises a right signal generator (210b) and a right signal output unit (220b), and wherein a gate-off signal (Goff) is alternately output by the left stage and the right stage, which are provided on both sides of a gate line (GL), in order to continuously output the gate-off signal (Goff) to the gate line. Display device according to claim 1, wherein a gate-off signal (Goff) is alternately output by the left stage and the right stage, which are provided on both sides of a gate line (GL), in order to continuously output the gate-off signal (Goff) to the gate line. Display device according to claim 1 or 2, wherein the nth left signal output unit (220a) includes an nth left pull-up transistor (L_Tun) configured to output the nth left gate pulse (L_GPn) and an nth left pull-down transistor (L_Tdn) configured to output the nth left gate off signal (L_Goffn), and the nth right signal output unit (220b) includes an nth right pull-up transistor (R_Tun) configured to output the nth right gate pulse (R_GPn) and an nth right pull-down transistor (R_Tdn) configured to output the nth right gate off signal (R_Goffn). Display device according to one of the preceding claims, wherein the nth left stage (L_Stage n) is configured to receive an nth left gate clock (L_SCCLK(n)) to generate the nth left gate pulse (L_GP) and to receive an nth left ripple clock (L_DCLK(n)) to drive the nth left ripple transistor (L_Trpn), and the nth right stage (R_Stage n) is configured to receive an nth right gate clock (R_SCCLK(n)) to generate the nth right gate pulse (R_GP) and to receive an nth right ripple clock (R_DCLK(n)) to drive the nth right ripple transistor (R_Trpn). Display device according to claim 4, wherein a phase of the nth left gate clock (L_SCCLK(n)) is equal to a phase of an nth left ripple clock (L_DCLK(n)), and a phase of an nth right gate clock (R_SCCLK(n)) supplied to the nth right stage (R_Stage n) to generate the nth right gate pulse (R_GP) is equal to a phase of an nth right ripple clock (R_DCLK(n)) supplied to drive the nth right ripple transistor (R_Trpn), and / or a phase of an nth left ripple clock (L_DCLK(n)) supplied to drive the nth left ripple transistor (L_Trpn) is equal to a phase of an nth right ripple clock (R_DCLK(n)), which is supplied to drive the nth right ripple transistor (R_Trpn). Display device according to one of the preceding claims, wherein the first terminal of the nth left ripple transistor (L_Trpn) is connected to the nth left Q node L_Qn, a second terminal of the nth left ripple transistor (L_Trpn) is connected to a first voltage terminal (GVSS), and a gate of the nth left ripple transistor (L_Trpn) is connected to a gate of an nth left pull-down transistor (L_Tdn) controlling an output of an nth left gate off signal (L_Goffn), and a first terminal of the nth right ripple transistor (R_Trpn) is connected to the nth right Q node, a second terminal of the nth right ripple transistor (R_Trpn) is connected to the first voltage terminal (GVSS), and a gate of the nth right A ripple transistor (R_Trpn) is connected to a terminal to which an nth right ripple clock (R_DCLK(n)) is supplied. Display device according to claim 6, wherein a phase of an nth left gate clock (L_SCCLK(n)) supplied to the nth left stage to generate the nth left gate pulse is equal to a phase of an nth left ripple clock (L_DCLK(n)) supplied to drive the nth left ripple transistor (L_Trpn), and a phase of an nth right gate clock (R_SCCLK(n)) supplied to the nth right stage (R_Stage n) to generate the nth right gate pulse (R_GP) is equal to a phase of the nth right ripple clock (R_DCLK(n)) supplied to a gate of the nth right ripple transistor (R_Trpn). Display device according to one of the preceding claims, wherein an nth left ripple clock (L_DCLK(n)) is supplied to a gate of the nth left ripple transistor (L_Trpn), the nth right ripple clock (R_DCLK(n)) is supplied to a gate of the nth right ripple transistor (R_Trpn), and a phase of the nth left ripple clock (L_DCLK(n)) is equal to a phase of the nth right ripple clock (R_DCLK(n)). Display device according to one of the preceding claims, wherein a gate of the nth left ripple transistor (L_Trpn) is connected to a gate of an nth left pull-down transistor (L_Tdn) that controls an output of the nth left gate off signal (L_Goff), and a gate of the nth right ripple transistor (R_Trpn) is not connected to a gate of an nth right pull-down transistor (R_Tdn) that controls an output of an nth right gate off signal (R_Goff). Display device according to claim 9, wherein a gate of the nth right pull-down transistor (R_Tdn) is connected to a gate of a right ripple transistor (R_Tdn(n+1)) of a further right stage, preferably to a gate of an n+1th right ripple transistor (R_Tdn(n+1)) contained in an n+1th right stage. Display device according to one of the preceding claims, wherein when the nth left ripple transistor (L_Trpn) is switched on, an nth left gate off signal (L_Goff) is output from the nth left stage (L_Stage n) to an nth gate line (GLn), and when the nth right ripple transistor (R_Trpn) is switched off, an nth right gate off signal (R_Goff) is output from the nth right stage (R_Stage n) to the nth gate line (GL). Display device according to one of the preceding claims, wherein an nth left gate off signal (L_Goff) output by the nth left stage (L_Stage n) and an nth right gate off signal (R_Goff) output by the nth right stage (R_Stage n) are alternately output to the nth gate line (GLn). Display device according to one of the preceding claims, wherein the nth left gate off signal (L_Goff) and an nth right gate off signal (R_Goff) are controlled by an nth left Qb node contained in the nth left stage (L_Stage n) and an nth right Qb node contained in the nth right stage (R_Stage n), and / or a gate of the nth left ripple transistor (L_Trpn) and the nth left Qb node contained in the nth left stage (L_Stage n) are connected to each other, and the nth right Qb node contained in the nth right stage (R_Stage n) is connected to a gate of an n+1-th right ripple transistor (R_Trpn) contained in a The n+1-th right stage (R_Stage n+1) is contained and connected. Display device according to one of the preceding claims, wherein the nth left stage (L_Stage n) comprises an nth left signal generator (210a) containing the nth left ripple transistor (L_Trpn), and an nth left signal output unit (220a) configured to output an nth left gate off signal (L_Goff) and the nth left gate pulse (L_GP) based on an nth left control signal generated by the nth left signal generator (210a), and the nth right stage (R_Stage n) comprises an nth right signal generator (210b) containing the nth right ripple transistor (R_Trpn), and an nth right signal output unit (220b) configured to output an nth left gate off signal (L_Goff) and the nth left gate pulse (L_GP) based on an nth left control signal generated by the nth left signal generator (210b). The control signal to output an nth right gate off signal (R_Goff) and the nth right gate pulse (R_GP) includes,where preferably the nth left gate off signal (L_Goff) and the nth right gate off signal (R_Goff) are output alternately. Display device according to one of the preceding claims, wherein the nth left signal output unit (220a) comprises an nth left pull-up transistor (L_Tun) outputting the nth left gate pulse (L_GP), wherein a gate of the nth left pull-up transistor (L_Tun) is connected to the nth left Q node, and the nth right signal output unit (220b) comprises an nth right pull-up transistor (R_Tun) outputting the nth right gate pulse (R_GP), wherein a gate of the nth right pull-up transistor (R_Tun) is connected to the nth right Q node, and / or the nth left signal output unit (220a) comprises an nth left pull-down transistor (L_Tdn) outputting the nth left outputs gate-off signal (L_Goff), wherein a gate of the nth left pull-down transistor (L_Tdn) is connected to a gate of the nth left ripple transistor (L_Trpn), and the nth right signal output unit (220b) comprises an nth right pull-down transistor (R_Tdn),which outputs the nth right gate off signal (R_Goff), wherein a gate of the nth right pull-down transistor (R_Tdn) is connected to a gate of an n+1th right ripple transistor (R_Trpn-+1) contained in an n+1th right stage (R_Stage n+1). Display device according to one of the preceding claims, wherein the nth left signal output unit (220a) further comprises an n_2th left pull-up transistor (L_Tun), wherein a gate of the n_2th left pull-up transistor (L_Tun_2) is connected to the nth left Q node, wherein g is an even number and n is a natural number of g / 2, and the nth right signal output unit (220b) further comprises an n_2th right pull-up transistor (R_Tun_2), wherein a gate of the n_2th right pull-up transistor (R_Tun_2) is connected to the nth right Q node;and / or the nth left signal output unit (220a) further comprises an n_2th left pull-down transistor (L_Tdn_2) connected to the n_2th left pull-up transistor (L_Tun_2), a gate of the n_2th left pull-down transistor (L_Tdn_2) connected to a gate of the nth left ripple transistor (L_Trpn), the nth right signal output unit (200b) further comprises an n_2th right pull-down transistor (R_Tdn_2) connected to the n_2th right pull-up transistor (R_Tun_2), and a gate of the n_2th right pull-down transistor (R_Tdn_2) connected to a gate of an n_1th right ripple transistor (R_Trpn-1), which is contained in an n-1th right stage (R_Stage n-1).;

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