VERTICAL POWER SEMICONDUCTOR DEVICE WITH SOURCE OR EMITE PAD

Abstract

Vertical power semiconductor device (100) comprising: a SiC semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite the first surface (1031); a first wiring plane (104) above the first surface (1031), wherein the first wiring plane (104) consists of laterally spaced portions of a structured conductive layer or a structured conductive layer stack and has as a portion of the laterally spaced portions a first lower source or emitter pad (1041) and as a further portion of the laterally spaced portions a second lower source or emitter pad (1042);a second wiring level (106) above the first wiring level (104), wherein the second wiring level (106) consists of laterally spaced portions of a structured conductive layer or a structured conductive layer stack and has as part of the laterally spaced portions a gate pad (1061) and as another part of the laterally spaced portions a source or emitter pad (1062), wherein the source or emitter pad (1062) of the second wiring level (106) is electrically connected to the first lower source or emitter pad (1041) and to the second lower source or emitter pad (1042) of the first wiring level (104);and wherein the first wiring level (104) further comprises, as a further part of the laterally spaced parts, a gate line (1043) which is arranged laterally between the first lower source or emitter pad (1041) and the second lower source or emitter pad (1042), wherein the gate line (1043) is arranged vertically between the source or emitter pad (1062) of the second wiring level (106) and the first surface (1031) and the gate line (1043) is electrically insulated from the source or emitter pad (1062) of the second wiring level (106) by an interlayer dielectric structure (108).

Description

TECHNICAL AREA The present disclosure relates to a vertical power semiconductor device, in particular to a vertical power semiconductor device with a wiring plane that includes a source or emitter pad. BACKGROUND The technological development of new generations of vertical power semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), or junction / barrel field-effect transistors (JFETs), aims to improve electrical device characteristics and reduce costs by shrinking device geometries. For example, reference is made to the disclosure content in US 2022 / 0093761A1. Although costs can be reduced by shrinking device geometry, a variety of trade-offs and challenges must be addressed. For example, meeting reliability requirements necessitates design optimization, such as with respect to interconnects, when device functionalities per unit area are increased. Therefore, there is a need for an improved vertical power semiconductor device. SUMMARY The invention is defined in the independent claims. Further developments are the subject of the dependent claims. An example of the present disclosure relates to a vertical power semiconductor device. The vertical power semiconductor device comprises a SiC semiconductor body having a first surface and a second surface opposite the first surface. The vertical power semiconductor device further comprises a first wiring layer above the first surface. The first wiring layer includes a first lower source or emitter pad and a second lower source or emitter pad. The vertical power semiconductor device further comprises a second wiring layer above the first wiring layer. The second wiring layer includes a gate pad and a source or emitter pad.The source or emitter pad of the second wiring layer is electrically connected to the first lower source or emitter pad and to the second lower source or emitter pad of the first wiring layer. The first wiring layer also includes a gate line located laterally between the first lower source or emitter pad and the second lower source or emitter pad. The gate line is located vertically between the source or emitter pad of the second wiring layer and the first surface. The gate line is electrically isolated from the source or emitter pad of the second wiring layer by an interlayer dielectric structure. Another example from the present disclosure relates to a vertical power semiconductor device. The vertical power semiconductor device comprises a SiC semiconductor body having a first surface and a second surface opposite the first surface. The vertical power semiconductor device further comprises a first trench structure extending from the first surface into the SiC semiconductor body. The vertical power semiconductor device further comprises a plurality of second trench structures branching off from the first trench structure. The cross-sectional area of ​​the first trench structure is larger than the cross-sectional area of ​​each of the plurality of second trench structures. The vertical power semiconductor device further comprises a wiring plane above the first surface. The wiring plane includes a gate pad and a source or emitter pad. Another example from the present disclosure relates to a method for fabricating a vertical power semiconductor device. The method comprises forming a first wiring layer over a first surface of a SiC semiconductor body, which has the first surface and a second surface opposite the first surface. The first wiring layer includes a first lower source or emitter pad and a second lower source or emitter pad. The method further comprises forming a second wiring layer over the first wiring layer. The second wiring layer includes a gate pad and a source or emitter pad. The source or emitter pad of the second wiring layer is electrically connected to the first lower source or emitter pad and to the second lower source or emitter pad of the first wiring layer.The first wiring layer further includes a gate line located laterally between the first lower source or emitter pad and the second lower source or emitter pad. The gate line is arranged vertically between the source or emitter pad of the second wiring layer and the first surface. The gate line is electrically isolated from the source or emitter pad of the second wiring layer by an interlayer dielectric structure. Another example from the present disclosure relates to a method for fabricating a vertical power semiconductor device. The method comprises forming a first trench structure extending from a first surface into a SiC semiconductor body, the SiC semiconductor body having the first surface and a second surface opposite the first surface. The method further comprises forming a plurality of second trench structures branching off from the first trench structure, wherein a cross-sectional area of ​​the first trench structure is larger than a cross-sectional area of ​​each of the plurality of second trench structures. The method further comprises forming a wiring plane above the first surface, the wiring plane having a gate pad and a source or emitter pad. The expert will recognize additional features and advantages when reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are enclosed to provide a further understanding of the embodiments and are incorporated into and form part of this description. The drawings illustrate examples of vertical power semiconductor devices and, together with the description, serve to explain the principles of the examples. Further examples are described in the following detailed description and the claims. Figures 1, 2, and 3 are schematic cross-sectional views and examples of vertical power semiconductor devices for illustration, including a gate pad and a source or emitter pad. Figures 4A and 4B are a schematic cross-sectional view and a top view, respectively, to illustrate another example of a vertical power semiconductor device, including a first trench structure and a second trench structure branching off from the first trench structure.Figures 5A to 5F are schematic cross-sectional views to illustrate an example of the construction of the first trench structure and the second trench structures branching off from the first trench structure. DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific examples of vertical power semiconductor devices. It is understood that further examples may be used and structural or logical modifications made without departing from the scope of this disclosure. For example, features illustrated or described for one example may be used in conjunction with other examples to arrive at yet another example. It is intended that this disclosure includes such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of the attached claims. The drawings are not to scale and are for illustrative purposes only.Corresponding elements are designated with the same reference symbols in the various drawings, unless otherwise stated. The terms "have," "contain," "comprise," "exhibit," and the like are open terms, indicating the presence of the identified structures, elements, or features, but not excluding the presence of additional elements or features. Indefinite and definite articles should encompass both the plural and singular unless the context clearly indicates otherwise. The term "electrically connected" can describe a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" can include the possibility that one or more intermediate elements suitable for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. A resistive contact can be a non-rectifying electrical junction. For physical quantities, specified ranges include the boundary values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a boundary value such as "at most" and "at least". The terms "on" and "over" should not be interpreted as meaning only "directly on" and "directly over". Rather, if an element is positioned "on" or "over" another element (e.g., a layer is "on" or "over" another layer or "on" or "over" a substrate), another component (e.g., another layer) can be positioned between the two elements (e.g., another layer can be positioned between a layer and a substrate if the layer is "on" or "over" the substrate). An example of the present disclosure relates to a vertical power semiconductor device. The vertical power semiconductor device comprises a SiC semiconductor body having a first surface and a second surface opposite the first surface. The vertical power semiconductor device includes a first wiring layer above the first surface. The first wiring layer may have a first lower source or emitter pad and a second lower source or emitter pad. Furthermore, the vertical power semiconductor device includes a second wiring layer above the first wiring layer. The second wiring layer may have a gate pad and a source or emitter pad. The source or emitter pad of the second wiring layer may be electrically connected to the first lower source or emitter pad and to the second lower source or emitter pad of the first wiring layer.Furthermore, the first wiring layer can include a gate line located laterally between the first lower source or emitter pad and the second lower source or emitter pad. The gate line can also be located vertically between the source or emitter pad of the second wiring layer and the first surface. The gate line can be electrically isolated from the source or emitter pad of the second wiring layer by an interlayer dielectric structure. The vertical power semiconductor device can be, for example, part of an integrated circuit, a discrete semiconductor device, or a semiconductor module, or it can at least constitute one of these. The semiconductor device can be used in applications related to power or energy transmission and distribution, automotive and transportation technology, renewable energy, consumer electronics, and other industrial applications. The vertical power semiconductor device can be, for example, an insulated-gate field-effect transistor (IGFET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a junction field-effect transistor (JFET), or a thyristor, or it can contain such a component. The vertical power semiconductor device can have a load current flow between the first surface and the second surface opposite the first. For example, the first surface can be a front or top surface of the semiconductor body, and the second surface can be a rear or back surface of the semiconductor body. The semiconductor body can be mounted on a conductor frame, for example, via the second surface. Intermediate connections can be arranged on a contact pad structure of a wiring area above the first surface of the semiconductor body to electrically connect device elements within the SiC semiconductor body to elements, such as other semiconductor devices, outside the semiconductor device. The vertical power semiconductor device can be configured to conduct currents greater than 1 A, 10 A, 30 A, 50 A, 75 A, or even 100 A. Furthermore, the vertical power semiconductor device can be configured to block voltages between load terminals, such as between the collector and emitter of an IGBT or between the drain and source of a MOSFET or JFET, in the range of several hundred to several thousand volts, e.g., 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the power semiconductor device. The semiconductor body may contain or be composed of epitaxially deposited semiconductor material. Separately or in combination, the semiconductor body may include a growth substrate. For example, the vertical power semiconductor device may be based on a semiconductor body made of a crystalline SiC material. The semiconductor material may be, for example, 2H-SiC (SiC of the 2H polytype), 6H-SiC, 3C-SiC, or 15R-SiC. According to one example, the semiconductor material is silicon carbide of the 4H polytype (4H-SiC). The semiconductor body may consist of a semiconductor substrate or may include or be composed of a semiconductor substrate that has no, one, or more than one SiC layer, such as epitaxially grown SiC layers. To achieve a desired current handling capability, the vertical power semiconductor device can be configured with a multitude of parallel-connected transistor cells within a transistor cell region. For example, the parallel-connected transistor cells can be arranged in the form of a strip or a strip segment. The transistor cells can also have any other shape, such as circular, elliptical, or polygonal (e.g., hexagonal or octahedral). The transistor cells can be arranged within the transistor cell region of the SiC semiconductor body. The transistor cell region can be an active region in which a source region of a FET or JFET is located on the first surface and a drain region of the FET or JFET is arranged oppositely to each other along the vertical direction.Similarly, the transistor cell region can be an active region in which an emitter region of an IGBT is located on the first surface and a collector region of the IGBT is oriented oppositely to each other along the vertical direction. Within the transistor cell region, a load current can enter and exit the semiconductor body of the FET, JFET, IGBT, or thyristor, for example, via contact plugs on the first surface of the semiconductor body. The transistor cell region can, for instance, be defined by a region in which the lower source or emitter pads and the gate line(s) are located above the first surface of the SiC semiconductor body. An edge termination region can at least partially surround the transistor cell region and may contain a termination structure.In a blocking mode or a reverse-biased mode of the FET, JFET, or IGBT, the blocking voltage drops laterally between the transistor cell region and a field-free region across the termination structure in the edge termination region. The termination structure may have a higher or slightly lower voltage blocking capability than the transistor cell region. The termination structure may, for example, include a junction termination extension (JTE) with or without variation of lateral doping (VLD), one or more laterally separated guide rings, or any combination thereof. A wiring region above the first surface can comprise the first wiring layer and the second wiring layer. Each wiring layer can be formed by a single or a stack of conductive layers, such as metal layer(s), metal alloy layer(s), highly doped semiconductor layer(s), or any combination thereof. For example, the wiring layers can contain at least one of Cu, Au, AlCu, Ag, or alloys thereof. The wiring layers can be, for example, lithographically structured. The interlayer dielectric structure can be arranged between stacked wiring layers and / or between laterally spaced portions of each wiring layer. A contact plug (contact plug) or contact lead (contact leads) can be formed in openings in the interlayer dielectric structure to connect portions, such as...To electrically connect metal conductors or contact areas of different wiring configurations. For example, an interlayer dielectric of the interlayer dielectric structure can be arranged between the first surface of the SiC semiconductor body and the first and second lower source or emitter pads. A contact plug or contact line can also be formed in openings in the interlayer dielectric structure to electrically connect portions of a lowest wiring level (e.g., the wiring level closest to the first surface, such as the first wiring level) to the active region of the SiC semiconductor body, e.g., a doped source or emitter region. The first and second lower source or emitter pads can be part of the structured first wiring layer. In other words, the first and second lower source or emitter pads can be laterally separated by a portion of the interlayer dielectric structure. The gate line can be another part of the structured first wiring layer and can likewise be laterally separated from the lower source or emitter pads, for example, by a portion of the interlayer dielectric structure, such as a first passivation structure. The vertical power semiconductor device can incorporate a dual wiring level for the source or emitter pads. The first wiring level can distribute gate current between gate electrodes in the active region and the gate pad via the gate trace in the first wiring level, as well as distribute source or emitter current from the active region to the lower source or emitter pads. Because the source or emitter pad in the second wiring level is not interrupted by the gate trace, a larger surface area for interconnect technologies (e.g., sintering or soldering) can facilitate easier sintering on the source or emitter pad. This can also allow for an increase in maximum current densities compared to, for example, a wire-based interconnect scheme.Furthermore, the lower source or emitter pad can be extended with respect to the dual wiring level below the gate pad, allowing for an increase in the active area below the gate pad. For example, the first wiring layer can contain copper, and the second wiring layer can also contain copper. In some examples, the first wiring layer can consist predominantly of copper. Likewise, the second wiring layer can consist predominantly, i.e., more than 50% by volume, of copper. The copper in the first wiring layer can be formed, for example, by an electrochemical copper deposition (ECD) process. A copper seed layer can be formed, for example, prior to the ECD process. The copper seed layer can be formed, for example, as a sputtered or vapor-deposited copper seed layer. Additionally, or as an alternative, the copper in the first wiring layer can also be formed by a sputtering deposition process. The copper in the second wiring layer can also be formed, for example, by an electrochemical copper deposition (ECD) process.Prior to the ECD process, a copper seed layer can be formed, for example. Additionally or alternatively, the copper for the second wiring layer can also be formed using a sputtering deposition process. For example, the vertical power semiconductor device can further include a barrier layer positioned between the first wiring level and the second wiring level. The barrier layer can be, for example, a single layer or it can be configured as a stack of sublayers. For example, the barrier layer can be configured to act as a hard layer to protect the lower source or emitter pads from damage when bonding occurs on the top surface of the source or emitter pad of the second wiring level. For example, the barrier layer can be formed by a physical vapor deposition (PVD) process, such as a sputtering process. The barrier layer can, for example, contain a Ti-W alloy or a Cu-Ti alloy. The Ti-W alloy layer can have a thickness ranging from a few tens of nanometers to a few hundred nanometers. The Ti-W alloy layer can be configured to act as a hard layer to protect the wiring layers in the first wiring layer, such as the first and second source or emitter pads, from damage when bonding occurs on the top surface of the source or emitter pad of the second wiring layer. The Cu-Ti alloy can be formed by Ti or Cu deposition. Initiated by a curing process, the deposited Ti can then react with Cu to form hard Cu-Ti phases. The curing process can be performed after structuring the Cu, for example, by an etching process. The mechanical properties of the Cu-Ti alloy, e.g.,The hardness can be advantageous with respect to wire bonding on the top of the second wiring layer or with respect to the inclusion of fine-grained copper in the second wiring layer. This can enable an increase in the mechanical strength of copper in the second wiring layer. The barrier layer can, for example, provide a diffusion barrier against the solder chemistry. Solder chemistry is typically made from lead (Pb) and / or tin (Sn) elements. Sn tends to react or diffuse into copper and can consume the copper. Barrier layers are configured to separate the first copper-containing wiring layer from the second copper-containing wiring layer, thereby preventing Sn diffusion into the first copper-containing wiring layer and protecting it and the device from thermal runaway. Both Ti-Cu and TiW layers act as a diffusion barrier against Sn diffusion. For example, Al can be added as a solute in a second copper-containing wiring layer. The barrier layer can, for example, contain a stress compensation layer. The barrier layer can, for example, contain or consist of TiW. The first wiring layer can, for example, have a thickness in the range of 2 µm to 7 µm. The second wiring layer can have a thickness in the range of 10 µm to 20 µm. For example, the ratio of the thickness of the second wiring layer to the thickness of the first wiring layer can be in the range of 2 to 20. The thickness of the first and / or second wiring layer can be determined according to requirements such as transverse conductivity, gate leads, source / emitter or gate distributors / runners, mechanical robustness, and heat dissipation. The interlayer dielectric structure can contain a first passivation structure, for example, an imide, an oxide, or a nitride. The interlayer dielectric structure can laterally separate and electrically insulate parts of the first wiring layer (e.g., gate trace, gate or source / emitter runner, lower source or emitter pads). For example, the vertical power semiconductor device can further include a second passivation structure arranged on a portion of the first passivation structure. The second passivation structure can, for example, contain one or more layers of a dielectric material, such as an oxide or nitride, an imide, or an epoxy material. The second passivation structure can be formed after structuring the second wiring layer, for example, after etching the second wiring layer. The second passivation structure can laterally separate and electrically insulate portions of the second wiring layer (e.g., the gate pad and the source or emitter pad). The second passivation structure can also be formed, for example, over a portion of the gate pad and / or the source or emitter pad, such as an edge region of the gate pad and / or the source or emitter pad. The vertical power semiconductor device may further include, for example, a currentless plating structure on the gate pad and on the source or emitter pad. The currentless plating structure may, for example, be laterally adjacent to the second passivation structure of the interlayer dielectric structure. The currentless plating structure may, for example, comprise at least one NiMoP layer, or a NiP / Au, or a NiP / Pd / Au, or a NiP / Ag, or a NiMoP / Ag layer stack. The first wiring level can, for example, further include a lower gate pad arranged between the gate pad of the second wiring level and the first surface. The lower gate pad can be electrically connected to the gate pad of the second wiring level. The interlayer dielectric structure can, for example, be laterally adjacent to the lower gate pad. The interlayer dielectric structure can also be formed above the lower gate pad in a boundary region of the lower gate pad. Thus, a bottom surface of the gate pad can be formed on a top surface of the interlayer dielectric structure in the boundary region of the lower gate pad, as well as on a top surface of the lower gate pad itself. The first lower source or emitter pad can, for example, extend laterally beneath the gate pad of the second wiring level. The first lower source or emitter pad can be electrically isolated from the gate pad of the second wiring level by the interlayer dielectric structure. The interlayer dielectric structure can not only laterally isolate the first lower source or emitter pad, but can also extend over the first lower source or emitter pad, at least in an overlap region between the gate pad and the first source or emitter pad. An electrically active region can be present beneath the gate pad. For example, transistor cells in the SiC semiconductor device can be arranged directly beneath the gate pad. Another example in the present disclosure relates to a vertical power semiconductor device. Details regarding structure, function, technical benefits, or features described above in relation to the exemplary vertical power semiconductor devices, such as details relating to the SiC semiconductor body, the wiring plane, or the interlayer dielectric structure, apply equally to the examples described below. The vertical power semiconductor device comprises a SiC semiconductor body having a first surface and a second surface opposite the first surface. The vertical power semiconductor device may further comprise a first trench structure extending from the first surface into the SiC semiconductor body.The vertical power semiconductor device can further include a plurality of second trench structures branching off from the first trench structure. The cross-sectional area of ​​the first trench structure can be larger than the cross-sectional area of ​​any of the plurality of second trench structures. The vertical power semiconductor device can further include a wiring plane above the first surface. The wiring plane contains a gate pad and a source or emitter pad. For example, the vertical power semiconductor device can include a plurality of first trench structures. Second trench structures branching off from adjacent first trench structures can merge into each other. In other words, the plurality of first trench structures and the plurality of second trench structures can, for example, define a grid. The first trench structure can contain a gate line.By burying the gate trace below the first surface of the SiC semiconductor body, the source or emitter pad is not interrupted by the gate trace and is therefore comparatively larger, thus providing a larger surface area for interconnection technologies (e.g., sintering or soldering), which can facilitate easier sintering on the source or emitter pad. This can also allow for an increase in maximum current densities compared to, for example, a wire-based interconnection scheme. For example, the minimum lateral extent of the first trench structure may be greater than the minimum lateral extent of any of the multiple second trench structures. The minimum lateral extent may refer to a lateral direction perpendicular to a longitudinal direction of the respective trench structure. For example, the vertical extent of the first trench structure may be greater than the vertical extent of any of the multiple second trench structures. The first trench structure can, for example, contain a gate conduction material and a gate conduction dielectric located between the gate conduction material and the SiC semiconductor body. Each of the multiple second trench structures can contain a gate electrode material and a gate dielectric located between the gate electrode material and the SiC semiconductor body. The thickness of the gate conduction dielectric at a bottom face of the first trench structure can be greater than the thickness of the gate dielectric at a bottom face of each of the second trench structures. For example, the ratio of the thickness of the gate conduction dielectric at a bottom face of the first trench structure, e.g., 10 nm to 200 nm, to the thickness of the gate dielectric at a bottom face of each of the second trench structures can be in the range of 2 to 50. The first trench structure can extend laterally to a gate distributor or...The gate runner extends to at least partially surround a transistor cell region of the vertical power semiconductor device. The gate conductor material of the first trench structure can be electrically connected to the gate runner at a connection region. For example, in a top view, the connection region can be an overlap region between the first trench structure and the gate runner. For example, both the gate electrode material and the gate conductor material can contain doped polycrystalline silicon or a metal, e.g. tungsten (W). Details regarding structure, function, technical benefits, or characteristics described above in relation to a vertical power semiconductor device such as a FET, JFET, IGBT, or thyristor apply equally to the exemplary procedures described herein. Machining or processing of the SiC semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more of the examples described above or below. An example of the present disclosure relates to a method for fabricating a vertical power semiconductor device. The method comprises forming a first wiring layer over a first surface of a SiC semiconductor body, which has the first surface and a second surface opposite the first surface. The first wiring layer may include a first lower source or emitter pad and a second lower source or emitter pad. The method further comprises forming a second wiring layer over the first wiring layer. The second wiring layer may include a gate pad and a source or emitter pad. The source or emitter pad of the second wiring layer may be electrically connected to the first lower source or emitter pad and to the second lower source or emitter pad of the first wiring layer.Furthermore, the first wiring layer can include a gate line arranged laterally between the first lower source or emitter pad and the second lower source or emitter pad. The gate line can also be arranged vertically between the source or emitter pad of the second wiring layer and the first surface. The gate line can be electrically isolated from the source or emitter pad of the second wiring layer by an interlayer dielectric structure. Another example from the present disclosure relates to a further method for fabricating a vertical power semiconductor device. The method comprises forming a first trench structure extending from a first surface into a SiC semiconductor body. The SiC semiconductor body has the first surface and a second surface opposite the first surface. The method further comprises forming a plurality of second trench structures branching off from the first trench structure. A cross-sectional area of ​​the first trench structure may be larger than a cross-sectional area of ​​any of the plurality of second trench structures. The method further comprises forming a wiring plane above the first surface. The wiring plane may include a gate pad and a source or emitter pad. The description and drawings merely illustrate the principles of revelation. Furthermore, all examples cited herein are expressly intended primarily for illustrative purposes, to aid the reader in understanding the principles of revelation and the concepts contributed by the inventor(s) to advance the state of the art. All statements herein that present principles, aspects, and examples of revelation, as well as specific examples thereof, are intended to include their equivalents. It is understood that the disclosure of multiple actions, processes, operations, steps, or functions in the description or claims cannot be interpreted as meaning that they occur or are present in a specific sequence, unless, for example, terms such as "thereafter" expressly or implicitly indicate otherwise, perhaps for technical reasons. The disclosure of multiple actions or functions will therefore not restrict them to a particular order, unless such actions or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single action, function, process, operation, or step may comprise or be subdivided into multiple sub-actions, functions, processes, operations, or steps.Such partial acts may be included in and form part of the disclosure of that single act, unless they are expressly excluded. The examples and features described above and below can be combined. Functional and structural details (e.g., materials, dimensions) described in relation to the examples above apply equally to the examples illustrated in the figures and further described below. More details and aspects are mentioned or cited in connection with the examples described above or below. The processing of a SiC semiconductor body, e.g., a wafer, may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below. Fig. 1 schematically and exemplarily shows a partial cross-sectional view of an example of a vertical power semiconductor device 100. The vertical power semiconductor device comprises a SiC semiconductor body 102, which has a first surface 1031 and a second surface 1032 opposite the first surface 1031. Device elements of an active region, e.g., transistor cells, and / or an edge termination region, e.g., edge termination structures, are formed in an element region 1021 of the semiconductor body 102, which is adjacent to the first surface 1031. The specific structure of the device elements in the element region 1021 depends on the type of vertical power semiconductor device, e.g., JFET, MOSFET, IGBT, or thyristor, and also depends on the specific layout chosen for the transistor cells (TCs) or edge termination structures.The schematic illustrations of the present disclosure may include any of the specific layouts of active regions or specific layouts of edge termination regions and are simplified insofar as the element region containing the active region or the edge termination region in the SiC semiconductor body 102 is indicated by the dashed line 1021. A first wiring level 104 is arranged above the first surface 1031. The first wiring level 104 contains a first lower source or emitter pad 1041 and a second lower source or emitter pad 1042. A second wiring level 106 is arranged on top of the first wiring level 104. The second wiring level 106 contains a gate pad 1061 and a source or emitter pad 1062. The source or emitter pad 1062 of the second wiring level 106 extends laterally over the first lower source or emitter pad 1041 and the second lower source or emitter pad 1042 and is electrically connected to the first lower source or emitter pad 1041 and the second lower source or emitter pad 1042 via a top surface of both the first lower source or emitter pad 1041 and the second lower source or emitter pad 1042. The first wiring level 104 further includes a gate line 1043 between the first lower source or emitter pad 1041 and the second lower source or emitter pad 1042. The gate line 1043 is arranged vertically between the source or emitter pad 1062 of the second wiring level 106 and the first surface 1031. The thickness d1 of the first wiring level 104 is less than the thickness d2 of the second wiring level 106. The gate line 1043 is electrically isolated from the source or emitter pad 1062 of the second wiring level 106 by an interlayer dielectric structure 108, e.g., a first passivation structure 1081 of the interlayer dielectric structure 108. In the exemplary vertical power semiconductor device 100 illustrated in Fig. 1, the first wiring level 104 further includes a lower gate pad 1044, which is arranged between the gate pad 1061 of the second wiring level 106 and the first surface 1031. The lower gate pad 1044 is electrically connected to the gate pad 1061 of the second wiring level 106. A second passivation structure 1082 laterally separates and electrically insulates parts of the second wiring level 106 from each other. As illustrated in Fig. 1, the second passivation structure 1082 laterally separates and electrically insulates the gate pad 1061 and the source or emitter pad 1062 from each other. Fig. 2 schematically and exemplarily shows a partial cross-sectional view of another example of a vertical power semiconductor device 100. The vertical power semiconductor device 100 of Fig. 2 differs from the exemplary device illustrated in Fig. 1 in that the first lower source or emitter pad 1041 extends below the gate pad 1061. The first passivation structure 1081 of the interlayer dielectric structure 108 extends laterally over the first source or emitter pad 1041 to provide electrical insulation between the first source or emitter pad 1041 and the gate pad 1061. A portion of an active region of the vertical power semiconductor device 100, e.g., transistor cells, can be arranged in the semiconductor body 102 directly below the gate pad 1061. Fig. 3 schematically and exemplarily shows a partial cross-sectional view of another example of a vertical power semiconductor device 100. The vertical power semiconductor device 100 of Fig. 3 differs from the exemplary device illustrated in Fig. 1 in that it further includes a structure 110 of currentless plating on the gate pad 1061 and on the source or emitter pad 1062. Fig. 4A schematically and exemplarily shows a partial cross-sectional view of an example of a vertical power semiconductor device 100. Fig. 4B is an exemplary top view of the vertical power semiconductor device 100 from Fig. 4A. Referring to Fig. 4A, Fig. 4B, the vertical power semiconductor device 100 includes a first trench structure 120 extending from the first surface 1031 into the SiC semiconductor body 102. A plurality of second trench structures 122 branch off from the first trench structure 120 (for illustrative purposes, only one of the plurality of parallel second trench structures is shown). The cross-sectional area of ​​the first trench structure 120 is larger than the cross-sectional area of ​​each of the plurality of second trench structures 122. A minimum lateral extent w1 of the first trench structure 120 is larger than a minimum lateral extent w2 of each of the plurality of second trench structures 122. A vertical extent t1 of the first trench structure 120 is larger than a vertical extent t2 of each of the plurality of second trench structures 122. In other examples, the vertical extents t1 and t2 may also be equal. The first trench structure 120 contains a gate conduction material 1201 and a gate conduction dielectric 1202, which is arranged between the gate conduction material 1201 and the SiC semiconductor body 102. Each of the plurality of second trench structures 122 contains a gate electrode material 1221 and a gate dielectric 1222, which is arranged between the gate electrode material 1221 and the SiC semiconductor body 102. The thickness of the gate conduction dielectric 1202 on a bottom side of the first trench structure 120 is greater than the thickness of the gate dielectric 1222 on a bottom side of each of the second trench structures 122. The first trench structure 120 extends laterally to a gate runner 1243, which at least partially surrounds a transistor cell region of the vertical semiconductor device 100. The gate runner 1243 transitions into a gate pad 1241 of a wiring level 124. The gate runner 1243 can be configured as part of the wiring level 124.Alternatively or additionally, the gate runner 1243 can be configured as a continuation of the first trench structure 120, i.e., by a conductive material filled in a trench that is electrically insulated from the SiC semiconductor body 102 by a dielectric. The gate conductor material 1201 of the first trench structure 120 can be electrically connected to the gate runner 1243 at a connection area 126. For example, in a top view, the connection area 126 can be an overlap region between the first trench structure 120 and the gate runner 1243. Furthermore, the wiring plane 124 includes a source or emitter pad 1242. The schematic cross-sectional views in Figures 5A to 5F illustrate an example of the construction of the first trench structure 120 and the second trench structures 122 branching off from the first trench structure 120. For illustrative purposes, the cross-sectional views of the first trench structure 120 and the second trench structures 122 are shown side by side, separated by a dashed line, although these cross-sectional views are taken along different lateral directions, e.g., along line AA' of Figure 4B for the first trench structure 120 and along line BB' for one of the second trench structures 122. Referring to Fig. 5A, a structured mask layer 127, e.g. a hard mask or resist mask, is formed on the first surface 1031 of the SiC semiconductor body 102. Referring to Fig. 5B, a gate conduit trench 1281 and gate trenches 1282 are formed by means of an etching process through openings in the structured mask layer 127. The mask layer 127 is removed, and an optional curing process, e.g., a hydrogen curing process, can be carried out. Referring to Fig. 5C, a dielectric layer structure 130, comprising one or more dielectric layers such as an oxide, a nitride, or tetraethyl orthosilicate (TEOS), is formed, for example, by one or more deposition processes. The dielectric layer structure 130 covers sidewalls and one bottom side of the gate and gate conduction trenches 1282, 1281, as well as the first surface 1031 of the SiC semiconductor body 102. Referring to Fig. 5D, the electrical layer structure 130 is removed in a region of the gate trenches 1282 and remains in the first trench 1281 as the gate conduction dielectric 1202. Referring to Fig. 5E, an electrical layer structure comprising one or more dielectric layers such as a thermal oxide or a nitride or a dielectric with a high dielectric constant is formed in the gate grooves 1282 and remains as the gate dielectric 1222. Referring to Fig. 5F, a conductive layer structure 134, comprising one or more conductive layers, is formed, for example, by means of one or more deposition processes in the gate-conductor trench 1281 and in the gate trenches 1282. The deposition process(s) can be followed, for example, by a recessing or depression process for the conductive material up to the first surface 1031. The conductive layer structure 134 that fills the gate conduction trenches 1281 remains as the gate electrode 1221, and the conductive layer structure 134 that fills the gate trenches 1282 remains as the gate electrode 1221. In the exemplary processes illustrated in Figs. 5A to 5F, the vertical extent t1 of the gate conduction trench 1281 may be equal to or, due to the manufacturing process, slightly greater than the vertical extent t2 of the gate trenches 1282.However, according to other examples, the vertical extent t2 can be set to be greater than t1 by processing the gate conduit trench 1281 and the gate trenches 1282 separately, for example. The description and drawings merely illustrate the principles of revelation. Moreover, all examples cited herein are expressly intended primarily for illustrative purposes only, to assist the reader in understanding the principles of revelation and the concepts contributed by the inventor(s) to advance the state of the art. All statements contained herein that present principles, aspects, and examples of revelation, as well as their specific examples, are intended to include their equivalents. The aspects and features mentioned and described together with one or more of the previously detailed examples and figures can also be combined with one or more of the other examples to replace an identical or similar feature of the other example or to additionally introduce the feature into the other example.

Claims

Vertical power semiconductor device (100) comprising: a SiC semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite the first surface (1031); a first wiring plane (104) above the first surface (1031), wherein the first wiring plane (104) consists of laterally spaced portions of a structured conductive layer or a structured conductive layer stack and has as a portion of the laterally spaced portions a first lower source or emitter pad (1041) and as a further portion of the laterally spaced portions a second lower source or emitter pad (1042);a second wiring level (106) above the first wiring level (104), wherein the second wiring level (106) consists of laterally spaced portions of a structured conductive layer or a structured conductive layer stack and has as part of the laterally spaced portions a gate pad (1061) and as another part of the laterally spaced portions a source or emitter pad (1062), wherein the source or emitter pad (1062) of the second wiring level (106) is electrically connected to the first lower source or emitter pad (1041) and to the second lower source or emitter pad (1042) of the first wiring level (104);and wherein the first wiring level (104) further comprises, as a further part of the laterally spaced parts, a gate line (1043) which is arranged laterally between the first lower source or emitter pad (1041) and the second lower source or emitter pad (1042), wherein the gate line (1043) is arranged vertically between the source or emitter pad (1062) of the second wiring level (106) and the first surface (1031) and the gate line (1043) is electrically insulated from the source or emitter pad (1062) of the second wiring level (106) by an interlayer dielectric structure (108). Vertical power semiconductor device (100) according to the preceding claim, wherein the first wiring level (104) comprises copper and the second wiring level (106) comprises copper. Vertical power semiconductor device (100) according to one of the preceding claims, further comprising a barrier layer arranged between the first wiring level (104) and the second wiring level (106). Vertical power semiconductor device (100) according to the preceding claim, wherein the barrier layer comprises a Ti-W alloy or a Cu-Ti alloy. Vertical power semiconductor device (100) according to one of the two preceding claims, wherein the barrier layer comprises a diffusion barrier for a solder chemistry. Vertical power semiconductor device (100) according to one of the two preceding claims, wherein the barrier layer comprises a voltage compensation layer. Vertical power semiconductor device (100) according to one of the preceding claims, wherein the first wiring level (104) has a thickness (d1) in the range of 2 µm to 7 µm and the second wiring level (106) has a thickness (d2) in the range of 10 µm to 210 µm. Vertical power semiconductor device (100) according to one of the preceding claims, wherein the interlayer dielectric structure (108) comprises a first passivation structure (1081) comprising an imide, an oxide or a nitride. Vertical power semiconductor device (100) according to the preceding claim, further comprising a second passivation structure (1082) arranged on a part of the first passivation structure (1081). Vertical power semiconductor device (100) according to one of the preceding claims, further comprising a structure (110) of a currentless plating on the gate pad (1061) and on the source or emitter pad (1062). Vertical power semiconductor device (100) according to the preceding claim, wherein the structure (110) of a currentless plating comprises a NiMoP layer or a NiP / Au or a NiP / Pd / Au or a NiP / Ag or a NiMoP / Ag layer stack. Vertical power semiconductor device (100) according to one of the preceding claims, wherein the first wiring level (104) further comprises a lower gate pad (1044) arranged between the gate pad (1061) of the second wiring level (106) and the first surface (1031), wherein the lower gate pad (1044) is electrically connected to the gate pad (1061) of the second wiring level (106). Vertical power semiconductor device (100) according to one of the preceding claims, wherein the first lower source or emitter pad (1041) extends laterally below the gate pad (1062) of the second wiring level (106), wherein the first lower source or emitter pad (1041) is electrically isolated from the gate pad (1061) of the second wiring level (106) by the interlayer dielectric structure (108). Method for manufacturing a vertical power semiconductor device (100), the method comprising: forming a first wiring plane (104) over a first surface (1031) of a SiC semiconductor body (102) having the first surface (1031) and a second surface (1032) opposite the first surface (1031), wherein the first wiring plane (104) consists of laterally spaced portions of a structured conductive layer or a structured conductive layer stack and has as a portion of the laterally spaced portions a first lower source or emitter pad (1041) and as a further portion of the laterally spaced portions a second lower source or emitter pad (1042);Forming a second wiring level (106) above the first wiring level (104), wherein the second wiring level (106) consists of laterally spaced portions of a structured conductive layer or a structured conductive layer stack and has as part of the laterally spaced portions a gate pad (1061) and as another part of the laterally spaced portions a source or emitter pad (1062), wherein the source or emitter pad (1062) of the second wiring level (106) is electrically connected to the first lower source or emitter pad (1041) and to the second lower source or emitter pad (1042) of the first wiring level (104);and wherein the first wiring level (104) further comprises, as a further part of the laterally spaced parts, a gate line (1043) which is arranged laterally between the first lower source or emitter pad (1041) and the second lower source or emitter pad (1042), wherein the gate line (1043) is arranged vertically between the source or emitter pad (1062) of the second wiring level (106) and the first surface (1031) and the gate line (1043) is electrically insulated from the source or emitter pad (1062) of the second wiring level (106) by an interlayer dielectric structure (108).

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