MANUFACTURING METHOD OF A FLAT TRENCH INSULATION STRUCTURE WITH NITRIDE RETRACTION BY IMPLANTATION TREATMENT

Abstract

A method for forming a semiconductor device, comprising: exposing an upper surface (112) of a semiconductor layer (110) through an opening in a dielectric layer; forming a trench (T11) in the semiconductor layer (110) below the opening; forming a first lining layer (141) on a trench surface (115) of the semiconductor layer (110) in the trench (T11); implanting an element type into the dielectric layer; removing the first lining layer (141) and a portion of the dielectric layer, thereby forming a recess (117) between the dielectric layer and the upper surface (112); forming a second lining layer (142) on the trench surface (115), the second lining layer (142) extending into the recess (117); and forming an insulating structure in the trench (T11).

Description

TECHNICAL FIELD

[0001] This disclosure relates generally to semiconductor devices and, more particularly, but not exclusively, to forming shallow trench isolation structures. BACKGROUND

[0002] Shallow trench isolation (STI) structures are commonly used in semiconductor devices to isolate one active region from another active region on a semiconductor substrate. However, multiple oxide deglazing steps or other steps after an STI trench is filled with dielectric material can create or enlarge a "pit" at the edge of the STI trench. This pit can degrade the performance of a transistor formed adjacent to the trench. SUMMARY

[0003] Various disclosed methods and devices may be advantageously applied to transistor devices, methods of forming transistor devices, or other applications where high voltages may be applied in the devices. While such examples may be expected to offer performance improvements over baseline devices and methods, such as improved drain current (I D )-Gate voltage(V G ) characteristics, no particular result is required in the present invention unless it is expressly mentioned in a particular claim.

[0004] In one aspect of the present disclosure, a method of forming a semiconductor device includes exposing a top surface of a semiconductor layer through an opening in a dielectric layer. A trench is formed in the semiconductor layer below the opening. A first liner layer is formed on a trench surface of the semiconductor layer in the trench. A device species is implanted into the dielectric layer. The first liner layer and a portion of the dielectric layer are removed, thereby forming a recess between the dielectric layer and the top surface. A second liner layer is formed on the trench surface, the second liner layer extending into the recess. An isolation structure is formed in the trench.

[0005] In another aspect of the present disclosure, a method of forming a semiconductor device includes forming an opening in an oxide layer and a nitride layer above a semiconductor layer. At least one elemental species is implanted into the nitride layer. A trench is formed in the semiconductor layer below the opening. A wet acid etch removes a portion of the nitride layer, exposing a corner of the semiconductor layer, and a recess is formed between the nitride layer and the semiconductor layer. A liner layer is formed on the semiconductor layer in the trench, and the liner layer extends from a sidewall of the trench into the recess. An isolation structure is formed in the trench.

[0006] In another aspect of the present disclosure, a semiconductor device includes a trench extending into a semiconductor layer. A liner layer is located on a sidewall of the semiconductor layer in the trench. The liner layer extends from the sidewall to a top surface of the semiconductor layer. An isolation structure is located in the trench. The isolation structure is located between a first region of the semiconductor layer and a second region of the semiconductor layer. The semiconductor layer includes a third region connecting the first region to the second region of the semiconductor layer. The third region of the semiconductor layer is substantially free of phosphorus impurities. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a detailed description of various examples, reference is now made to the attached drawings, which show: Fig. 1 to Fig. 11C shows cross-sectional views of example structures at various stages of forming an example semiconductor device using an example method; Fig. 11D is a plan view of exemplary structures at the same stage of formation as in Fig. 11B and Fig. 11C; and Fig. 12 to Fig. 15 Cross-sectional views of example structures at various stages of forming another example semiconductor device using another example method. DETAILED DESCRIPTION

[0008] Shallow trench isolation (STI) structures are commonly used in semiconductor devices to electrically isolate electrical devices in adjacent active areas of a semiconductor substrate. Some STI structures are formed by etching a trench in a semiconductor substrate using a silicon nitride hard mask over a silicon oxide "pad oxide" layer. The trench is then filled with a dielectric material, such as a plasma oxide, and the oxide fill is polished back to the silicon nitride layer using a chemical mechanical polishing (CMP) process. Some process flows include multiple oxide deglazing steps after the STI trench is filled. These deglazing steps can result in loss of dielectric material at the trench corners where the dielectric material meets a trench sidewall, resulting in a "pit" at such locations.This depression sometimes results in a location where a later-formed polysilicon gate is separated from the underlying semiconductor substrate by an oxide layer thinner than a gate oxide layer. The polysilicon is sometimes referred to as "wrapping" the trench corner. This thin oxide region can lead to a parasitic corner transistor that has a lower threshold voltage than the transistor to be formed, resulting in undesirable performance of the semiconductor device, such as an undesirable "hump" in the drain current (I). D )-Gate voltage(V G ) characteristic curve.

[0009] In some process technologies, the nitride hardmask layer is stripped away from the STI trench using hot phosphoric acid to subject the STI corner to a subsequent thermal oxidation step. The increased exposure results in greater conversion of the silicon at the corner to thermal oxide, rounding the corner and increasing the thickness of the thermal oxide, thus avoiding the parasitic transistor. Such a strategy may be suitable for some applications, such as switching transistors, where the transistor's specific IV characteristic is not necessarily paramount to the transistor's electrical properties. However, in analogous applications, the use of hot phosphoric acid to strip back the nitride layer can lead to phosphorus contamination in the semiconductor region adjacent to the STI structure.Phosphorus contamination can cause leakage between adjacent devices and IV characteristics that are undesirable for analog applications.

[0010] Some examples of the present disclosure provide semiconductor devices and methods for forming such devices that reduce or eliminate the effect of the parasitic corner transistor without the aforementioned phosphorus contamination. In some example methods, an atomic species is implanted into the silicon nitride hardmask to weaken the silicon nitride and thereby render the weakened silicon nitride soluble in aqueous hydrofluoric acid (HF), thereby stripping the nitride hardmask without the use of phosphoric acid. Such methods and semiconductor devices may be advantageously employed, for example and without implicit limitation, in integrated circuits having analog transistors or high-voltage transistors.

[0011] Fig. 1 to Fig. 11C show cross-sectional views of example structures at various stages of forming an example semiconductor device, e.g., an integrated circuit (IC) 100 including an STI isolation structure, and accordingly illustrate an example method of forming the IC 100. Fig. Figure 11D shows a top view of exemplary structures at a similar stage of formation as Fig. 11B and Fig. 11C. Some of the Fig. 1 to Fig. 11 include Cartesian coordinates as a reference to facilitate visualization and reference.

[0012] First, with reference to Fig.1, the IC 100 is shown at an early stage of fabrication. The semiconductor layer 110 may be a semiconductor substrate, such as a handle wafer, or a layer formed over a substrate, such as an epitaxial layer. In the following description, the semiconductor layer is referred to as silicon, but other examples may include semiconductor materials such as GaAs, SiGe, and the like. In various examples, the semiconductor layer is a lightly doped p-type layer, but it is not limited to any particular conductivity type or doping level. A silicon oxide layer 120 has been formed over a top surface 112 of the semiconductor layer 110, and a silicon nitride layer 130 has been formed over the silicon oxide layer 120. (Hereinafter, a silicon oxide layer may be referred to as an "oxide layer" and a silicon nitride layer as a "nitride layer").The oxide layer 120 may sometimes also be referred to as the pad oxide layer 120.

[0013] With reference to the coordinates in Fig. 1, the X-axis and Y-axis are orthogonal to each other and parallel to the upper surface 112, which is why they are referred to as the "in-plane direction." The Z-axis is perpendicular to the X- and Y-axes and is therefore referred to as the "out-of-plane direction."

[0014] A patterned photoresist layer M11 has been formed over the nitride layer 130 and includes openings where trenches for isolation structures, e.g., STI isolation structures, are to be formed using an etch process 2100. The etch process 2100 may comprise any suitable process, such as an RIE plasma etch process. The etch process 2100 may comprise multiple process recipes to remove the nitride layer 130, then the pad oxide layer 120, and then the semiconductor layer 110.

[0015] Fig.2 shows the IC 100 after forming trenches T11 by the etching process 2100. The trenches T11 may have a depth of less than 1 µm and are therefore sometimes referred to as "shallow" trenches compared to deeper trenches with a greater depth. In some examples, the trenches T11 have a depth of 0.1 µm to 0.7 µm. The semiconductor regions 113 are located between the trenches T11 and are sometimes also referred to as "mesas" 113. Thus, the nearest regions, or mesas 113, of the semiconductor layer 110 are spaced from each other by the trenches T11 and connected by regions 114. The trenches T11 each have a trench surface 115 comprising a bottom surface and side surfaces. Above each mesa 113 there is a remaining portion 120A of the pad oxide layer 120 between the mesa 113 and a remaining portion of the nitride layer 130, hereinafter referred to as hard mask 130A.The following discussion concerns a single hard mask 130A over a single mesa 113, with no implied limitation on any particular number of remaining portions of the nitride layer 130 that may be formed.

[0016] Fig. 3 shows the IC 100 after forming a recess 117 (e.g., undercut) between the mesa 113 and the corresponding hard mask 130A, e.g., by etching a portion of the pad oxide layer 120 with dilute aqueous hydrogen fluoride or another suitable etchant. The recesses 117 expose corners of the trenches T11 at the top of the trench sidewalls for a subsequent oxidation step and allow the later formed liner layers (see, e.g., liner layers 141 in Fig. 4) to extend into the recesses 117.

[0017] Fig.4 shows the IC 100 after forming the liner layers 141 on or over the trench surfaces 115 of the semiconductor layer 110, extending into the recesses 117. The liner layers 141 may be formed, for example, by a thermal oxidation process or other suitable oxidation processes. The exposed trench corners are partially consumed by the oxidation, so that rounded corners 116 are formed between the trenches T11 and the top surface 112 of the semiconductor layer 110. In examples where the material of the semiconductor layer 110 is silicon, the liner layer 141 comprises silicon oxide. Rounding the corners 116 causes an increase in the radius of curvature of the rounded corners 116, which may increase the thickness of the liner layer 141 over the rounded corners 116 and reduce the electric fields at the rounded corners 116 during operation of the IC 100.

[0018] Fig.5 shows the IC 100 during the implantation of at least one elemental species into the liner layers 141 and edge regions 131 of the hard mask 130A by ion implantation 2300. The elemental species generally comprises a non-dopant element such as a Group IV element (e.g., Si or Ge) or a noble element (e.g., Ne, Ar, or Kr). The implantation of the elemental species may weaken the silicon nitride in the edge regions 131, making the edge regions more soluble in an etchant in which silicon nitride is normally poorly soluble. In one example, the ion implantation 2300 comprises implanting the elemental species with an energy in the range of 3 keV to 10 keV. In some examples, the semiconductor layer 110 may be angled with respect to the direction of the implantation beam by an angle in the range of +5 degrees to +45 degrees and -5 degrees to -45 degrees, e.g., B. + / -15 degrees.The tilt angle is defined as the angle between a direction orthogonal to the top surface 112 (surface normal or Z-axis) and the direction of the implantation beam. In certain examples, the dose of the implanted element type is in the range of 2×10. 14 cm -2 up to 7×10 15 cm -2 . In some examples, the implantation may be performed multiple times (or may include multiple implantations or implantation processes) to improve the uniformity of the implantation. In certain examples, the implantation (such as implantation 2300) is performed four times, and the handle wafer is rotated 90 degrees after each implantation. In the example of Fig. 5, the hard mask 130A has a width W130A and the implantation-treated edge region 131 has a width W131 at each end (or side) of the hard mask 130A.

[0019] Fig.6 shows the IC 100 after removing the liner layer 141 and the edge regions 131 with an isotropic etch process 2400. The etch process 2400 may be any process that removes the liner layer 141 faster than the etch process 2400 removes silicon nitride and is substantially free of phosphorus. In some examples, the etch process 2400 uses a wet chemical etchant comprising hydrogen fluoride (HF). For example, the etch process 2400 may use an aqueous solution of hydrogen fluoride comprising a unit volume of -50% aqueous HF (as received) diluted with 100 unit volumes of DI water (v / v) to produce a 1:100 HF:H2O v / v solution. Such a solution may have an HF molarity of 0.02–0.03 M and is commonly referred to as a dilute HF solution. In some examples, the wet chemical etchant includes a buffering agent such as ammonium fluoride (NH4F).The semiconductor layer 110 may be immersed in the wet chemical etchant for about 5 minutes at about 22°C during the etching process 2400. In some examples, a 1:100 HF:H2O solution removes the implant-treated edge region 131 about four times faster than the untreated hard mask 130A. In the context of a wet chemical etchant, "substantially free of phosphorus" means that the etchant comprises no more than 1 ppm of phosphorus.

[0020] By removing the edge region 131, the hard mask 130A is retracted along the X and Y axes (not shown), resulting in a shortened hard mask 130B over the mesa 113. Retracting the hard mask 130B results in a reduced width W130B of the hard mask 130B. In some examples, a retraction distance (equal to the width W131 of the removed edge region 131, Fig.5) each end (or side) of the hard mask 130B in a range of 10 nm to 15 nm, and the width W130B is reduced by 20 nm to 30 nm with respect to the width W130A. Furthermore, the etching process 2400 removes the liner layer 141, exposing the rounded corners 116 and forming a recess 117 between the hard mask 130B and the mesa 113. By using dilute aqueous hydrogen fluoride instead of hot phosphoric acid to remove the implanted edge region 131 of the hard mask 130A and to remove the liner layer 141, phosphorus contamination in the semiconductor layer 110 (such as the mesa 113 and region 114, and the silicon nitride layer may sometimes be referred to as the hard mask 130), which might otherwise result from the use of hot phosphoric acid, can be prevented. Accordingly, the semiconductor layer 110 may be substantially free of phosphorus impurities (or phosphorus).With respect to the semiconductor layer 110, the term “substantially free of phosphorus contamination” or the like means that the phosphorus concentration in the semiconductor layer 110 is not greater than about 1 E12 cm. -3 is.

[0021] If, on the other hand, hot phosphoric acid were used to strip back the hard mask 130A, a portion of the phosphorus could diffuse into the semiconductor layer 110, resulting in phosphorus contamination of the semiconductor layer 110. The subsequent formation of lining layers (such as those shown in Fig.7) may involve curing at a temperature of approximately 1050°C, which may diffuse the phosphorus contamination deeper into the semiconductor layer 110. Such phosphorus contamination may lead to undesirable leakage current between electronic components in adjacent mesas 113 that are intended to be electrically isolated by an intervening STI structure, which may potentially impair the performance of the IC 100, e.g., by increasing standby leakage currents and / or battery power dissipation, or possibly lead to failure of the IC 100.

[0022] Fig.7 shows the IC 100 after forming liner layers 142 on or over the trench surfaces 115 extending into the recesses 117, e.g., between the mesa 113 and the hard mask 130B. The liner layers 142 may be formed by a thermal oxidation process or other suitable oxidation process, which may round or further round the rounded corners 116 by consuming additional semiconductor material at the corners of the trenches T11. This rounding may further increase the radius of curvature of the rounded corners 116 and provide a thicker oxide layer at the corner than would be the case with a smaller radius of curvature.The liner layer 142 is wrapped around and covers the respective rounded corner 116 of the semiconductor layer 110, where "wrapped" means that the liner layer 142 forms a continuous layer extending from the trench surface 115 across the rounded corner 116 to the top surface 112. The thicker oxide at the rounded corner 116 can prevent or mitigate local thinning of the gate oxide in a subsequent gate oxidation step, which could otherwise lead to gate oxide failure in the presence of a high electric field at the corner.

[0023] Fig.Figure 8 shows the IC 100 after depositing an insulation material 151 into the trenches T11 and over the hard mask 130B. The insulation material 151 may generally have a topography resulting in a non-planar top surface. In some examples, the insulation material 151 comprises an oxide such as plasma-deposited silicon oxide. In certain examples, the insulation material 151 is deposited by a high-density plasma (HDP) process and may be HDP-deposited silicon oxide.

[0024] Fig. 9 shows the IC 100 after planarization of the insulation material 151 by chemical mechanical polishing (CMP) or another suitable planarization technique. In the described example, the hard mask 130B can serve as both a CMP stop layer and a hard mask for the trench etch process 2100 ( Fig.1). During planarization, the insulation material 151 above the hard mask 130B is removed, separating portions of the insulation material 151 located in the trenches T11 to create insulation structures 150. The planarization may result in surfaces of the insulation structures 150 that are approximately coplanar with the top surface of the hard mask 130B, as shown, or the surfaces may be slightly offset below the top surface of the hard mask 130B.

[0025] Fig.10 shows the IC 100 after removing the hard mask 130B, e.g., by hot phosphoric acid etching or oxide-selective dry etching. The underlying pad oxide layer 120, the liner layer 142 (e.g., the sidewall oxide), and the isolation material 151 may protect the mesa 113 and the trench surface 115 (such as the trench sidewalls) from phosphorus contamination. The silicon nitride removal process may also remove a portion of the isolation structures 150 due to the non-zero etch rate of the isolation material (oxide), thereby reducing the height of the isolation structures 150 above the top surface 112 and rounding the corners of the isolation structures 150.

[0026] Fig.11A-11D illustrate aspects of forming one or more passive or active electronic components of IC 100. Such components may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar transistor, a diode, a drain-extended MOS transistor (DEMOS), or other suitable electronic component. In the following discussion, a MOSFET 128 is illustrated as an example.

[0027] In Fig.11A, a deglazing process (oxide removal) was performed, stripping the pad oxide layer 120 and creating recesses at the corners of the isolation structures 150. The recesses may cause the oxide remaining over the rounded corners 116 to become thinner, but according to the described examples, the remaining oxide is thicker than might otherwise be the case in a basic process flow. A gate dielectric layer 121 was formed over the mesa 113, e.g., by thermal oxidation, and a gate electrode layer 122, e.g., polysilicon, was formed over the gate dielectric layer 121.

[0028] Fig. 11B shows the MOSFET 128 in a section through the XZ plane, Fig. Figure 11C shows the MOSFET 128 in a section through the YZ plane and Fig. Figure 11 D shows the MOSFET 128 in plan view in the XY plane. In the following discussion, reference is also made to Fig.11B-11D. In one non-limiting example, semiconductor layer 110 is p-type.

[0029] The gate electrode layer 122 and the gate dielectric layer 121 were patterned to form a gate electrode 122' and a gate dielectric 121'. Various dopant implantations were performed to create the source / drain extension regions 123, 124, the source region 125, and the drain region 126. Sidewall spacers 127 were formed on the sidewalls of the gate electrode 122'. Silicide layers 195 provide ohmic contact to the source region 125 and the drain region 126. A channel region 191 is located beneath the gate dielectric 121' and can conduct current between the source region 125 and the drain region 126 when an appropriate voltage is applied to the gate electrode 122'. Fig.11 D includes unreferenced vertical connections to the source region 125, the drain region 126 and the gate electrode 122'.

[0030] For example, an n-type range 118 ( Fig. 11B) having an N+ dopant concentration may be formed by implanting n-type dopants into a portion of semiconductor layer 110. N-type region 118 and semiconductor layer 110 form a diode 129 with a pn junction between n-type region 118 and semiconductor layer 110. In another example, a substrate contact 119 having a P+ dopant concentration may be formed by implanting p-type dopants into a portion of semiconductor layer 110 to increase the dopant concentration. In other examples, other devices may be formed in or above semiconductor layer 110.

[0031] Fig.Figure 11C shows the MOSFET 128 in a section along the long axis of the gate electrode 122', e.g., the Y-axis. The gate electrode 122' extends over two adjacent STI structures 150, including over the depressions at the rounded corners 116 of the trenches T11, which it fills. Each liner layer 142 is wrapped around and covers the rounded corners 116 of the respective trench T11. Since the thickness of the liner layers 142 over the rounded corners 116 is thicker than the gate dielectric 121', the MOSFET 128 is expected to have an I D -Vg characteristic curve which is essentially independent of the thickness of the lining layers 142 at the rounded corners 116, e.g. it does not show the above-mentioned hump in the I D -Vg characteristic curve.

[0032] Furthermore, the semiconductor layer 110 (including the mesa 113 and the regions 114) is expected to be substantially free of phosphorus contamination due to the use of aqueous HF to remove weakened portions of the hard mask 130A, which may be achieved by an implantation to treat the edge region 131 of the hard mask 130A (see, e.g., Fig. 5) and further, the stripping of the hard mask 130A can be achieved with the aqueous HF. Thus, the mesa 113 and regions 114 are expected to be free of phosphorus contamination (or phosphorus), and accordingly, leakage current between the diode 129 and the MOSFET 128 in the IC 100 is expected to be prevented or reduced compared to alternatives involving the use of hot phosphoric acid to strip a nitride layer over the mesa 113.

[0033] In some examples, semiconductor layer 110 comprises silicon, pad oxide layer 120 comprises silicon oxide (such as SiO2), gate dielectric layer 121 comprises silicon oxide, liner layer 142 comprises silicon oxide, hard mask 130A comprises silicon nitride, and STI structure 150 comprises silicon oxide. The STI material (such as STI fill oxide) of STI structure 150 may be deposited in various ways, e.g., using a high-density plasma (HDP) process or a non-plasma high-aspect-ratio chemical vapor deposition (HARP) process, and may be subjected to various thermal post-treatments.

[0034] Fig. 12 to Fig.15 show cross-sectional views of exemplary structures at various stages of forming another exemplary integrated circuit (IC) 1200 including an STI structure, and accordingly illustrate an alternative exemplary method for forming a semiconductor device with an STI structure. In this method, an edge region of the hard mask is treated by implantation prior to forming the STI trench in the semiconductor layer 210. Accordingly, a liner layer, such as the liner layer 141 ( Fig. 4) It is not necessary to protect the semiconductor layer 210 because the element-implanted portions of the semiconductor layer 210 are removed when the STI trench is formed in the semiconductor layer 210. Accordingly, the manufacturing cost can be reduced.

[0035] Fig.12 shows the IC 1200 after forming an oxide layer (e.g., a pad oxide layer) 220 on or over a semiconductor layer 210 (such as a silicon layer) and a nitride layer 230 on or over the oxide layer 220. The nitride layer 230 has a width W230A. The semiconductor layer 210 has a top surface 212. Openings in the oxide layer 220 and the nitride layer 230 expose portions of the top surface 212 of the semiconductor layer 210.

[0036] Fig.13 shows the IC 1200 during the implantation of at least one elemental species into the edge regions 231 of the nitride layer 230 by ion implantation 2500. In some examples, the elemental species comprises a non-dopant element such as a Group IV element (e.g., Si or Ge) or a noble element (e.g., Ne, Ar, or Kr). The elemental species is implanted into the edge regions 231 so that the edge regions 231 can be etched with dilute aqueous hydrogen fluoride. The at least one elemental species is also implanted into portions of the semiconductor layer 210 adjacent to exposed portions of the top surface 212. Various parameters or configurations of the ion implantation 2500, such as the tilt angle between the top surface 212 and the direction of the implantation beam, the implantation energy, and the implantation dose, may be the same as or similar to the previously described implantation 2300.

[0037] Fig.14 shows a cross-section of IC 1200 after forming trenches T21 in the semiconductor layer by an etching process 2600. In some examples (not shown), a patterned photoresist layer is present during etching process 2600. Etching process 2600 creates trenches T21 in semiconductor layer 210.

[0038] Fig. 15 shows the IC 1200 after etching by an etching process 2700. At least a portion of the edge regions 231 has been removed by the etching process 2700, and a portion of the oxide layer 220 has also been removed to form a recess 226 between the nitride layer 230 and the top surface 212. A dilute aqueous HF solution can be used for the etching process 2700, as previously described. The removal of the edge region 231 retracts the nitride layer 230 (reduces the lateral width of the nitride layer 230), so that the width of the nitride layer 230 from W230A ( Fig.12) is reduced to W230B. Accordingly, the corner 216 of the semiconductor layer 210 is exposed at the trench T21. As previously described, phosphorus contamination of the semiconductor layer 210 (such as regions 213 and 214) by hot phosphoric acid can be prevented. Accordingly, the semiconductor layer 210 (including regions 213 and 214) is substantially free of phosphorus.

[0039] Furthermore, processes or steps that are identical to the methods or steps of the Fig. 7 to Fig. 11 to form a semiconductor device that is the same as or similar to the IC 100 described above. Reference may be made to the above descriptions, such as descriptions related to the IC 100 and the method of forming the IC 100.

[0040] Table 1 includes examples of etchback rates in nitride hardmask layers without and with ion implantation after etching with dilute aqueous HF. In these examples, 1 volume unit of HF is diluted with 100 volume units of H2O. In other examples, the dilute aqueous hydrogen fluoride may have a different suitable concentration. Table 1 implantation Nitride layer without implantation Nitride layer with 5 keV Si implantation Nitride layer with 12 keV Si implantation Nitride layer with 9 keV Ge implantation Retraction distance (nm) 0,0 9,9 11,6 11,9

[0041] Nitride layer pullback indicates that a portion of the nitride layer is removed along a lateral direction (such as + / - X direction in Fig. 6, Fig. 15) is etched away, so that the lateral width of the nitride layer is reduced (see e.g. Fig. 6, Fig.15). In the examples of Table 1, the nitride layers are etched with a 1:100 HF:H2O solution for five minutes. The pullback distance for a nitride layer without Si or Ge implantation is zero, the pullback distance with a 5 keV Si implantation is 9.9 nm, the pullback distance with a 12 keV Si implantation is 11.6 nm, and the pullback distance with a 9 keV Ge implantation is 11.9 nm. These examples demonstrate that treating a silicon nitride layer such as hard mask 130A with ion implantation (e.g., with Si or Ge) results in sufficient pullback with HF etching to enable the described processes without phosphorus contamination of a semiconductor substrate in which STI structures are formed.

[0042] Unless otherwise specified, "about," "approximately," or "substantially" before a value means + / - 10 percent of the stated value. Modifications to the described examples are possible, and other examples are also conceivable within the scope of the claims.

Claims

[1] A method of forming a semiconductor device, comprising: Exposing an upper surface of a semiconductor layer through an opening in a dielectric layer; Forming a trench in the semiconductor layer under the opening; Forming a first liner layer on a trench surface of the semiconductor layer in the trench; Implanting an element type into the dielectric layer; Removing the first liner layer and a portion of the dielectric layer, thereby forming a recess between the dielectric layer and the top surface; Forming a second lining layer on the trench surface, the second lining layer extending into the recess; and Forming an isolation structure in the trench. [2] The method of claim 1, wherein the dielectric layer comprises silicon nitride, and further comprising removing the portion of the dielectric layer with hydrofluoric acid. [3] The method of claim 1, wherein forming the second liner layer comprises thermally oxidizing the semiconductor layer, thereby rounding an STI corner between the recess and the trench. [4] The method of claim 1, wherein the semiconductor layer comprises silicon and the first and second cladding layers comprise silicon oxide. [5] The method of claim 1, wherein implanting the elemental species into the first liner layer and the dielectric layer comprises implanting at least one of silicon, germanium, or argon. [6] The method of claim 1, wherein implanting the element type into the first liner layer and the dielectric layer comprises implanting the element type at an inclination angle in a range of +5 degrees to +45 degrees with respect to a normal to the top surface. [7] The method of claim 1, wherein implanting the element type into the dielectric layer increases a wet etching rate at a surface of the dielectric layer with respect to an interior of the dielectric layer. [8] The method of claim 1, wherein implanting the elemental species comprises implanting at least one of silicon, germanium, or argon with an implantation energy in the range of 3 keV to 10 keV. [9] The method according to claim 1, wherein the dose of the elemental species is in a range of 2×10 14 cm -2 up to 7×10 15 cm -2 lies. [10] The method of claim 1, wherein removing the portion of the dielectric layer comprises exposing the dielectric layer to a hydrogen fluoride solution having a molar HF concentration in the range of about 0.2 mol / liter to about 0.3 mol / liter for five minutes. [11] The method of claim 1, wherein removing the portion of the dielectric layer comprises exposing the dielectric layer to a hydrogen fluoride solution substantially free of phosphorus. [12] The method of claim 1, further comprising: Forming a transistor in a first region of the semiconductor layer forming a first sidewall of the recess; and Forming a diode in a second region of the semiconductor layer forming a second sidewall of the recess. [13] The method of claim 1, further comprising forming a gate electrode of a transistor, the gate electrode extending over the isolation structure and into the recess. [14] A method of forming a semiconductor device, comprising: Forming an opening in an oxide layer and a nitride layer over a semiconductor layer; implanting at least one type of element into the nitride layer; Forming a trench in the semiconductor layer under the opening; Removing a portion of the nitride layer by wet acid etching, thereby exposing a corner of the semiconductor layer, and forming a recess between the nitride layer and the semiconductor layer; Forming a liner layer on the semiconductor layer in the trench, the liner layer extending from a sidewall of the trench into the recess; and Forming an isolation structure in the trench. [15] The method of claim 14, wherein forming the liner layer comprises thermally oxidizing the semiconductor layer. [16] The method of claim 14, wherein the semiconductor layer comprises silicon. [17] The method of claim 14, wherein implanting the elemental species into the nitride layer comprises implanting at least one of silicon, germanium, or argon into the nitride layer. [18] A semiconductor device comprising: a trench extending into a semiconductor layer; a liner layer on a sidewall of the semiconductor layer in the trench, the liner layer extending from the sidewall to a top surface of the semiconductor layer; and an isolation structure in the trench, wherein: the insulation structure is located between a first region of the semiconductor layer and a second region of the semiconductor layer; the semiconductor layer comprises a third region connecting the first region to the second region of the semiconductor layer; and the third region of the semiconductor layer is substantially free of phosphorus impurities. [19] A semiconductor device according to claim 18, wherein the third region of the semiconductor layer is adjacent to the cladding layer. [20] A semiconductor device according to claim 18, further comprising: a diode in the first region of the semiconductor layer; and a transistor in the second region of the semiconductor layer.

Images