Power semiconductor device: Method for manufacturing a power semiconductor device

Abstract

Power semiconductor device (1) comprising in a single chip: a semiconductor body (10) configured to conduct a load current between a first load terminal (11) on a first side (110) of the semiconductor body (10) and a second load terminal (12) on a second side (120) of the semiconductor body (10); a drift region (100) of a first conductivity type within the semiconductor body (10); trenches (14, 16) extending from the first side (110) to the second side (120), each trench (14, 16) comprising a trench electrode (141, 161) separated from the semiconductor body (10) by a trench insulator (142, 162); Meses (15; 18) which are laterally bounded by the trenches (14, 16), wherein the meses (15; 18) include first-type meses (18) and second-type meses (15); and semiconductor structures (151, 152, 153).Each semiconductor structure comprises a series connection of a first conductivity-type region (151) coupled to or formed by the drift region (100); a second conductivity-type region (152); and a third conductivity-type region (153) coupled to the first load terminal (11) by at least one ohmic resistor (1531; 1534) and a Zener diode (1533). Each first-type mesa (18) is configured to conduct the load current, is electrically connected to the first load terminal (11), and is free of any of the semiconductor structures (151, 152, 153). The semiconductor structures (151, 152, 153) are arranged in the second-type mesa (15).

Description

TECHNICAL FIELD

[0001] This description relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on power semiconductor devices. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications, including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device typically comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is typically conducted via an active region of the power semiconductor device. The active region is typically surrounded by an edge termination region terminated by an edge of the chip.

[0004] In the case of a controllable power semiconductor device, e.g., a transistor, the load current path can be controlled by means of an insulated electrode, commonly referred to as the gate electrode. For example, upon receiving a corresponding control signal, e.g., from a driver unit via a control terminal of the device, the control electrode can place the power semiconductor device between a forward conducting state and a blocking state.

[0005] Furthermore, some devices provide reverse current capability; that is, the active region of the semiconductor body is further configured to conduct a reverse current along a reverse current path between the two load terminals of the device. For example, the RC (reverse current) IGBT is one example of such devices. In an RC-IGBT, a single chip combines an IGBT structure and a diode structure.

[0006] Regardless of whether the device has an RC configuration or not, it is generally a goal to design a power semiconductor device to have high robustness, i.e. with respect to handling overload situations during which the load current temporarily exceeds the rated load current, e.g. due to a short circuit situation or the like. SUMMARY

[0007] The subject matter of the independent claims is presented. Features of exemplary embodiments are defined in the dependent claims.

[0008] According to one embodiment, a power semiconductor device in a single chip comprises: a semiconductor body configured to conduct a load current between a first load terminal on a first side of the semiconductor body and a second load terminal on a second side of the semiconductor body; a drift region of a first conductivity type within the semiconductor body; trenches extending from the first side to the second side, each trench including a trench electrode separated from the semiconductor body by a trench insulator; meses laterally bounded by the trenches, the meses including meses of the first type and meses of the second type; and semiconductor structures.Each semiconductor structure includes a series connection of a first region of the first conductivity type coupled to or formed by the drift region; a second region of a second conductivity type; and a third region of the first conductivity type coupled to the first load terminal through at least one of a first ohmic resistor and a Zener diode. Each mesa of the first type is configured for load current conduction, electrically connected to the first load terminal, and free of any of the semiconductor structures. The semiconductor structures are arranged in the mesa of the second type.

[0009] According to another embodiment, a method of manufacturing a power semiconductor device comprises forming the following components in a single chip: a semiconductor body configured to conduct a load current between a first load terminal on a first side of the semiconductor body and a second load terminal on a second side of the semiconductor body; a drift region of a first conductivity type within the semiconductor body; trenches extending from the first side to the second side, each trench including a trench electrode separated from the semiconductor body by a trench insulator; meses laterally bounded by the trenches, the meses including meses of the first type and meses of the second type; and semiconductor structures.Each semiconductor structure includes a series connection of a first region of the first conductivity type coupled to or formed by the drift region; a second region of a second conductivity type; and a third region of the first conductivity type coupled to the first load terminal through at least one of a first ohmic resistor and a Zener diode. Each mesa of the first type is configured for load current conduction, electrically connected to the first load terminal, and free of any of the semiconductor structures. The semiconductor structures are arranged in the mesa of the second type.

[0010] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The parts in the figures are not necessarily to scale, but rather the emphasis is on illustrating the principles of the invention. Furthermore, like reference numerals designate corresponding parts throughout the figures. In the drawings: Fig. 1 schematically and exemplarily shows a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; Fig. 2 schematically and exemplarily shows a section of a horizontal projection of a power semiconductor device according to one or more embodiments; Fig. 3 schematically and exemplarily shows a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; Fig. 4 schematically and exemplarily shows a section of a horizontal projection of a power semiconductor device according to one or more embodiments; Fig. 5 schematically and exemplarily shows a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; Fig. 6 schematically and exemplarily shows three sections of a horizontal projection of a power semiconductor device according to some embodiments; Fig. 7-9 each schematically and exemplary sections of a vertical cross section of a power semiconductor device according to some embodiments; Fig. 10-19 each schematically and exemplarily show a portion of a horizontal projection of a power semiconductor device according to some embodiments; and Fig. 20-25 each schematically and exemplary sections of a vertical cross section of a power semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0012] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0013] In this regard, directional terminology such as "above," "below," "below," "front," "back," "rear," "leading," "trailing," "over," etc., may be used with reference to the orientation of the described figures. Because portions of embodiments may be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0014] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided for purposes of illustration and is not intended to be limiting of the invention. For example, features illustrated or described as part of one embodiment may be used on or in conjunction with other embodiments to yield yet another embodiment. It is intended that the present invention include such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only.For the sake of clarity, the same elements or manufacturing steps in the different drawings have been designated by the same reference numerals unless otherwise indicated.

[0015] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may be, for example, the surface of a semiconductor wafer, die, or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, and the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0016] The term "vertical" as used in this specification is intended to describe an orientation that is substantially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / cube. For example, the extension direction Z mentioned below may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0017] In this specification, n-doped is referred to as the "first conductivity type," while p-doped is referred to as the "second conductivity type." Alternatively, opposite doping relationships can be used, so the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0018] In the context of the present description, the terms “in ohmic contact”, “in electrical contact”, “in ohmic connection” and “electrically connected” are intended to describe that there is a low-resistance electrical connection or a low-resistance current path between two regions, sections, zones, portions or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or metallization or electrode and a portion or part of a semiconductor device, where “low-resistance” may mean that the properties of the respective contact are substantially unaffected by the ohmic resistance. Furthermore, in the context of the present description, the term “in contact” is intended to describe that there is a direct physical connection between two elements of the respective semiconductor device; e.g.it is possible that a transition between two elements that are in contact with each other does not involve any further intermediate element or the like.

[0019] Additionally, in the context of the present description, the term "electrical isolation," unless otherwise stated, is used in the context of its generally accepted understanding and is thus intended to describe that two or more components are positioned separately from each other and that there is no ohmic connection connecting these components. However, components that are electrically isolated from each other may nevertheless be coupled to each other, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled and / or electrostatically coupled (for example, in the case of a junction). To give an example, two electrodes of a capacitor may be electrically isolated from each other and simultaneously mechanically and capacitively coupled to each other, e.g., by means of insulation, e.g., a dielectric.

[0020] Specific embodiments described in this specification relate to, but are not limited to, a power semiconductor device that can be used within a power converter or a power supply. Thus, in one embodiment, such a power semiconductor device may be configured to carry a load current to be supplied to a load and / or provided by a power source, respectively. For example, the power semiconductor device may comprise one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell, a monolithically integrated transistor cell, e.g., a monolithically integrated IGBT or MOSFET cell, and / or derivatives thereof. Such diode / transistor cells may be integrated within a single chip.A plurality of such cells may form a cell array arranged within an active region of the power semiconductor device.

[0021] The term "off-state" of the power semiconductor device may refer to conditions when the power semiconductor device is in a state configured to block load current flow while an external voltage is applied. In particular, the power semiconductor device may be configured to block forward load current through the power semiconductor device while a forward voltage bias is applied. In comparison, the power semiconductor device may be configured to conduct the forward load current in a "conducting state" of the power semiconductor device while a forward voltage bias is applied. A transition between the off-state and the conducting state may be controlled by a control electrode or, in particular, a potential of the control electrode.Of course, the electrical properties can only be valid within a predetermined operating range of the external voltage and current density within the power semiconductor device. The term "forward-biased off-state" can therefore refer to conditions where the power semiconductor device is in the off-state while a forward bias voltage is applied.

[0022] The term "power semiconductor device" as used in this specification is intended to describe a single-chip power semiconductor device with high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor device is intended for high current, typically in the ampere range, e.g., up to several tens or hundreds of amperes, and / or high voltages, typically above 15 V, more typically 100 V and above, e.g., up to at least 400 V or even more, e.g., up to at least 3 kV or even up to 10 kV or more, depending on the particular application.

[0023] For example, the term “power semiconductor device” as used in this specification is not directed to logic semiconductor devices used, for example, for storing data, computing data, and / or other types of semiconductor-based data processing.

[0024] For example, the power semiconductor device described below may be a single semiconductor chip having, for example, a strip cell configuration (or a cell / needle cell configuration) and may be configured to be used as a power component in a low, medium, and / or high voltage application.

[0025] Fig. 1 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device 1 according to one or more embodiments. The power semiconductor device 1, also referred to herein as a "device," comprises, in a single chip, a semiconductor body 10 configured to conduct a load current between a first load terminal 11 on a first side 110 of the semiconductor body 10 and a second load terminal 12 on a second side 120 of the semiconductor body 10.

[0026] The first side 110 and the second side 120 may be arranged opposite each other. For example, the first side 110 is a front side of the device 1, and the second side 120 is a rear side of the device 1. Accordingly, the device 1 may have a vertical configuration, according to which the load current within the device 1 follows a path parallel to the vertical direction Z.

[0027] The device 1 further comprises a drift region 100 of a first conductivity type within the semiconductor body 10. Herein, the term "drift region" is used with the meaning typically associated with it by those skilled in the art of power semiconductor devices. For example, the vertical extension of the drift region 100 influences the voltage blocking capabilities of the device 1.

[0028] The device 1 further comprises trenches 14, 16 extending from the first side 110 to the second side 120, e.g., along the vertical direction Z. Each trench 14, 16 includes a trench electrode 141, 161 separated from the semiconductor body 10 by a trench insulator 142, 162.

[0029] The trenches may include first-type trenches 14, wherein each trench electrode 141 of the first-type trenches 14 is electrically isolated from the first load terminal 11 and configured to receive a control signal. For this purpose, according to one embodiment, each trench electrode 141 of the first-type trenches 14 is electrically connected to a control terminal (not illustrated) of the device 1. Herein, the first-type trenches 14 are also referred to as "control trenches" and the corresponding trench electrodes 141 as "control trench electrodes."

[0030] The trenches may further include second-type trenches 16, wherein each trench electrode 161 of the second-type trenches 16 is electrically connected to the first load terminal 11. Herein, the second-type trenches 16 are also referred to as "source trenches" and the corresponding trench electrodes 161 as "source trench electrodes."

[0031] The device 1 further comprises mesas 15, 18, which are laterally delimited by the trenches 14, 16. The mesas 15, 18 include mesas of the first type 18 and mesas of the second type 15.

[0032] For example, each first-type mesa 18 is laterally delimited by at least one of the control trenches 14. For example, each first-type mesa 18 is electrically connected to the first load terminal 11, e.g., by means of a respective first contact plug 111, as illustrated. Alternatively, a planar contact may be used. Each first-type mesa 18 may be configured for load current conduction. For example, each first-type mesa 18 comprises a semiconductor body region 102 of the second conductivity type electrically connected to the first load terminal 11 (e.g., through the first contact plug), and optionally a semiconductor source region 101 of the first conductivity type electrically connected to the first load terminal 11, wherein the semiconductor source region 101 is isolated from the drift region 100 by at least the semiconductor body region 102.The adjacent control trench electrode 141 may be configured to induce an inversion channel in the semiconductor body region 102 when exposed to a corresponding ON control signal. This process may place the device 1 in the forward conducting state. The adjacent control trench electrode 141 may be configured to turn off the inversion channel in the semiconductor body region 102 when exposed to a corresponding OFF control signal, which may place the device 1 in the forward blocking state.

[0033] A first body contact region 1021 and a second body contact region 1022 having an increased dopant concentration compared to the average dopant concentration of the body region 102 may be formed as subsections of the body region 102 and arranged in contact with the first contact plug 111.

[0034] The configuration of the second-type mesas 15 may be different compared to the configuration of the first-type mesas 18. For example, the second-type mesas 15 are not configured to conduct load current during nominal operating conditions of the device 1, which will be explained in more detail below.

[0035] The above-described features of the power semiconductor device 1 may enable the design of diverse trench mesa patterns on the first side 110. Such a pattern may include further trench types and / or further mesa types, e.g., floating trenches whose trench electrodes are not connected to a defined electrical potential, or second-type control trenches whose trench electrodes are connected to a different control terminal compared to the control trench electrodes 141 to implement a dual- or multi-gate configuration, and so on. Other mesa types may also be implemented, e.g., those with a different threshold voltage compared to the first-type mesa 18.The following description of the embodiments focuses on the trench mesa patterns using the first and second trenches 14, 16 and the first and second type mesas 15, 18, wherein the presence of further type trenches and / or further type mesas is not excluded unless explicitly stated.

[0036] The portion of the semiconductor body 10 adjacent to the second load terminal 12 on the second side 120 may be configured according to the designated characteristic of the device 1. For example, an emitter region 108 of the second conductivity type may be provided between the drift region 100 and the second load terminal 12 if the device 1 is to have an IGBT configuration. The emitter region 108 is arranged in contact with the second load terminal 12. Furthermore, a field stop region 107 of the first conductivity type may be provided between the drift region 100 and the second load terminal 12, wherein the field stop region 107 has a higher dopant concentration than the drift region 100. If the device 1 is to have a MOSFET configuration, the emitter region 108 is omitted, so that the field stop region 107 would be adjacent to the second load terminal 12.If the device 1 is to have an RC-IGBT configuration, the emitter region 108 may have subsections of the first conductivity type, as is known to those skilled in the art.

[0037] To minimize conduction and switching losses, a power semiconductor device (such as device 1 described above) can be designed with a comparatively small total vertical extension of the semiconductor body. When it is off, i.e., when switching from the on-state to the off-state, particularly in an overload situation where the on-state load current exceeds the rated load current, dynamically increased field strengths can arise. Such dynamically increased field strengths can be caused by the hole current flowing in the space charge region, which, due to the positive charge of the holes, leads to an increased space charge density compared to the static case. One possible consequence can be the occurrence of a so-called dynamic avalanche, in which many electron-hole pairs are generated by impact ionization.Then, when the device is turned off, it goes through unstable states during which load current filamentation can occur. With such load current filamentation, the load current density can be more than an order of magnitude higher than the average total current density. The device can then be destroyed, for example, by latch-up. The risk of such a latch-up increases with reduced device thickness.

[0038] Here, the overload situation typically occurs when the let-through load current is at least 150% or 200% of the rated load current of the device 1.

[0039] The embodiments described below have a feature for preventing the occurrence of dynamic avalanches.

[0040] For example, the device 1 further comprises semiconductor structures. Each semiconductor structure includes a series connection of a first region 151 of the first conductivity type, which is coupled to or formed by the drift region 100, a second region 152 of a second conductivity type, and a third region 153 of the first conductivity type, which is connected by at least one of a first ohmic resistor 1531 (cf., e.g., Fig. 1, resistance “Rn”) and a Zener diode 1533 (cf. e.g. Fig. 7) is coupled to the first load terminal 11. Accordingly, the semiconductor structures can be npn semiconductor structures.

[0041] Each first-type mesa 18 is configured to conduct load current, is electrically connected to the first load terminal 11, and is free of any semiconductor structures. The semiconductor structures are arranged in the second-type mesa 15.

[0042] In one embodiment, the semiconductor structures (cf. elements 151, 152, 153) are configured to inject electrons into the semiconductor body 10 during an overload situation in order to limit the strength of an electric field in the semiconductor body 10. It may further be provided that the semiconductor structures are configured not to inject a significant amount of electrons into the semiconductor body when the load current is equal to or less than the rated load current of the power semiconductor device 1, i.e., when no overload situation exists.

[0043] The integration of such structures, as described above, can result in electrons being injected through the structures during switching of the device 1 from the on-state to the off-state in the event of an overload situation, even during the turn-off of the inversion channel in the first-type mesensing region 18. These electrons at least partially compensate for the holes present in the space-charge region. Accordingly, the increase in field strengths is limited, and the risk of a dynamic avalanche is reduced.

[0044] In one embodiment, each mesa of the second type 15 is laterally bounded by at least one of the source trenches 16. Furthermore, as in Fig. 1, it can be ensured that each second-type mesa 15 is not laterally delimited by any of the control trenches 14. This means that the above-mentioned semiconductor structures contained in the second-type mesae are arranged at a comparatively large distance from the nearest control trench electrode 141.

[0045] For example, the semiconductor structures are only effective during the switching off of an overload current, but otherwise do not or not significantly influence the properties of the device 1.

[0046] The first region 151 may be formed by the portion of the drift region present within the second-type mesa 15. The first region 151 may act as an n-type collector. The second region 152 may form a p-type base of the semiconductor structure. The second region 152 may be arranged between the first region 151 and the third region 153. The third region 153 may act as an n-type emitter of the structure.

[0047] For example, each of the semiconductor structures has a vertical configuration according to which the series connection of the first region 151, the second region 152 and the third region 153 is made along a direction pointing from the second side 120 to the first side 110, as exemplified in Fig. 1. As described above, each of the first region 151, the second region 152, and the third region 153 of each semiconductor structure may be arranged within a respective one of the second-type mesa 15. In one embodiment, the third region 153 is arranged in contact with an insulation layer 19 disposed between the first load terminal 11 and the semiconductor body 10. At its upper surface, the second region 152 may adjoin a lower surface of the third region 153 to form a first pn junction. At its lower surface, the second region 152 may adjoin a upper surface of the first region 151 to form a second pn junction. For example, each of the first region 151, the second region 152, and the third region 153 has a respective width along the first lateral direction X that is identical to the width of the second-type mesa 15.Along the second lateral direction Y, the semiconductor structures, i.e., the respective first region 151, the respective second region 152, and the respective third region 153, may be patterned as described further below. The second regions 152 in the second-type meses 15 and the body regions 102 in the first-type meses 18 may be formed together, e.g., based on the same processing steps. Likewise, the third regions 153 in the second-type meses 15 and the source regions 101 in the first-type meses 18 may be formed together, e.g., based on the same processing steps.

[0048] With further reference to Fig. 1, in one embodiment, the second region 152 of at least one or each of the semiconductor structures is separated by at least one second ohmic resistor 1521 (see, e.g. Fig. 1, resistance “Rp”) is coupled to the first load terminal 11. In Fig. 1, both the first ohmic resistor 1531 and the second ohmic resistor 1521 are illustrated based on the circuit symbol for an ohmic resistor. In contrast to this schematic illustration, the resistors 1531, 1521 (and similar resistors mentioned below) may be integrated within the chip, e.g., at least partially between the first load terminal 11 and the semiconductor body 10, or e.g., within the semiconductor body 10. Various elements may be used to form and dimension the resistors 1531, 1521 (in terms of ohmic resistance). For example, both the first ohmic resistor 1531 and the second ohmic resistor 1521 are integrated within the individual chip and in proximity to the respective structure 151, 152, 153. For example,both the first ohmic resistor 1531 and the second ohmic resistor 1521 are completely or at least partially integrated within one or more of the mesas of the second type 15.

[0049] During turn-off of device 1, a significant portion of the load current flows as hole current to first side 110. A portion of this current flows into body region 102 and thus directly to first load terminal 11. The remainder of the hole current flows into second region 152 and further via second ohmic resistor 1521 to first load terminal 11. When the voltage drop across second ohmic resistor 1521 exceeds the diode threshold of the pn junction between third region 153 and second region 152, third region 153 begins to inject electrons. These electrons diffuse through second region 152 to drift region 100 and thus into the space charge region. There, the electrons flow to second side 120 in the region of high electric field strength. In the region of high electric field strength of the space charge region, electrons and holes flow at a speed close to their respective saturation speeds.Thus, their concentrations are roughly proportional to the respective current densities. The injected electron current thus leads to a negative contribution to the space charge density and at least partially compensates for the positive contribution made by the hole charge. Due to the reduced overall space charge density, a reduced electric field gradient and a correspondingly reduced maximum field strength are achieved.

[0050] Thus, with appropriate dimensioning of the first ohmic resistor 1531 and the second ohmic resistor 1521 (examples given below), the risk of a dynamic avalanche caused by impact ionization is reduced. The voltage between the second region 152 and the third region 153 depends only slightly (e.g., only logarithmically) on the injected electron current once an injection threshold is exceeded. Thus, the increase in the voltage drops across the first ohmic resistor 1531 and the second ohmic resistor 1521 is approximately equal to the increase in the corresponding currents. Therefore, the ratio of the ohmic resistance of the first ohmic resistor 1531 and the ohmic resistance of the second ohmic resistor 1521 also determines the ratio of the electron current to the increase in the hole current from the space charge zone into the second region 152.Thus, by dimensioning the ohmic resistance of the first ohmic resistor 1531 and the ohmic resistance of the second ohmic resistor 1521, the degree of charge compensation in the space charge zone can be adjusted.

[0051] With respect to the embodiments in which the third region 153 is coupled to the first load terminal 11 via at least the first ohmic resistor 1531, one or more of the following dimensioning rules (i) to (v) may apply: (i) The resistance Rn of the first ohmic resistor 1531 is within the range of 0.2 to 2 times the resistance Rp of the second ohmic resistor 1521. (ii) The resistance Rn of the first ohmic resistor 1531 is within the range of 40% to 100% of the resistance Rp of the second ohmic resistor 1521. (iii) The parallel connection of all second ohmic resistors 1521 has a product of active area times resistance, Rp*Aact, within the range of 1 mOhm cm 2 up to 0.1 Ohm cm 2 on. (iv) The parallel connection of all second ohmic resistors 1521 has a product of active area times resistance, Rp*Aact, within the range of 5 mOhm cm 2 up to 20 Ohm cm 2 on. (v) Dimensioning rules (iii) and (iv) can be applied in the case of device 1 with a nominal load current density in the range of 200 A / cm 2 be suitable. If the nominal current density jnom significantly exceeds 200 A / cm 2deviates, the values ​​specified in rules (iii) and (iv) should be scaled inversely proportional to the nominal current density. For example, Rp*Aact is then between 0.2 V / jnom and 20 V / jnom or between 1 V / jnom and 4 V / jnom. These values ​​apply at room temperature and may vary depending on the temperature, e.g., increasing slightly with higher temperatures.

[0052] With regard to the formation of the first ohmic resistor 1531 and the second ohmic resistor 1521, some examples will now be described with reference to the next figures. In general, the first ohmic resistor 1531 and the second ohmic resistor 1521 can be integrated into the chip near the associated semiconductor structure 151, 152, 153. For a large number of semiconductor structures 151, 152, 153, a correspondingly large number of distributed resistor structures based on the first ohmic resistors 1531 and the second ohmic resistors 1521 can also be provided.

[0053] One possibility to integrate the first ohmic resistors 1531 and the second ohmic resistors 1521 is to use the polysilicon filling of adjacent trenches and to arrange the resistors in the third dimension (i.e., along the second lateral direction Y). An example of such a variant is shown in the Fig. 2 and Fig. 3, to which reference is now made. There, second contact plugs 112 are used to electrically connect the source trench electrodes 161 to the first load terminal 11. As shown in Fig. As shown in Figure 2, the semiconductor structure 151, 152, 153 in the mesa of the second type 15 is structured laterally along the second lateral direction Y by partially omitting the third region 153 along the second lateral direction Y, resulting in the second region 152 being adjacent to the insulation layer 19 in the case of omission. As a result, both the second region 152 and the third region 153 can be ohmically coupled to the first load terminal 11, e.g., as follows:

[0054] As exemplified in the Fig. 2 and Fig. As shown in Figure 3, a first contact bridge 114 may be arranged between the insulation layer 19 and the trench insulator 162 of the source trench 16, such that the first contact bridge 114 connects the third region 153 to the source trench electrode 161, which is electrically connected to the first load terminal 11. As a result, the first ohmic resistor 1531 is formed between the third region 153 and the first load terminal 11.

[0055] Similarly, a second contact bridge 113 may be arranged between the insulation layer 19 and the trench insulator 162 of another of the source trenches 16, such that the second contact bridge 113 connects the second region 152 to the source trench electrode 161 of the other source trench 16, which is electrically connected to the first load terminal 11. This forms the second ohmic resistor 1521 between the second region 152 and the first load terminal 11.

[0056] Accordingly, to dimension the resistance of the first ohmic resistor 1531 and the resistance of the second ohmic resistor 1521, the resistance of the source trench electrode 161 (which is based, for example, on polysilicon filling) can be adjusted.

[0057] Instead of the second contact bridges 113, the second region 152 may be electrically coupled to the first load terminal 11 based on third contact plugs 115, as shown in Fig. 4. For example, the third contact plugs 115 may be configured dimensionally similar to the first contact plugs 114 used to electrically connect the first-type resistors 18 to the first load terminal, but with a higher resistance to form the second resistors 1521. In one embodiment, the third region 153 may also be contacted based on such contact plugs instead of based on the first contact bridges 114.

[0058] Fig. 5 illustrates a vertical cross-section of another embodiment. For example, a second body region 102' of the second conductivity type is arranged in a third-type mesa 15'. The second body region 102' may comprise a highly doped portion 1021'. The third-type mesa 15' is arranged separately from the second-type mesa 15. For example, the mesae 15 and 15' are separated from each other by a third-type trench 17 including a trench electrode 171 insulated from the semiconductor body 10 by a trench insulator 172. The third region 153 is electrically connected to the trench electrode 171 of the third-type trench 17 via a third contact bridge 117. The second body region 102' or its optional highly doped subsection 1021' is electrically connected to the trench electrode 171 of the third type trench 17 via a fourth contact bridge 118.The trench electrode 171 of the third-type trench 17 may or may not be connected to the first load terminal 11 via a separate contact plug. Furthermore, the second body region 102' or its optional highly doped subsection 1021' is electrically connected to the first load terminal 11, e.g., via a fourth contact plug 116, according to one embodiment. Accordingly, in one example, the first ohmic resistance 1531 (Rn) may be formed based on the third contact bridge 117, the trench electrode 171 of the third-type trench 17, the fourth contact bridge 118, and the second body region 102'.

[0059] Fig. Figure 6(A) illustrates a horizontal projection similar to that shown in Fig. 5, wherein the left part of the trench mesa pattern of Fig. 5 is mirrored at a vertical central axis of the mesa of the third type 15'.

[0060] It is noted that for dimensioning the resistance of the first ohmic resistor 1531 and the resistance of the second ohmic resistor 1521, the resistance of the third region 153 and the resistance of the second region 152 may also be taken into account, since these resistors contribute to the total resistance of the first ohmic resistor 1531 and the total resistance of the second ohmic resistor 1521 according to one embodiment.

[0061] Fig. Figure 6(B) illustrates a variant of the embodiment of Fig. 6(A), wherein common contact bridges 114' are used to connect the respective regions. For example, some of the common contact bridges 114' contact the third regions 153 of the two second-type meses 15, the trench electrodes 171 of the two third-type trenches 17, and the second body region 102' or its optional highly doped portion 1021', respectively. Others of the common contact bridges 114' contact one of the second regions 152 and one of the source trench electrodes 161.

[0062] Fig. Figure 6(B) also illustrates that the division of the structures in the mesas of the first type 18 in the second lateral direction Y may be different from the division of the structures in the mesas of the second type 15.

[0063] Fig. Figure 6(C) illustrates a further variant of the embodiment of Fig. 6(A), wherein a different lateral structure of the third regions 153 and the second regions 152 is proposed in the second type mesas 15. Accordingly, the total lateral extent of the second region 152 along the second lateral direction Y is reduced, and the total lateral extent of the third region 153 along the second lateral direction Y is increased accordingly.

[0064] It is emphasized here that both the structure of the semiconductor regions in the mesas of the second type 15 and the contacting scheme for the mesas of the second type 15 are independent of the structure of the semiconductor regions in the mesas of the first type 18 and the contacting scheme for the mesas of the first type 18, respectively, according to one embodiment.

[0065] According to the Fig. 7, the third region 153 is coupled to the first load terminal 11 by a Zener diode 1533. Except for the coupling of the third region 153 to the first load terminal 11, this and the embodiments described below can be used with respect to the Fig. 1 to Fig. 6 described embodiments, so reference is made to the above.

[0066] For example, with reference to both variants (A) and (B) of Fig. 7, an NPN transistor is integrated based on the third region 153 (acting as an n-type emitter), the second region 152 (acting as a p-type base), and the first region 151 (acting as an n-type collector), wherein the third region 153 is initially floating. Upon turning off an overcurrent in the device 1, the third region 153 emits electrons due to the breakdown of the Zener diode 1533 (also referred to as an avalanche diode). The breakdown of the Zener diode 1533 electrically connects the third region 153 to the first load terminal 11. Then, even if the control signal supplied to the control trench electrode 141 is an OFF signal for turning off the inversion channel in the body region 102, electrons are injected, resulting in a reduced risk of a dynamic avalanche, as described with respect to Fig. 1 explained in more detail.

[0067] In one embodiment, the breakdown voltage of the Zener diode 1533 is within the range of 3 V to 20 V, e.g., between 5 V and 10 V.

[0068] In an embodiment as in variant (B) of Fig. 7, the third region 153 is coupled to the first load terminal 11 based on a series connection of a third ohmic resistor 1534 and the Zener diode 1533.

[0069] Furthermore, the second region 152 may be connected to the first load terminal 11 based on the second ohmic resistor 1521, cf. Fig. 8, variants (A) and (B). As with regard to the Fig. 6(A) to Fig. 6(C), the third region 153 and the second region 152 in the second type mesa 15 may be structured laterally along the second lateral direction Y. Fig. Figure 8 illustrates different positions along the second lateral direction Y based on variants (A) and (B).

[0070] It is noted that, according to one embodiment, both the second regions 152 in the second-type meses 15 and the body regions 102 in the first-type meses 18 may be formed based on common processing steps. Accordingly, both the second regions 152 in the second-type meses 15 and the body regions 102 in the first-type meses 18 may have the same vertical extent. Furthermore, the second regions 152 may include highly doped subregions 1522 as body regions 102. Likewise, in one embodiment, both the third regions 153 in the second-type meses 15 and the source regions 101 in the first-type meses 18 may be formed based on common processing steps. Accordingly, both the third regions 153 in the second type meses 15 and the source regions 101 in the first type meses 18 may have the same vertical extension.

[0071] According to the Fig. 9, the second region 152 is indirectly connected to the first load terminal 11 via the second ohmic resistor 1521 and the third ohmic resistor 1534.

[0072] Fig. Figure 10 schematically illustrates a horizontal projection of an embodiment showing the Fig. 7(A), Fig. 7(B), Fig. 8(A), Fig. 8(B) and Fig. 9. The mesa of the second type 15, which is also Fig. 11 and including the semiconductor structure 151, 152, 153, is arranged between two source trenches 16, each of which is arranged adjacent to an adjacent one of the first-type mesas 18. Of course, this trench-mesa pattern is described by way of example; other trench-mesa patterns may be chosen.

[0073] As described above, for example with regard to the Fig. 6(A)-(C), the second contact plugs 112 electrically connect the source trench electrodes 161 to the first load terminal 11. The third contact plugs 115 electrically connect the second regions 152 (or their highly doped subregions 1522) to the first load terminal 11.

[0074] The Zener diode 1533 is formed, for example, based on a pn junction formed at a junction (along the second lateral direction Y) between the third region 153 and the highly doped subsection 1522 of the second region 152. The third ohmic resistor 1534 can be formed via a less doped region in the second-type mesa 15, e.g., based on the second region 152. The second region 152 can be connected to the first load terminal 11 via one of the third contact plugs 115, which extends into another highly doped subsection 1522 of the second region 152 or directly into the second region 152. The heavily doped subsection 1522 and the another highly doped subsection 1522 can together form a continuous region.

[0075] Fig. 11 shows the section of Fig. 10, which includes the second type mesa 15 and the adjacent source trenches 16. Fig. Figure 12 illustrates a vertical cross-section corresponding to the horizontal projection in Fig. 11. For example, two laterally shifted, highly doped subsections 1522 of the second region 152 are each contacted by one of the third contact plugs 115. Two further highly doped subsections 1522, which are arranged separately from these contacted, highly doped subsections 1522, border the first region 153. Again, it is noted that the respective two subsections 1522 (which are connected by the respective third ohmic resistors R3) can alternatively form a single, contiguous subsection 1522. In any case, the subsections 1522 are separated from one another based on the third region 153, wherein the third region 153 can overcompensate the subsections 1522.

[0076] The highly doped subsections 1522 of the second region 152 in the second type meses 15 can be formed based on an implantation processing step. The same or a different implantation processing step can be used to form the highly doped subsections of the body regions 102 in the first type meses 18. The implantation for the highly doped subsections 1522 can also reach the location of the first region 153 or a part thereof. In this case, the first region 153 can overcompensate the implantation there. This process can be used, for example, for a Fig. 15 described embodiment may be advantageous.

[0077] Based on Fig. 13, the Fig. 12 and additionally illustrates the path of a part of the load current, an exemplary function of the semiconductor structure in the mesa of the second type 15 will be explained:

[0078] During switching of the device 1 from the on-state to the on-state, a significant portion of the load current flows as hole current to the first side 110. Part of this current flows into the mesa of the second type 15 and there in the second region 152 (e.g., p-base region) laterally to the next third contact plug 115. The voltage drop across the second ohmic resistor 1521 (Rp) leads to an increase in the potential of the second region at point 1, for example, to approximately 10 V. There, the pn junction to the third region 153 (e.g., n-emitter region) is initially only slightly forward-biased, so that at point 2 in the third region 153, a potential of approximately 10 V (more precisely, slightly less, approximately 9.5 V) is also present. This potential is also present at point 3 in the third region 153, while in the adjacent highly doped section 1522 of the second region 152 the potential is lower (close to 0 V).At point 3, the pn junction of Zener diode 1533 is thus reverse-biased. When this voltage drop across the pn junction of Zener diode 1533 exceeds the breakdown voltage of Zener diode 1533, electron-hole pairs are generated at point 3. The generated electrons then flow in the third region 153 (n-emitter region) to point 2 and are injected there into the second region 152 (p-base region). These electrons then flow further into the space charge region and there, in the region of high electric field strength, to the second side 120. As explained above, in the region of high electric field strength of the space charge zone, electrons and holes flow at a rate close to their respective saturation rates. Thus, their concentrations are approximately proportional to the respective current densities.The injected electron current thus leads to a negative contribution to the space charge density and at least partially compensates for the positive contribution made by the hole charge. Due to the reduced total space charge density, a reduced electric field gradient and a correspondingly reduced maximum field strength are achieved.

[0079] With respect to the embodiments in which the third region 153 is coupled to the first load terminal 11 via at least the Zener diode 1533, one or more of the following dimensioning rules (vi) to (viii) may apply: (vi) The parallel connection of all second ohmic resistors 1521 has a product of active area times resistance, Rp*Aact, of at least 10 mOhm cm 2 or at least 0.1 Ohm cm 2 on. (vii) The parallel connection of all third ohmic resistors 1534 has a product of active area times resistance, R3*Aact, within the range of 0.2 mOhm cm 2 up to 100 mOhm cm 2 or within the range of 1 mOhm cm 2 up to 10 mOhm cm 2 on. (viii) Dimensioning rules (vi) and (vii) can be applied in the case of device 1 with a nominal load current density in the range of 200 A / cm 2 be suitable. If the nominal current density jnom significantly exceeds 200 A / cm 2 deviates, the values ​​specified in rules (vi) and (vii) should be scaled inversely to the nominal current density. For example, Rp*Aact is then at least 2 V / jnom or at least 20 V / jnom. And R3 - Aact is then between 0.04 V / jnom and 20 V / jnom or between 0.2 V / jnom and 2 V / jnom. These values ​​apply at room temperature and may vary depending on the temperature, e.g., increasing slightly with higher temperatures.

[0080] With regard to the formation of the third ohmic resistor 1534 (R3) and the second ohmic resistor 1521 (Rp) (when provided in an embodiment in which the third region 153 is coupled to the first load terminal 11 via at least the Zener diode 1533), some examples will now be described with reference to the next figures.

[0081] As explained above, in one embodiment, a significant portion of the total resistance of the third ohmic resistor 1534 is formed by the second region 152 and / or by one or more of the highly doped sub-sections 1522 of the second region 152, the latter being a variant of the Fig. 11 and Fig. 12 illustrated embodiment in the Fig. 14 and Fig. 15, wherein the highly doped subsections 1522 continuously couple the third region 153 to the third contact plugs 115. As explained above, the third region 153 (of the first conductivity type) may overcompensate the subsections 1522 (of the second conductivity type). To achieve this effect, the third region 153 may, in one embodiment and as shown in Fig. 15 illustrates extending further along the vertical direction Z than the subsections 1522 of the second region 152. For example, such a configuration may provide advantages with respect to the fabrication of the device 1, since, for example, the highly doped subsections 1522 may be implanted without using a mask before the third region 153 is implanted with a mask. Additionally or alternatively, the lateral extension of the regions 1522 and 153 may be selected such that the third region 153 (of the first conductivity type) overcompensates for the subsections 1522 (of the second conductivity type) in an overlapping region.

[0082] Another variant is in the Fig. 18- Fig. 19. There, the path between the highly doped subsection 1522 contacted by the third contact plug 115 and the highly doped subsection 1522 contacted by the third region 153 includes a further region 1538 of the first conductivity type. The further region 1538 of the first conductivity type may be a floating region. The further region 1538 of the first conductivity type may have the same dopant concentration as the third region 153, but a smaller total lateral extent along the second lateral direction Y, which may be, for example, less than half the total lateral extent of the third region 153 along the second lateral direction Y, for example to prevent the further region 1538 of the first conductivity type from acting as an emitter region.The further region 1538 of the first conductivity type can overcompensate the subsections 1522 (of the second conductivity type), for example such that the third ohmic resistor 1534 consists only of a part of the second region 152 below the further region 1538 of the first conductivity and thus has a correspondingly increased resistance value.

[0083] The third region 153 may be arranged in contact with the adjacent two highly doped sections 1522 (as shown, for example, in the Fig. 12 and Fig. 13) or spaced apart from it (as in the Fig. 16 and Fig. 17). The breakdown voltage of the Zener diode 1533 can be influenced by the (possible) distance between the third region 153 and the highly doped section 1522 adjacent to the third region 153.

[0084] In one embodiment, the total extension of the region corresponding to the third ohmic resistor 1534 (for example, the further region 1538 of the first conductivity type or the distance between the highly doped subsections 1522) is within the range of 0.5 µm to 20 µm. Furthermore, the total extension of the third region 153 may be within the range of 5 µm to 100 µm. The exact values ​​can be selected depending on the designated resistance R3 of the third ohmic resistor 1534 and the designated resistance Rp of the second ohmic resistor 1521.

[0085] The above-presented embodiments of including the semiconductor structures 151, 152, 153 in the mesas of the second type 15 can be used in devices in which the emitter region 108 is laterally structured on the second side 120, as in Fig. 20 shown.

[0086] For example, the emitter region 108 includes one or more first subregions 1081 and one or more second subregions 1082 that differ in average dopant concentration and / or emitter efficiency. The difference in the dopant concentrations of the emitter region 108 at the second side 120 may be reflected by a corresponding change in the dimensioning of the breakdown voltage of the Zener diode 1533 and / or the resistance of the third ohmic resistor 1534 and / or the resistance of the second ohmic resistor 1521. For example, in a region laterally overlapping with an increased emitter efficiency (e.g., the first subregion 1081), the resistance R3 of the third ohmic resistor 1534 is higher compared to a region laterally overlapping with a decreased emitter efficiency (e.g., the second subregion 1082).

[0087] As in the Fig. 21- Fig. 22, for example, due to higher current densities during turn-off in the region near the junction termination, the semiconductor structures 151, 152, 153 may be arranged exclusively in or near an edge termination region 1-3 surrounding an active region 1-2 (which includes a cell array comprising in particular the first type meses 18 and the control trenches 14), cf. Fig. 21, or in both the active area 1-2 and the edge termination area 1-3, cf. Fig. 22. For example, with reference to Fig. 21, the semiconductor structure 151, 152, 153 is not necessarily arranged in one of the mesas of the second type 15, but adjacent to one of the source trenches 16 at a junction between the active region 1-2 and the edge termination region 1-3. There, the second region 152 can laterally adjoin a well region 13 of the second conductivity type. On the other hand, a region of the second conductivity type 159, e.g., a so-called p-ring, adjacent to the second region 152 can be laterally connected to the first load terminal 11 via one or more further contact plugs 119. In another embodiment, as shown in Fig. 22, the semiconductor structure 151, 152, 153 is arranged in one of the mesas of the second type 15 in the edge termination region 1-3. The third ohmic resistor 1534 can be connected via a (in the Fig. 21- Fig. 22) which is arranged, for example, in the rightmost mesa 15, may be connected to the first load terminal 11.

[0088] If the device 1 is implemented as an RC-IGBT, the semiconductor structures 151, 152, 153 may be arranged both in the IGBT region of the RC-IGBT and in the diode region of the RC-IGBT. For example, with reference to Fig. 23, the emitter region 108 has one or more first sections 1083 and one or more second sections 1084 that differ in dopant type. For example, the one or more first sections 1083 are part of the IGBT region and thus of the second conductivity type. The one or more second sections 1084 are part of the diode region and thus of the first conductivity type. The difference in the dopant type of the emitter region 108 on the second side 120 can be reflected by a corresponding change in the dimensioning of the breakdown voltage of the Zener diode 1533 and / or the resistance of the third ohmic resistor 1534.For example, in a region that is part of the diode region (later overlapping with the one or more second sections 1084), the resistance R3 of the third ohmic resistor 1534 is higher or lower compared to a region that is part of the IGBT region (later overlapping with the one or more first sections 1084), since the current density in the diode region may differ from the current density in the IGBT region.

[0089] The device 1 can also be designed as a diode, cf. Fig. 24, wherein the emitter region 108 is entirely of the first conductivity type. Then, no source region 101 is included in the first-type mesas 18. If implemented as a diode, the device 1 can be provided without trench electrodes.

[0090] Fig. Figure 25 illustrates three variants (A) to (C) of the embodiment of Fig.9. According to these variants, the device 1 further comprises a barrier region 105 of the first conductivity type. The barrier region 105 has a larger dopant concentration compared to the drift region. In one embodiment, cf. variant (A), the barrier region 105 is arranged in both the first type meses 18 and the second type meses 15. There, it may be arranged in contact with the body region 102 and the second region 152 or, as illustrated, spaced therefrom along the vertical direction Z. A bottom surface of the barrier region 105 may still be arranged within the meses 15, 18; i.e., the barrier region 105 does not extend below the bottoms of the trenches 14, 16 in one example. Furthermore, the barrier region 105 may be laterally structured, e.g. B. by extending only into the meses of the first type 18 (variant (B)) or only into the meses of the second type 15 (variant (C)).

[0091] Furthermore, in another embodiment, such structures may be implemented in regions where the local doping of the backside emitter is enhanced, which may be the case, for example, to improve the softness of the device or to improve the current-induced short-circuit strength.

[0092] Also presented herein is a method for manufacturing a power semiconductor device. The method includes forming the following components in a single chip: a semiconductor body configured to conduct a load current between a first load terminal on a first side of the semiconductor body and a second load terminal on a second side of the semiconductor body; a drift region of a first conductivity type within the semiconductor body; trenches extending from the first side to the second side, each trench including a trench electrode separated from the semiconductor body by a trench insulator; meses laterally bounded by the trenches, the meses including meses of the first type and meses of the second type; and semiconductor structures.Each semiconductor structure includes a series connection of a first region of the first conductivity type coupled to or formed by the drift region; a second region of a second conductivity type; and a third region of the first conductivity type coupled to the first load terminal through at least one of a first ohmic resistor and a Zener diode. Each mesa of the first type is configured for load current conduction, electrically connected to the first load terminal, and free of any of the semiconductor structures. The semiconductor structures are arranged in the mesa of the second type.

[0093] Embodiments of this manufacturing method correspond to the embodiments of the power semiconductor device 1 described above. Accordingly, these embodiments of the method are not described verbatim herein, but reference is made to the above. For example, as described, both the body regions 102 in the first-type meses 18 and the second regions 152 in the second-type meses 15 may be formed based on common processing steps. Likewise, both the source regions 101 in the first-type meses 18 and the third regions 153 in the second-type meses 15 may be formed based on common processing steps.

[0094] In the above, embodiments relating to power semiconductor devices and corresponding manufacturing methods have been explained.

[0095] For example, these power semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body and its regions / zones, e.g., regions, etc., may be a monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.

[0096] However, it is understood that the semiconductor body and its regions / zones may be made of any semiconductor material suitable for fabricating a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP) and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. to name.The above-mentioned semiconductor materials are also called "homojunction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SiC1-x), and silicon-SiGe heterojunction semiconductor materials. Currently, Si, SiC, GaAs, and GaN materials are mainly used for power semiconductor switching applications.

[0097] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used for convenience of description to explain the positioning of one element relative to a second element. These terms are intended to encompass various orientations of the respective device in addition to orientations other than those illustrated in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms may refer to like elements throughout the description.

Claims

[1] Power semiconductor device (1) comprising in a single chip: - a semiconductor body (10) configured to conduct a load current between a first load terminal (11) on a first side (110) of the semiconductor body (10) and a second load terminal (12) on a second side (120) of the semiconductor body (10); - a drift region (100) of a first conductivity type within the semiconductor body (10); - trenches (14, 16) extending from the first side (110) to the second side (120), each trench (14, 16) including a trench electrode (141, 161) separated from the semiconductor body (10) by a trench insulator (142, 162); - mesas (15, 18) which are laterally delimited by the trenches (14, 16), the mesas (15, 18) comprising mesas of the first type (18) and mesas of the second type (15); - semiconductor structures (151, 152, 153), each semiconductor structure comprising a series circuit of ◯ a first region (151) of the first conductivity type coupled to or formed by the drift region (100); ◯ a second region (152) of a second conductivity type; and ◯ a third region (153) of the first conductivity type coupled to the first load terminal (11) through at least one of a first ohmic resistor (1531; 1534) and a Zener diode (1533); wherein: - each mesa of the first type (18) is configured to conduct load current, is electrically connected to the first load terminal (11) and is free of any of the semiconductor structures (151, 152, 153); and - the semiconductor structures (151, 152, 153) are arranged in the mesas of the second type (15). [2] The power semiconductor device (1) according to claim 1, wherein the trenches include first type trenches (14), each trench electrode (141) of the first type trenches (14) being electrically isolated from the first load terminal (11) and configured to receive a control signal. [3] The power semiconductor device (1) according to claim 1 or 2, wherein the trenches include second type trenches (16), each trench electrode (161) of the second type trenches (16) being electrically connected to the first load terminal (11). [4] Power semiconductor device (1) according to claim 2 or 3, wherein: - each mesa of the first type (18) is laterally delimited by at least one of the trenches of the first type (14); and / or - each mesa of the second type (15) is laterally delimited by at least one of the trenches of the second type (16). [5] Power semiconductor device (1) according to one or more of the preceding claims 2 to 4, wherein each mesa of the second type (15) is not laterally delimited by any of the trenches of the first type (14). [6] Power semiconductor device (1) according to one or more of the preceding claims, wherein the semiconductor structures (151, 152, 153) are configured to inject electrons into the semiconductor body (10) during an overload situation in order to limit the strength of an electric field in the semiconductor body (10). [7] Power semiconductor device (1) according to one or more of the preceding claims, wherein the semiconductor structures (151, 152, 153) are configured not to inject a significant amount of electrons into the semiconductor body (10) when the load current is equal to or less than the rated load current of the power semiconductor device (1). [8] Power semiconductor device (1) according to one or more of the preceding claims, wherein the second region (152) of at least one or each of the semiconductor structures is coupled to the first load terminal (11) by at least one second ohmic resistor (1521). [9] The power semiconductor device (1) according to claim 8, wherein both the first ohmic resistor (1531) and the second ohmic resistor (1521) are integrated within the single chip and in the vicinity of the respective semiconductor structure (151, 152, 153). [10] Power semiconductor device (1) according to claim 8 or 9, wherein both the first ohmic resistors (1531) and the second ohmic resistors (1521) are at least partially integrated within the one or more of the mesas of the second type (15). [11] Power semiconductor device (1) according to one or more of the preceding claims, wherein each of the semiconductor structures has a vertical configuration according to which the series connection is made along a direction pointing from the second side (120) to the first side (110). [12] Power semiconductor device (1) according to one or more of the preceding claims, wherein each mesa of the first type (18) comprises a semiconductor body region (102) of the second conductivity type electrically connected to the first load terminal (11), and optionally a semiconductor source region (101) of the first conductivity type electrically connected to the first load terminal (11), wherein the semiconductor source region (101) is isolated from the drift region (100) by at least the semiconductor body region (102). [13] Power semiconductor device (1) according to one or more of the preceding claims, wherein each of the first region (151), the second region (152) and the third region (153) of each semiconductor structure is arranged in the mesas of the second type (18). [14] Power semiconductor device (1) according to claim 12 and 13, wherein the body regions (102) in the meses of the first type (15) and the second regions (152) in the meses of the second type (18) are manufactured together, and / or wherein the source regions (101) in the meses of the first type (15) and the third regions (153) in the meses of the second type (18) are manufactured together. [15] Power semiconductor device (1) according to one or more of the preceding claims, wherein the third region (153) is coupled to the first load terminal (11) via the Zener diode (1533) and a third ohmic resistor (1534). [16] Power semiconductor device (1) according to one or more of the preceding claims, wherein the second region (152) comprises one or more highly doped subsections (1522) of the second conductivity type. [17] Power semiconductor device (1) according to one or more of the preceding claims, wherein: - the third region (153) is arranged in contact with an insulating layer (19), wherein the insulating layer (19) is arranged between the first load terminal (11) and the semiconductor body (10); and - the second region (152) insulates the third region (153) from the remaining portion of the semiconductor body (10). [18] Power semiconductor device (1) according to claim 15 to 17, wherein the pn junction of the Zener diode (1533) is formed based on a junction between one of the highly doped subsections (1522) and the third region (153), and wherein the second region (152) is connected to the first load terminal (11). [19] Power semiconductor device (1) according to one or more of the preceding claims, wherein the power semiconductor device (1) is one of an IGBT, an RC-IGBT or a diode. [20] A method of manufacturing a power semiconductor device (1), the method comprising forming the following components in a single chip: - a semiconductor body (10) configured to conduct a load current between a first load terminal (11) on a first side (110) of the semiconductor body (10) and a second load terminal (12) on a second side (120) of the semiconductor body (10); - a drift region (100) of a first conductivity type within the semiconductor body (10); - trenches (14, 16) extending from the first side (110) to the second side (120), each trench (14, 16) including a trench electrode (141, 161) separated from the semiconductor body (10) by a trench insulator (142, 162); - mesas (15; 18) which are laterally delimited by the trenches (14, 16), the mesas (15; 18) comprising mesas of the first type (18) and mesas of the second type (15); - semiconductor structures (151, 152, 153), each semiconductor structure comprising a series circuit of ◯ a first region (151) of the first conductivity type coupled to or formed by the drift region (100); ◯ a second region (152) of a second conductivity type; and ◯ a third region (153) of the first conductivity type coupled to the first load terminal (11) through at least one of a first ohmic resistor (1531; 1534) and a Zener diode (1533); wherein: - each mesa (18) of the first type is configured to conduct load current, is electrically connected to the first load terminal (11) and is free of any of the semiconductor structures (151, 152, 153); and - the semiconductor structures (151, 152, 153) are arranged in the mesas of the second type (15).

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