TRANSISTORBAUELEMENT

Abstract

A transistor component is revealed.

Description

[0001] This disclosure relates generally to a transistor device, in particular to a superjunction transistor device.

[0002] A superjunction transistor device may comprise multiple transistor cells, each comprising a gate electrode, a source region, a body region adjacent to the gate electrode and dielectrically isolated from the gate electrode by a gate dielectric, and a drift region adjacent to the body region. In an on-state (conductive state) of the transistor device, there is a conductive channel in the body region along the gate dielectric. In the off-state, the conductive channel is interrupted. The source region, the adjacent body region, and the drift region form a parasitic bipolar transistor, with the body region forming the base of the parasitic transistor.

[0003] During operation of the transistor device, operating scenarios may occur in which charge carriers are injected into the body region, which can cause the parasitic bipolar transistor to turn on, leaving the transistor device in an uncontrolled on state for at least a certain period of time. This is highly undesirable.

[0004] US 2020 / 0 388 703 A1 describes a transistor component with a plurality of transistor cells, each having a body region, a gate electrode dielectrically insulated from the body region by a gate electrode, and at least one body contact region contacted by a contact electrode. The distance between the contact electrode and a gate dielectric is between 100 nm and 400 nm.

[0005] US 2010 / 0 090 274 ​​A1 describes a transistor component with a plurality of transistor cells, each having a body region, a gate electrode dielectrically insulated from the body region by a gate electrode, and a body contact region contacted by a contact electrode.

[0006] An embodiment of the invention relates to a transistor component according to claim 1.

[0007] A further embodiment of the invention relates to a transistor component according to claim 14.

[0008] Examples are explained below with reference to the drawings. The drawings are intended to illustrate certain principles, so only aspects necessary for understanding those principles are shown. The drawings are not to scale. Throughout the drawings, like reference numerals indicate like features. Fig. 1 schematically illustrates a vertical cross-sectional view of a portion of a transistor device comprising a plurality of transistor cells; Fig. 2 and Fig. 3 illustrate horizontal cross-sectional views of the Fig. 1 shown transistor component in different horizontal sectional planes; Fig. 4 to 7 illustrate detailed views of transistor cells according to various examples; Fig. 8A to 8C illustrate an example of a method for forming contact regions and contact vias of the transistor cells; Fig. 9A to 9C illustrate another example of a method for forming contact regions and contact vias of the transistor cells; Fig. 10A to 10C illustrate yet another example of a method for forming contact regions and contact vias of the transistor cells; and Fig. 11A to 11B illustrate top views of the transistor device according to various examples.

[0009] In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and, for the purpose of illustration, show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with one another, unless expressly stated otherwise.

[0010] Fig. Figure 1 schematically illustrates a portion of a transistor device comprising a plurality of transistor cells 10. In particular, Fig. 1 a vertical cross-sectional view of a portion of a semiconductor body 100 of the transistor device in which the transistor cells 10 are integrated.

[0011] The semiconductor body 100 comprises a monocrystalline semiconductor material. The semiconductor material is, for example, silicon (Si) or silicon carbide (SiC).

[0012] Referring to Fig. 1, each transistor cell 10 comprises a source region 11 of a first doping type, a body region 12 of a second doping type complementary to the first doping type, and a gate electrode 21. The gate electrode 21 is adjacent to the body region 12, is dielectrically insulated from the body region 12 by a gate dielectric 22, and is arranged in a gate trench 120 extending from a first surface 101 of the semiconductor body 100 into the semiconductor body 100. Referring to Fig. 1, source and body regions 11, 12 of two adjacent transistor cells may be arranged in a mesa region between adjacent gate trenches 120. In this example, the body regions 12 of the two adjacent transistor cells 10 may be formed by a contiguous doped region of the second doping type. Furthermore, gate electrodes 21 of two (other) adjacent transistor cells may be formed by a contiguous electrode arranged in a gate trench 120.

[0013] The gate electrodes 21 comprise an electrically conductive material. Examples of the electrically conductive material include doped polysilicon or a metal such as tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), or the like. The gate dielectrics 22 comprise, for example, an oxide. According to one example, the oxide is silicon oxide (SiO2).

[0014] The transistor device further comprises a source electrode 41 electrically connected to the source and body regions 11, 12 of the transistor cells 10. Connections between the source electrode 41 and the source and body regions 11, 12 are shown in Fig. 1 is only shown schematically. Detailed examples for connecting the source electrode 41 to the source and body regions 11, 12 are explained further below. The source electrode comprises an electrically conductive material such as aluminum (Al), copper (Cu), or an aluminum-copper alloy (AlCu).

[0015] The source electrode 41 is separated from the semiconductor body 100 by an insulating layer 5. The insulating layer 5 comprises an electrically insulating material such as an oxide, a nitride, or the like.

[0016] Referring to Fig. 1, the transistor component further comprises a drain region 13 of the first doping type, drift regions 14 of the first doping type, compensation regions 15 of the second doping type, and a buffer region 16. The buffer region 16 is of the first doping type and is arranged between the drain region 13 and the drift and compensation regions 14, 15. According to one example, the buffer region 16 has a lower doping concentration than the drain region 13 and a higher doping concentration than the drift and compensation regions 14, 15.

[0017] The transistor component according to Fig. 1, which comprises drift regions 14 of the first doping type and compensation regions 15 of the second doping type, is a superjunction transistor component.

[0018] As explained further below, the transistor component can be operated in an on-state or an off-state. In the on-state, there are conductive channels in the body regions 12 along the gate dielectrics between the source regions 11 and the drift regions 14. For this purpose, the drift regions 14 each border the gate dielectric 22 and the body region 12 of at least one of the transistor cells 10. The compensation regions 15 are each adjacent to at least one of the drift regions 15 and are connected to the source electrode 41. In the Fig. 1, the compensation regions 15 each border on the body region 12 of at least one transistor cell and are connected to the source electrode 41 via the respective body region 12.

[0019] The transistor component according to Fig. 1 is a vertical transistor device. In this example, the drain region 13 is spaced apart from the source and body regions 11, 12 of the transistor cells 10 in a vertical direction z of the semiconductor body 100. The vertical direction z is substantially perpendicular to the first surface 101. According to one example, the drain region 13 adjoins a second surface 102 opposite the first surface 101 of the semiconductor body 100.

[0020] The drain region 13 forms a drain node D or is connected to a drain node D of the transistor component. The source electrode 41 forms a source node S or is connected to a source node S of the transistor component. Furthermore, the gate electrodes 21 are connected to a gate node (not shown) of the transistor component.

[0021] Referring to Fig. 1, the gate trenches with the gate electrodes 21 are spaced apart from each other in a first lateral direction x of the semiconductor body 100. The first lateral direction x is perpendicular to the vertical direction z. According to one example, the gate electrodes 21 are implemented as strip electrodes (elongated electrodes). In this example, the gate electrodes 21 are elongated in a second lateral direction y perpendicular to the first lateral direction x.

[0022] An example of elongated gate electrodes 21 is shown in Fig. 2, which illustrates a portion of the semiconductor body 100 in a first horizontal sectional plane AA intersecting the gate trenches 120 with the gate electrodes 21 and the gate dielectrics 22.

[0023] Referring to Fig. 1, the drift regions 14 are spaced apart from one another in the first lateral direction x and a compensation region 15 is arranged between two adjacent drift regions 14.

[0024] Fig. 3 illustrates a section of the semiconductor body 100 in a second horizontal sectional plane BB, which intersects the drift and compensation regions 14, 15. According to the Fig. In the example shown in Figure 3, the drift regions 14 and the compensation regions 15 are elongated regions with a longitudinal direction corresponding to the second lateral direction y. In this example, the drift and compensation regions 14, 15 are substantially parallel to the gate trenches 120. However, this is only an example.

[0025] According to another example (not shown), longitudinal directions of the drift and compensation regions 14, 15 are perpendicular to the longitudinal directions of the gate trenches 120. In this example, the drift regions 14 are spaced apart from each other in the second longitudinal direction y and are elongated in the first lateral direction x.

[0026] The transistor device can be operated in a conventional manner by applying a drive voltage (gate-source voltage) between the gate electrodes 21 and the source electrode 41. The transistor device is in the on-state (conductive state) when the drive voltage is such that conductive channels are created in the body regions 12 along the gate dielectrics 22 between the source regions 11 and the drift regions 14. The transistor device is in the off-state (blocking state) when the electrically conductive channels are interrupted.

[0027] The transistor device can be implemented as an N-type transistor device or as a P-type transistor device. For example, an N-type transistor device is in the on state when the drive voltage is higher than a predefined positive threshold voltage and in the off state when the drive voltage is below the threshold voltage.

[0028] In an N-type transistor device, the doped regions of the first doping type are N-type regions, and the doped regions of the second doping type are P-type regions. In a P-type transistor device, the doped regions of the first doping type are P-type regions, and the doped regions of the second doping type are N-type regions.

[0029] The source regions 11, the body regions 12, the drift and compensation regions 14, 15, the buffer region 16, and the drain region 13 can also be referred to as active device regions. For an N-type transistor component, doping concentrations of the active device regions are selected, for example, from the following ranges: Source area 11: 5E19 cm -3 - 5E20 cm -3 Body area 12: 3E19 cm -3 - 3E20 cm -3 Drainage area 13: 5E18 cm -3 - 5E20 cm -3 Drift area 14: 7E15 cm -3 - 7E16 cm-3 Compensation area 15: 7E15 cm -3 - 7E16 cm -3 Buffer area 16: 5E15 cm -3- - 5E16 cm -3- Body contact area 17: 1E20 cm -3 - 1E21 cm -3

[0030] The transistor device can be operated in a forward operating state or a reverse operating state. The transistor device is in the forward operating state when a voltage is applied between the drain node D and the source node S, reverse-biasing the PN junctions between the drift regions 14 and the body regions 12. For example, an N-type transistor device is in the forward operating state when a positive voltage is applied between the drain node D and the source node S, and in the reverse operating state when a negative voltage is applied between the drain node D and the source node S.

[0031] When the transistor device is in the on-state and in the forward operating state, charge carriers of the first type flow from the source regions 11 via the conductive channels along the gate dielectrics 22, the drift regions 14 and the buffer region 16 to the drain region 13. In an N-type transistor device, the charge carriers of the first type are, for example, electrons.

[0032] When the transistor device is in the off-state and forward-biased state, the conductive channels along the gate dielectrics 22 are interrupted, and the PN junctions between the body regions 12 and the drift regions 14 are reverse-biased. In this operating state, a charge carrier flow between the source regions 11 and the drain region 13 is interrupted as long as a voltage applied between the drain and source nodes D, S is lower than a voltage-blocking capability of the transistor device. If the voltage applied between the drain and source nodes D, S is higher than the voltage-blocking capability, an avalanche breakdown may occur, causing an avalanche current to flow between the source regions 11 and the drain region 13. An operating state of the transistor device in which an avalanche current flows is referred to below as avalanche operation.

[0033] In the reverse operating state, the PN junctions between the drift regions 14 and the body regions 12 are forward-biased, so that the transistor component conducts regardless of whether or not conductive channels are created along the gate dielectrics 22 by applying a suitable drive voltage. For example, an N-type transistor component is in the reverse operating state when a positive voltage is applied between the source node S and the drain node D.

[0034] When the transistor device is in the on state (so that there are conductive channels along the gate dielectrics 22) and in the reverse operating state, a current flowing between the source and drain regions 12, 13 is essentially a unipolar current. A unipolar current is a current that essentially comprises only majority charge carriers, which are charge carriers of the first type.

[0035] When the transistor device is in the off state (so that conductive channels along the gate dielectrics 22 are interrupted), the current flowing between the source and drain regions 12, 13 is a bipolar current. A bipolar current comprises charge carriers of the first type and charge carriers of the second type. In an N-type transistor device, charge carriers of the first type are electrons, and charge carriers of the second type are holes. The operating state of the transistor device in which a bipolar current flows is referred to below as diode operation. The charge carriers of the second type are minority charge carriers in the transistor device.

[0036] In each transistor cell 10, the source region 11, the body region 12, and the drift region 14 adjacent to the body region 12 form a parasitic bipolar transistor. Particularly when the transistor device is in avalanche mode or when the transistor device is in diode mode, charge carriers of the second type can be injected into the body regions 12. These charge carriers can cause the parasitic bipolar transistor to turn on. This is highly undesirable, as it would cause the transistor device to conduct uncontrollably.

[0037] Fig. 4 to 7 illustrate various examples for implementing the transistor device such that the risk of turning on the parasitic bipolar transistor is significantly reduced. Fig. 4 to 7 each show a vertical cross-sectional view of a portion of the semiconductor body 100 comprising two adjacent transistor cells 10. In particular, the Fig. 4 to 7 each show a mesa region between two adjacent gate trenches 120, sections of the adjacent gate trenches 120 with the gate electrodes 21 and the gate dielectrics 22 and sections of the drift and compensation regions 14, 15 which adjoin the body region 12 of the two transistor cells 10.

[0038] Referring to the Fig. 4 to 7, each of the transistor cells 10 comprises a body contact region 17 of the second doping type, which is electrically connected to the source electrode 41 via an electrically conductive via 42. The body contact region 17 adjoins the body region 12, so that the body region 12 is electrically connected to the source electrode 41 via the body contact region 17 and the electrically conductive via 42. A doping concentration of the body contact region 17 is higher than a doping concentration of the body region 12 and high enough to establish contact between the electrically conductive via 42 and the body contact region 17.

[0039] The electrically conductive via 42 comprises an electrically conductive material such as tungsten (W), titanium (Ti) or the like.

[0040] The via 42 is also connected to the source region 11 of the respective transistor cell 10, so that the source region 11 is connected to the source electrode 41 through the electrically conductive via 42.

[0041] In each transistor cell 10, the body contact region 17 not only serves to connect the body region 12 to the via 42 and the source electrode 41, but also serves to collect charge carriers of the second type that may be injected into the body region 12 to prevent these second-type charge carriers from turning on the parasitic bipolar transistor. To achieve high efficiency of the body contact region 17 in collecting the minority charge carriers, the body contact region 17 is arranged close to the respective gate dielectric 22. This includes a distance d4 (see Figures 1 and 5) between the body contact region 17 and the respective gate dielectric 22 being less than 300 nanometers.

[0042] According to one example, the distance d4 between the body contact region 17 and the respective gate dielectric 22 is more than 150 nanometers.

[0043] Arranging the body contact region 17 near the gate dielectric 22 prevents minority charge carriers from moving along the gate dielectric 22 to the source region 11. Minority charge carriers moving along the gate dielectric 22 to the source region 11 can cause a voltage drop, which can cause the parasitic bipolar transistor to turn on. Thus, collecting these minority charge carriers by the body contact region 17 can help prevent the parasitic bipolar transistor from turning on.

[0044] Referring to the Fig. 4 to 7, the body contact regions 17 may be spaced apart from the source regions 11 in the vertical direction z. However, this is only an example. According to a further example (not shown), the body contact region 17 of a transistor cell 10 borders both the body region 12 and the source region 11 of the respective transistor cell 10.

[0045] According to a Fig. 4, the two transistor cells 10, whose body and source regions 11, 12 are arranged in a common mesa region between two adjacent gate trenches 120, each comprise a body contact region 17 and a respective via 42, wherein the two body contact regions 17 and the vias 42 are spaced apart from one another in the first lateral direction x.

[0046] According to another in Fig. In the example shown in Figure 5, the two transistor cells 10, whose body and source regions 11, 12 are arranged in a common mesa region between two adjacent gate trenches 120, share a body contact region 17 and a respective via 42.

[0047] Referring to the Fig. 4-7, the source regions 11 of the two adjacent transistor cells 10 that share the mesa region are spaced apart from each other in the first lateral direction x. In the Fig. 4, in which each of the transistor cells 10 has its own body contact region 17 and the respective via 42, each of the source regions 11 can be implemented such that it does not extend beyond the via 42 in a direction facing away from the respective gate dielectric 22, so that the source region 11 is arranged only between the gate dielectric 22 and the via 42 in the first lateral direction x.

[0048] The source regions 11 may be formed before the gate vias 42 are formed. Due to unavoidable deviations in the dimension of the source regions 11 in the first lateral direction x and the positioning of the vias 42 relative to the source regions 11, the source region may be divided by the respective via 42 into the desired source region 11, which is arranged between the gate dielectric 22 and the via 42, and a remainder 11', which is separated from the source region 11 by the via 42. Such optional residues 11' are shown in the Fig. 6 and Fig. 7 shown in dashed lines.

[0049] Each of the residues 11', together with the body region 12 and a drift region 14, forms a parasitic bipolar transistor. To ensure that parasitic bipolar transistors formed by the residues 11', the body regions 12, and the drift regions 14 do not negatively affect the operation of the transistor component, at least one further body contact region 18 can be arranged in the mesa region between two adjacent body contact regions 17, wherein the further body contact region 18 is connected to the source electrode 41 via a respective electrically conductive via 43.

[0050] As in Fig. 6, the further body contact region 18 can be spaced apart from the body contact regions 17 in the first lateral direction x. According to one example, distances between the further body contact region 18 and the body contact regions 17 are less than 300 nm, in particular less than 200 nm or less than 100 nm.

[0051] According to another example published in Fig. As shown in Figure 7, the further body contact region 18 borders on the body contact regions 17. In this example, the vias 42, the body contact regions 17, and the further body contact region 18 form a closed shield around the residues 11'.

[0052] Fig. 8A to 8C illustrate an example of a method for producing the body contact regions 17 and the electrically conductive vias 42 of arrangements according to the Fig. 4, Fig. 6 and Fig. 7.

[0053] In the Fig. In the example illustrated in Figures 8A to 8C, the body contact regions 17 and the vias 42 are formed after the gate electrodes 21 and the gate dielectrics 22 have been formed in the gate trenches 120, the source and body regions 11, 12 in the mesa regions, and the insulating layer 5 has been formed over the gate electrodes 21 and the first surface 101 of the semiconductor body 100. Referring to Fig. 8A, the method includes forming contact trenches 420 that extend through the insulating layer 5 into the mesa region with the source and body regions 11, 12. The contact trenches 420 are formed such that each of the contact trenches 420 adjoins the source region 11 of the respective transistor cell 10 and extends in the vertical direction into the body region 12.

[0054] Referring to Fig. 8B, the method further comprises implanting dopant atoms of the second type into the body region 12 via bottoms of the contact trenches 420 to form implanted regions 17'. Based on the implanted regions 17', the body contact regions 17 are formed in an annealing process. This annealing process may take place directly after the implantation and before the formation of the vias 42, or may take place after the formation of the vias 42.

[0055] It should be noted that forming the source and body regions 11, 12 may also include an implantation process to implant dopant atoms into the semiconductor body, followed by a subsequent annealing process. The same annealing process may be used to form the source and body regions 11, 12 and the body contact regions 17. According to another example, different annealing processes are used to form the source and body regions 11, 12 on one side and the body contact regions 17 on the other side.

[0056] Referring to Fig. 8C, the method further comprises forming the vias 42 in the contact trenches 420. Forming the vias 42 may comprise completely filling the contact trenches with an electrically conductive material. Alternatively, forming the vias 42 comprises lining the bottoms and sidewalls of the contact trenches 420 with an electrically conductive material.

[0057] The optional further body contact region 18 and the corresponding via 43 can be manufactured by the same process sequence that produces the body contact regions 17 and the corresponding vias 42. The manufacturing of the optional further body contact region 18 and the corresponding via 43 is described in the Fig. 8A to 8C in dashed lines. This process includes forming another contact opening 430 together with the contact openings 420 (see Fig. 8A), implanting dopant atoms of the second type into the further contact opening 430 to form a further implanted region 18', forming the further body contact region 18 based on the further implanted region 18' using an annealing process, and forming the further via 43 in the further contact opening 430.

[0058] The Fig. 9A to 9C illustrate an example of a method for manufacturing an assembly of the Fig. 5, in which the two adjacent transistor cells 10 share the body contact region 17 and the corresponding via 42. The method according to the Fig. 9A to 9C is based on the procedure according to the Fig. 8A to 8C and differs from the procedure according to the Fig. 8A to 8C by only creating one contact opening 420 (see Fig. 9A), dopant atoms are implanted into a contact opening 422 to produce an implanted region 17' (see Fig. 9B), only one body contact region 17 is formed in each mesa region based on the implanted region 17' and the via 42 is formed in the contact opening 420.

[0059] For each of the Fig. 8A to 8C and 9A to 9C, in the implantation process for forming the implanted regions 17', the implantation energy is selected such that the dopant atoms are implanted into a region near the bottom of the contact opening 420, so that the resulting body contact region 17 is adjacent to the bottom and connected to the via 42 formed in the contact opening 420. According to one example, the implantation energy is selected from between 10 keV and 50 keV. According to one example, the implantation dose is selected from between 5E14 cm -2 and 5E15 cm-2 selected.

[0060] According to one example, the implantation dose is selected such that the minimum doping concentration of the body contact region 17 is at least 10 times the doping concentration of the body region 12.

[0061] Furthermore, the thickness of the insulating layer 5 is adapted to the implantation energy so that dopant atoms are not implanted through the insulating layer 5 into the semiconductor body 100.

[0062] As explained above, forming the body contact regions 17 based on the implanted regions 17' comprises an annealing process. According to one example, a temperature and duration of this annealing process are selected such that the implanted dopant atoms are electrically activated. As can be seen from the drawings, the body contact regions 17 may extend to some extent from the via 42 to the gate dielectric 22. This may be due to diffusion in the annealing process, but may also be due to scattering in the implantation process. A dedicated annealing process may be used to activate the dopant atoms contained in the body contact regions 17. According to another example, an annealing process that is used, for example, to activate the dopant atoms in the source and body regions 11, 12 is used to activate the dopant atoms contained in the body contact regions 17.

[0063] As explained above, the body contact regions 17 are spaced from the gate dielectric 22 by less than 300 nm. The contact openings (contact trenches) 420 are formed such that they are spaced from the gate dielectric 22 by less than 350 nm or less than 300 nm.

[0064] According to one example, the vertical dimension of the contact openings 420 in the semiconductor body 100 is between 400 nm and 600 nm. The vertical dimension is the dimension of the contact openings 420 in the vertical direction z. That is, in this example, the contact openings 420 extend through the insulating layer 5 and extend between 400 nm and 600 nm from the first surface 101 into the semiconductor body 100. The vertical dimension of the source regions 11 is, for example, between 100 nm and 200 nm. Thus, the body contact regions 17, which are formed by implanting dopant atoms into the bottoms of the contact openings 420, may be spaced from the source regions 11.

[0065] The depth of the gate trenches 120, which is the dimension of the gate trenches 120 in the vertical direction z, is, for example, between 2 micrometers and 4 micrometers. The width of the gate trenches 120, which is the dimension of the gate trenches 120 in the first lateral direction x, is, for example, between 700 nm and 1.3 micrometers (1300 nm). A pitch w2 (see Fig. 4 to 7), which is the center-to-center distance between two adjacent gate trenches, is, for example, between 3 micrometers and 5 micrometers. The lateral dimension w1 of the mesa region is given by the pitch w2 minus the gate trench width.

[0066] The Fig. 10A-10C illustrate another example of a method for forming a common body contact region 17 and a corresponding via 42.

[0067] Referring to the Fig. 10A-10B, this method comprises forming an implanted region 17' by implanting dopant atoms of the second type into the body region 12 via the first surface 101. The dopant atoms are implanted using an implantation mask 301 comprising an opening, wherein the opening defines the regions into which dopant atoms are to be implanted. The source and body regions 11, 12 may be formed before or after implanting the dopant atoms to form the implanted region 17'. The implantation process takes place before forming the insulating layer 5 on the first surface 101 of the semiconductor body 100.

[0068] Referring to Fig. 10B, the method further comprises forming the insulating layer 5 and forming the contact opening 420 in the insulating layer 5 and in portions of the semiconductor body 100. The contact opening (contact trench) 420 is formed such that it extends through the insulating layer 5 and portions of the semiconductor body 100 into the implanted region 17' or the body contact region 17.

[0069] As explained above, forming the body contact region 17 based on the implanted region 17' includes an annealing process. This annealing process may take place before or after forming the contact opening 420. Consequently, the contact opening 420 is formed to extend either into the implanted region 17' or into the body contact region 17.

[0070] Referring to Fig. 10C, the method further comprises forming the contact via 42 in the contact opening 420. In the Fig. In the example illustrated in FIG. 10C, the source regions 11 extend in lateral directions to the contact via 42. However, this is only an example. According to a further example (not illustrated), the transistor device may comprise further contact vias connecting the source regions 11 to the source electrode 41 (in Fig. 10C not shown).

[0071] In each of the examples explained here above, the source electrode 41 is formed after the contact vias 42 and the optional further contact vias 43 have been formed on the insulating layer 5.

[0072] As explained above, the body contact regions 17 increase the robustness of the transistor component, in particular the robustness of the transistor component in avalanche operation or diode operation. The buffer region 16 also contributes to the robustness of the transistor component in these operating states. As explained above, the buffer region 16 is arranged between the drift regions 14 and the drain region 13 and has a lower doping concentration than the drift regions 14 and the drain regions 13. The buffer region 16 contributes to the on-resistance of the transistor component, which is the electrical resistance between the drain and source nodes D, S in the on-state. In principle, the greater the thickness of the buffer region 16, the higher the on-resistance.

[0073] To deactivate the parasitic bipolar transistor, a thickness of the buffer region 16 may be reduced compared to a conventional superjunction transistor device.

[0074] The thickness d2 (see Fig. 1) of the buffer region 16 is the dimension of the buffer region 16 in the vertical direction z of the semiconductor body 100. According to one example, the thickness d2 of the buffer region 16 is less than 25% or even less than 20% of a distance d1 between the buffer region 16 and the first surface 101.

[0075] According to one example, the thickness d2 and the doping concentration of the buffer region 16 are adapted to one another such that a proportion of a total on-resistance of the transistor component resulting from the electrical resistance of the buffer region 16 is between 10% and 20% of the total on-resistance.

[0076] The distance between the buffer region 16 and the first surface 101 is primarily determined by the vertical dimension d3 of the drift and compensation regions 14, 15. The doping of the drift and compensation regions 15 and the vertical dimension d3 of the drift and compensation regions 14, 15 primarily define the voltage blocking capability of the transistor device. The vertical dimension of the body region 12 is much lower than the vertical dimension of the drift and compensation regions 14, 15 and amounts to less than 3% or even less than 2% of the vertical dimension d3 of the drift and compensation regions 14, 15.

[0077] According to one example, the distance d1 between the buffer region 16 and the first surface 101 is between 35 micrometers and 50 micrometers.

[0078] According to one example, the voltage blocking capability of the transistor device is 600 V. In this example, the distance between the buffer region 16 and the first surface 101 is between 38 micrometers and 42 micrometers and the thickness d3 of the buffer region 16 is, for example, between 6 micrometers (µm) and 10 micrometers.

[0079] According to another example, the voltage blocking capability of the transistor device is 650 V. In this example, the distance between the buffer region 16 and the first surface 101 is between 42 micrometers and 44 micrometers and the thickness d3 of the buffer region 16 is, for example, between 8 micrometers and 11 micrometers.

[0080] In both examples, the vertical dimension of the body region 12 is, for example, between 800 nanometers (nm) and 1.8 micrometers.

[0081] Fig. 11A to 11B schematically illustrate top views of the entire transistor device according to two different examples. More specifically, Fig. 11A to 11B show a top view of the source electrode 41 and other features formed over the first surface 101 (in the Fig. 11A to 11B not visible) of the semiconductor body 100.

[0082] Referring to the Fig. 11A to 11B, each of the transistor devices includes a gate runner 44 and a gate pad 45 connected to the gate runner 44. The gate runner 44 surrounds the source electrode 41 in horizontal directions. The gate pad 45 and the gate runner 44 are spaced apart from the source electrode 41. The gate pad 45, the gate runner 44, and the source electrode 41 may comprise the same material and may be fabricated by the same process. The gate pad 45 may be adjacent to the gate runner 41 (as shown). According to another example (not shown), the gate pad 45 is spaced apart from the gate runner 44, and a resistor (gate resistor) is formed between the gate runner 44 and the gate pad 45.

[0083] The transistor cells 10 are in the Fig. 11A and Fig. 11B is not shown. For illustrative purposes only, the position of two of the plurality of gate trenches 120 relative to the source electrode 41 and the gate runner 44 is shown in the Fig. 11A to 11B are shown by bold lines. As explained above, in each of these gate trenches 120, a respective electrode is arranged, which forms the gate electrode of at least one transistor cell 10. The gate electrode 21 in each of these trenches is electrically connected to the gate runner 44 at at least one of two opposite longitudinal ends of the respective gate electrode 21. The longitudinal ends of the gate electrodes 21 are ends of the gate electrodes 21 in the second lateral direction y. The gate electrodes 21 are connected to the gate runner 44 in a conventional manner, for example, using electrically conductive vias. However, such connections are not shown in the Fig. 11A to 11B not shown.

[0084] The gate pad 45 forms the gate node of the transistor components, so that the control voltage for switching on or off the transistor cells 10 can be applied between the gate pad 45 and the source electrode 41, which can also be referred to as the source pad.

[0085] In the Fig. 11A, the gate pad 45 is arranged at a position that is substantially midway between two opposite side walls of the semiconductor body 100. In the example according to Fig.11B, the gate pad 45 is arranged at a position close to a corner formed by two adjacent sidewalls of the semiconductor body 100. In each of these examples, the transistor device may comprise two types of gate electrodes 21, gate electrodes of a first type and gate electrodes of a second type. For gate electrodes 21 of the first type, both a first longitudinal end and an opposite second longitudinal end 122 are connected to the gate runner 44. For gate electrodes of the second type, only one longitudinal end is connected to the gate runner 44.

[0086] The semiconductor body 100 may comprise an inner region and a peripheral region. The inner region, which may also be referred to as the active region, comprises the transistor cells 10 and is essentially the region of the semiconductor body 100 that is arranged below the source electrode 41. The peripheral region is arranged between the inner region and the sidewalls of the semiconductor body 100. According to one example, the gate runner 44 and the gate pad 45 are arranged above the peripheral region of the semiconductor body 100.

Claims

[1] Transistor device comprising: transistor cells (10); a source electrode (41); Drift regions (14) of the first doping type and compensation regions (15) of the second doping type; a drain region (13) of the first doping type; and a buffer region (16) of the first doping type arranged between the drain region (13) and the drift and compensation regions (15), wherein the transistor cells (10) each have: a source region (11) of a first doping type; a body region (12) which is of a second doping type complementary to the first doping type and adjoins the source region (11); a gate electrode (21) which is adjacent to the body region (12), is dielectrically insulated from the body region (12) by a gate dielectric (22) and is arranged in a gate trench (120) which extends from a first surface (101) of a semiconductor body (100) into the semiconductor body (100); a body contact region (17) adjacent to the body region (12) and electrically connected to the source electrode (41), wherein a distance (d4) between the body contact region (17) and the gate dielectric (22) is less than 300 nanometers, wherein the drift regions (14) each adjoin the body region (12) of at least one of the transistor cells (10), wherein the compensation regions (15) are each connected to the source electrode (41) and are adjacent to at least one of the drift regions (14), and wherein a dimension (d6) of the buffer region (16) in a vertical direction (z) of the semiconductor body (100) is less than 25% or less than 20% of a distance between the buffer region (16) and the first surface (101). [2] Transistor component according to claim 1, wherein the distance (d4) between the body contact region (17) and the gate dielectric is greater than 150 nanometers. [3] A transistor device according to claim 1 or 2, further comprising: an insulating layer (5) arranged between the source electrode (41) and the first surface (101) of the semiconductor body (100). [4] Transistor component according to claim 3, wherein the body contact region (17) is connected to the source electrode (41) via an electrically conductive via (42) extending from the source electrode (41) through the insulating layer (5) and a portion of the semiconductor body (100) to the body contact region (17). [5] The transistor device of claim 4, wherein a distance between the electrically conductive via (42) and the gate dielectric (22) is less than 350 nanometers. [6] Transistor component according to claim 5, wherein source and body regions (11, 12) of two adjacent transistor cells (10) are arranged in a mesa region between adjacent gate trenches (120), and wherein the two adjacent transistor cells (10) each have a respective body contact region (17) and a respective electrically conductive via (42). [7] Transistor component according to claim 5, wherein source and body regions (11, 12) of two adjacent transistor cells (10) are arranged in a mesa region between adjacent gate trenches (120), and wherein the two adjacent transistor cells (10) have a common body contact region (17) and a common electrically conductive via (42) connected between the body contact region (17) and the source electrode (41). [8] A transistor device according to claim 6, further comprising: a further body contact region (18) which is arranged between the body contact regions (17) of the adjacent transistor cells (10) and is connected to the source electrode (41) via a further electrically conductive via (43). [9] Transistor component according to claim 8, wherein the further body contact region (18) is spaced from the body contact regions (17) of the adjacent transistor cells (10). [10] Transistor component according to claim 8, wherein the further body contact region (18) adjoins the body contact regions (17) of the adjacent transistor cells (10). [11] Transistor component according to one of the preceding claims, wherein a doping concentration of the body contact region (17) is at least 10 times a doping concentration of the body region (17). [12] Transistor component according to one of claims 1 to 11, wherein the compensation regions (15) each adjoin the body region (12) of at least one of the transistor cells (10). [13] A transistor device according to any one of claims 1 to 12, wherein the distance between the first surface (101) and the buffer region (16) is selected from between 35 micrometers and 50 micrometers. [14] Transistor device comprising: transistor cells (10); a source electrode (41), Drift regions (14) of the first doping type and compensation regions (15) of the second doping type; a drain region (13) of the first doping type; and a buffer region (16) of the first doping type arranged between the drain region (13) and the drift and compensation regions (15), wherein the transistor cells (10) each have: a source region (11) of a first doping type; a body region (12) which is of a second doping type complementary to the first doping type and adjoins the source region (11); a gate electrode (21) which is adjacent to the body region (12), is dielectrically insulated from the body region (12) by a gate dielectric (22) and is arranged in a gate trench (120) which extends from a first surface (101) of a semiconductor body (100) into the semiconductor body (100); a body contact region (17) adjacent to the body region (12) and electrically connected to the source electrode (41), wherein the body contact region (17) is connected to the source electrode (41) via an electrically conductive via (42) extending from the source electrode (41) through the insulating layer (5) and a portion of the semiconductor body (100) to the body contact region (17), wherein a distance between the electrically conductive via (42) and the gate dielectric (22) is less than 350 nanometers, wherein the drift regions (14) each adjoin the body region (12) of at least one of the transistor cells (10), wherein the compensation regions (15) are each connected to the source electrode (41) and are adjacent to at least one of the drift regions (14), and wherein a dimension (d6) of the buffer region (16) in a vertical direction (z) of the semiconductor body (100) is less than 25% or less than 20% of a distance between the buffer region (16) and the first surface (101). [15] The transistor device of claim 14, wherein the distance between the electrically conductive via (42) and the gate dielectric (22) is less than 300 nanometers.

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