Air lining for substrate through-holes and manufacturing processes

Abstract

Device comprising: a substrate (110, 210); a first conductive pad (370) arranged over a first side (230) of the substrate (110, 210) in a first direction; a second conductive pad (500) arranged over a second side (231) of the substrate (110, 210) in the first direction; a substrate via (350) extending into the substrate (110, 210) in the first direction, the substrate via (350) being arranged between the first conductive pad (370) and the second conductive pad (500) in the first direction; an air liner (450, 550, 750) being arranged between the substrate via (350) and the substrate (110, 210) in a second direction that differs from the first direction;a protective ring structure (250) arranged between the substrate (110, 210) and the first conductive pad (370) in the first direction, wherein the protective ring structure (250) is arranged adjacent to the substrate via (350) in the second direction, and wherein a section of the air lining (450, 550, 750) is arranged between the protective ring structure (250) and the substrate via (350) in the second direction; a dielectric lining (310) arranged between the air lining (450, 550, 750) and the first conductive pad (370) in the first direction, wherein the dielectric lining (310) is also arranged between the protective ring structure (250) and the substrate via (350) in the second direction;and an insulating film (460) which is arranged to plug the air lining (450, 550, 750) from the second side (231) between the air lining (450, 550, 750) and the second conductive pad (500) in the second direction, wherein the insulating film (460) is also arranged between the substrate (110, 210) and the substrate via (350) in the second direction.

Description

PRIORITY INFORMATIONThis application claims priority to U.S. Provisional Patent Application Serial No. 63 / 486,411, filed February 22, 2023, entitled “Through-Substrate Via (Tsv) Liner With Reduced Capacitance,” which is incorporated by reference into the present application.GENERAL STATE OF THE ARTThe semiconductor integrated circuit industry (SIC industry) has experienced exponential growth. Technological advances in IC materials and IC design have produced generations of ICs, with each generation having smaller and more complex circuits than the previous generation. As ICs have evolved, feature density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and decreasing associated costs. Such scaling-down has also increased the complexity of processing and manufacturing ICs. For example, existing manufacturing processes can result in components that have excessive parasitic capacitance.Therefore, conventional methods for manufacturing semiconductor devices, while generally suitable, have not been satisfactory in all respects.SHORT DESCRIPTION OF THE DRAWINGSAspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for the sake of clarity of illustration. It is also emphasized that the accompanying drawings illustrate only typical embodiments of this invention and, therefore, are not to be considered limiting of the scope, as the invention may equally well be practiced in other embodiments. Fig. 1A illustrates a three-dimensional perspective view of a FinFET device. Fig. 1B illustrates a top view of a FinFET device. Figure 1C illustrates a three-dimensional perspective view of a multi-channel gate-all-around (GAA) device. 2-24 illustrate a series of cross-sectional views of an IC device at various stages of fabrication in accordance with embodiments of the present disclosure. 25 illustrates a system for fabricating an integrated circuit in accordance with various aspects of the present disclosure. 26 is a flow diagram illustrating a method of manufacturing an IC device in accordance with various aspects of the present disclosure.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.Furthermore, spatially related terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used herein for convenience in describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or with other orientations) and the spatially related descriptors used herein may be interpreted accordingly.Furthermore, when a number or range of numbers is described with "about," "approximately," and the like, the term is intended to include numbers that are within a reasonable range including the described number, such as within + / - 10% of the described number or other values as one skilled in the art would understand. For example, the term "about 5 nm" includes the dimension range of 4.5 nm to 5.5 nm.The present disclosure relates generally to semiconductor devices, and more particularly to 3-Dimensional Integrated Circuits (3DICs), such as a package including a Through-Substrate Via (TSV) structure. More specifically, heat dissipation is a concern for 3DICs due to the thinness of the die. A thicker substrate may be helpful for heat dissipation, but it also leads to an increase in parasitic capacitance. Air has low capacitance, which may be used herein to reduce parasitic capacitance. For example, the present disclosure introduces air liners as a novel TSV liner for reducing parasitic capacitance.The various aspects of the present disclosure will now be discussed below with reference to FIGS. 1A-1C and 2-26. In more detail, FIGS. 1A-1C illustrate exemplary transistors that may be formed as part of a 3DIC device. For example, field effect transistors (FETs), such as three-dimensional fin-shaped FETs (FinFETs) or gate-all-around (GAA) devices, may be formed as components of the 3DIC device. In this regard, a FinFET device is a fin-shaped field effect transistor device and a GAA device is a multi-channel field effect transistor device. FinFET devices and GAA devices have both recently become increasingly popular in the semiconductor industry because they offer several advantages over traditional metal-oxide-semiconductor field-effect transistor (MOSFET) devices (e.g., "planar" transistor devices). These advantages may include better chip area efficiency, improved carrier mobility, and manufacturing processing compatible with the manufacturing processing of planar devices. Thus, it may be desirable to design an integrated circuit chip (IC) using FinFET devices or GAA devices for a portion of or the entire IC chip.Referring now to FIGS. 1A and 1B, a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) device 90 are illustrated, respectively. The IC device 90 is implemented as a FinFET. As shown in FIG. 1A, the IC device 90 includes a substrate 110. The substrate 110 may include an elemental semiconductor (single element semiconductor), such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 may be a single layer material having a uniform composition. Alternatively, the substrate 110 may include multiple layers of material having similar or different compositions suitable for IC device fabrication. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain regions, may be formed in or on the substrate 110. The doped regions may be doped with n-type dopants, such as phosphorus or arsenic, and / or p-type dopants, such as boron, depending on the design requirements. The doped regions may be formed directly on the substrate 110, in a p-well structure, in an n-well structure, in a double-well structure, or using a raised structure. The doped regions may be formed by implantation of doped atoms, in-situ doped epitaxial growth, and / or other suitable techniques.Three-dimensional active regions 120 are formed on the substrate 110. The active regions 120 may include elongated fin-like structures that protrude upwardly from the substrate 110. As such, the active regions 120 may be interchangeably referred to hereinafter as fin structures 120 or fins 120. The fin structures 120 may be formed using suitable processes including photolithography and etching processes. The photolithography process may include forming a photoresist layer overlying the substrate 110, exposing the photoresist to a structure, performing a post-exposure bake process, and developing the photoresist to form a masking element (not shown) including the resist. The masking element is then used to etch recesses into the substrate 110, leaving the fin structures 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed using double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography processes and self-aligned processes, which may create structures having, for example, pitches smaller than what may otherwise be obtained using a single, direct photolithography process. As an example, a layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned layer using a self-aligned process. The layer is then removed and the remaining spacers or mandrels may then be used to pattern the fin structures 120.The IC device 90 also includes source / drain components 122 formed over the fin structures 120. The source / drain components 122 may include epi layers epitaxially grown on the fin structures 120. The source / drain components 122 may refer individually or collectively to a source or a drain, depending on the context. A source / drain component (or source / drain region) may also refer to a component (or region) that provides a source and / or drain for multiple devices.The IC device 90 further includes isolation structures 130 formed over the substrate 110. The isolation structures 130 electrically isolate various components of the IC device 90. The isolation structures 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride doped silicate glass (FSG), a low-k dielectric material (having a dielectric constant less than about 3.9), and / or other suitable materials. In some embodiments, the isolation structures 130 may include shallow trench isolation features (STI). In one embodiment, the isolation structures 130 are formed by etching trenches in the substrate 110 during formation of the fin structures 120. The trenches may then be filled with an isolation material described above, followed by a chemical mechanical planarization (CMP) process. Another isolation structure, such as a field oxide, a local oxidation of silicon (LOCOS), and / or other suitable structures may also be implemented as isolation structures 130. Alternatively, isolation structures 130 may comprise a multi-layer structure, for example, comprising one or more thermal oxide liner layers.The IC device 90 also includes gate structures 140 formed over and engaging the fin structures 120 on three sides in a channel region of each fin 120. In other words, the gate structures 140 each wrap around a plurality of fin structures 120. The gate structures 140 may be dummy gate structures (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or they may be high-k metal gate (HKMG) structures including a high-k gate dielectric and a metal gate electrode, where the HKMG structures are formed by replacing the dummy gate structures. Although not illustrated herein, the gate structure 140 may include additional material layers, such as an interface layer over the fin structures 120, a cap layer, other suitable layers, or combinations thereof.Referring to FIGS. 1A-1B, a plurality of fin structures 120 are each longitudinally aligned along the X-direction and a plurality of gate structures 140 are each longitudinally aligned along the Y-direction, i.e., generally perpendicular to the fin structures 120. In many embodiments, the IC device 90 includes additional elements such as gate spacers disposed along the sidewalls of the gate structures 140, hard mask layer(s) disposed over the gate structures 140, and numerous other elements.Fig. 1C illustrates a three-dimensional perspective view of an exemplary multi-channel gate-all-around (GAA) device 150. GAA devices include multiple elongated nanostructure channels that may be implemented as nanotubes, nanosheets, or nanowires. For consistency and clarity, similar components in Fig. 1C and Figs. 1A-1B will be labeled the same. For example, active regions, such as fin structures 120, extend vertically upward from substrate 110 in the Z direction. Isolation structures 130 provide electrical isolation between fin structures 120. The gate structure 140 is located over the fin structures 120 and over the isolation structures 130. A mask 155 is located over the gate structure 140, and gate spacers 160 are located on sidewalls of the gate structure 140. A cap layer 165 is formed over the fin structures 120 to protect the fin structures 120 from oxidation during formation of the isolation structures 130.A plurality of nanostructures 170 are disposed above each of the fin structures 120. The nanostructures 170 may comprise nanosheets, nanotubes or nanowires, or another type of nanostructure extending horizontally in the X direction. Portions of the nanostructures 170 beneath the gate structure 140 may serve as channels of the GAA device 150. Dielectric internal spacers 175 may be disposed between the nanostructures 170. Additionally, although not illustrated for simplicity, each stack of nanostructures 170 may be circumferentially wrapped by a gate dielectric as well as a gate electrode. In the illustrated embodiment, the portions of the nanostructures 170 outside of the gate structure 140 may serve as source / drain elements of the GAA device 150. However, in some embodiments, continuous source / drain elements may be epitaxially grown over portions of the fin structures 120 outside of the gate structure 140. Regardless, conductive source / drain contacts 180 may be formed over the source / drain elements to provide electrical connectivity thereto. An interlayer dielectric (ILD) 185 is formed over the isolation structures 130 and around the gate structure 140 and the source / drain contacts 180. The ILD 185 may be referred to as an ILDo layer. In some embodiments, the ILD 185 may comprise silicon oxide, silicon nitride, or a low-k dielectric material.The FinFET devices of Figs. 1A-1B and the GAA devices of Fig. 1C can be used to implement electrical circuitry having various functionalities, such as memory devices (e.g., static random access memory (SRAM) devices), logic circuitry, application specific integrated circuit (ASIC) devices, high frequency (RF) circuitry, drivers, microcontrollers, central processing units (CPUs), image sensors, etc., as non-limiting examples.2-24 illustrate diagrammatic fragmentary cross-sectional views of a portion of a three-dimensional integrated circuit (3DIC) device 200 at various stages of fabrication. FIGS. 2-24 correspond to three different embodiments, with FIGS. 2-9 corresponding to a first embodiment of the present disclosure, FIGS. 10-15 corresponding to a first embodiment of the present disclosure, and FIGS. 16-24 corresponding to a third embodiment of the present disclosure.Referring to FIG. 2, the 3DIC device 200 includes a substrate 210. In some embodiments, the substrate 210 includes a silicon substrate. In other embodiments, the substrate 210 may include another type of material, for example, another type of semiconductor material. A variety of manufacturing processes have already been performed on the 3DIC device 200 to form various components. For example, the FinFET devices or the GAA devices previously discussed with reference to FIGS. 1A-1C may be formed in the 3DIC device 200, for example, as part of the electrical circuitry 220. In some embodiments, the electrical circuitry 220 may be part of a system-on-a-chip (SoC) device.The substrate 210 has a front side 230 and a back side 231 opposite the front side 230. The front side 230 and the back side 231 may also be considered the front and back sides of the 3DIC device 200, respectively. The electrical circuitry 220 is formed over the front side 230 of the substrate 210.A multilayer interconnect structure 240 is also formed over the front side 230 of the substrate 210. When completed, the multilayer interconnect structure 240 may include a plurality of metal layers having interconnection elements, such as metal lines, and conductive vias vertically interconnecting different metal lines of different metal layers. The metal lines and the conductive vias are embedded in a dielectric material 245, such as a silicon oxide material or a low-k dielectric material.Portions of the multilayer interconnect structure 240 may be used to implement a plurality of guard ring (GR) structures 250. For example, each guard ring structure 250 consists of a vertical stack of metal lines and vias of the multilayer interconnect structure 240. The guard ring structures 250 protect the components of the 3DIC device 200 from undesirable elements in semiconductor manufacturing, such as moisture, humidity, dirt particles, or even pressure exerted against the 3DIC device 200 (e.g., pressure exerted by a dicing / sawing tool in a dicing process). This is because the guard ring structures can form an enclosed barrier around the components that need to be protected so that the undesirable elements discussed previously (e.g., moisture, dirt particles, etc.) cannot pass through the barrier in a way that negatively affects the other components within the 3DIC device 200.Continuing to refer to FIG. 2, one or more etch processes 280 may be performed on the 3DIC device 200 to form an opening 300. For example, a patterned photoresist layer (including an opening) may be formed over the front side 230 of the 3DIC device 200. Thereafter, the one or more etch processes 280 may be performed. In some embodiments, the etch processes may include wet etch processes. In other embodiments, the etch processes may include dry etch processes. The patterned photoresist layer may serve as a protective mask during the etch processes 280 such that portions of the 3DIC device 200 not protected by the patterned photoresist layer may be etched away during the etch processes 280.As shown in Figure 2, the opening 300 extends vertically through the interconnect structure (e.g., separating the guard ring structures 250) and through portions of the substrate 210, although the opening 300 does not extend completely vertically through the substrate 210. It should be noted that the guard ring structures 250 help protect components of the 3DIC device 200 (e.g., the SoC comprising the electrical circuitry 220) from moisture, stress, and / or debris that may be introduced during the etch processes 280.After the opening 300 is formed, a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)) may be performed to deposit a liner layer 310 over the 3DIC device 200. The liner layer 310 partially fills the opening 300. For example, the liner layer 310 is deposited on the bottom surface and side surfaces defining the opening 300. In some embodiments, the liner layer 310 comprises a dielectric material, such as silicon oxide. However, in other embodiments, the liner layer 310 may comprise other types of dielectric materials, such as a low-k dielectric material (e.g., having a dielectric constant less than that of silicon dioxide). In some embodiments, the liner layer 310 has a dielectric constant in a range between about 1 and about 3. Example materials of the liner layer 310 may include SiOC(N), SiB, SiBN, AlOx, or LTOx. It is understood that the liner layer 310 will be removed in a later process to form air liners. In some embodiments, the liner layer 310 has a thickness between about 0.1 microns and about 0.3 microns. This range of values is optimized. If the liner layer 310 is too thick, then the size of the TSV structure (to be subsequently formed) may also need to be increased. If the liner layer 310 is not thick enough, then it may not be able to block the water gas / vapor or other forms of moisture.Referring now to FIG. 3, a TSV formation process 330 is performed on the 3DIC device 200 to form a TSV structure 350. More specifically, as a first step of the TSV formation process 330, a layer 360 may be deposited on the liner layer 310 in the opening 300. In some embodiments, the layer 360 includes a seed layer for a subsequent electroplating process. The seed layer may include a conductive material such as copper, aluminum, tungsten, cobalt, titanium, or combinations thereof. In some embodiments, the layer 360 may also include a barrier layer in addition to the seed layer. The barrier layer is configured to prevent or reduce undesirable diffusion.As a second step of the TSV formation process 330, an electroplating process may be performed to completely fill the opening 300 with a conductive material (such as copper, aluminum, tungsten, cobalt, titanium, or combinations thereof). It should be noted that the conductive material filling the opening 300 may have a same material composition as the seed layer (e.g., layer 360). As such, there may be no discernible interface between the conductive material filling the opening 300 and the seed layer. Thereafter, one or more planarization (CMP) processes may be performed to planarize or otherwise flatten a top surface of the conductive material filling the opening 300. The TSV structure 350 is formed by the remaining portion of the conductive material in the opening 300.Following formation of the TSV structure 350, a plurality of back-end-of-the-line processes may be performed to form additional metallization components over the front side 230 of the 3DIC device 200. For example, a conductive pad 370 is formed directly on the TSV structure 350, and another conductive pad 380 is formed over the conductive pad 370. The conductive pad 370 may also be referred to as a top metal pad, and the conductive pad 380 may also be referred to as an access pad. The conductive pad 370 and the conductive pad 380 may each include a conductive material, such as aluminum or copper, although it is possible that the conductive pad 370 and the conductive pad 380 may have different material compositions. The conductive pad 370 and the conductive pad 380 may also be electrically coupled to each other by a plurality of conductive vias 390. A conductive bump 400 (e.g., a solder bump) may also be formed over the conductive pad 380. The conductive pad 370, the conductive pad 380, the conductive vias 390, and a portion of the conductive bump 400 may be embedded within a passivation structure 410, which may include one or more dielectric materials. Electrical access to the TSV structure 350 may be obtained through the conductive bump 400, the conductive pad 380, and the conductive pad 370.Referring now to FIG. 4, a backside thinning process 420 is performed on the 3DIC device 200. More specifically, the backside thinning process 420 may include one or more chemical etching and / or mechanical grinding processes configured to remove portions (e.g., including the substrate 210, the liner layer 310, the layer 360, and the TSV structure 350) of the 3DIC device 200 from the backside 231. The backside thinning process 420 is performed until the bottom surface (the surface facing the backside 231) of the TSV structure 350 is exposed. At this stage of fabrication, the TSV structure 350 has a vertical dimension 430 (which may also be referred to as the thickness of the TSV). In some embodiments, the vertical dimension 430 may range from about 1 micron to about 50 microns.Referring now to FIG. 5, one or more etch processes 440 may be performed on the 3DIC device 200 to form air liners 450 between the substrate 210 and the TSV structure 350. The one or more etch processes 440 may include wet etch processes, dry etch processes, or combinations thereof. The one or more etch processes 440 are configured to have etch selectivity between the liner layer 310 and the substrate 210. For example, one or more etch processes 440 may be configured to have a substantially higher etch rate (e.g., five times higher, ten times higher, or more) for the liner layer 310 than for the substrate 210. As such, when the one or more etch processes 440 are performed from the backside 231 of the 3DIC device 200, portions of the liner layer 310 are etched away at the substantially higher etch rate than the substrate 210. Consequently, air gaps -which may be referred to as air liners 450 hereinafter -are formed in place of the removed portions of the liner layer 310, while the substrate 210 remains substantially unaffected. It should be noted that the one or more etch processes 440 may also be performed with a sufficiently high etch selectivity between the liner layer 310 and the TSV structure 350 such that the formation of the air liners 450 does not significantly affect the TSV structure 350 either.After the air liners 450 are formed, an insulation film 460 is formed on the backside 231 of the 3DIC device 200. In some embodiments, the insulation film 460 comprises silicon oxide, silicon nitride, or polyimide. The insulation film 460 may be formed via one or more deposition processes. The deposition processes are configured to deposit portions of the insulation film 460 to partially (but not completely) fill the air liners 450. In other words, the insulation film 460 is formed to plug or otherwise seal the air liners 450 from the backside 231.As shown in FIG. 5, the air liners 450 formed herein each have a vertical dimension 470 (also referred to as a length of the air liners 450) at this stage of fabrication. One of the advantages of the present disclosure is that the vertical dimension 470 is adjustable. For example, the parameters of the etch processes 440 may be adjusted to establish how much of the liner layer 310 is subsequently removed, which in turn determines the vertical dimension 470 of the air liners 450. For example, a longer etch time or a stronger etchant may result in a larger vertical dimension 470 for the air liners 450. Conversely, a shorter etch time or a weaker etchant may result in a smaller vertical dimension 470 for the air liners 450. The adjustability of the vertical dimension 470 of the air liners 450 allows the overall dielectric constant (and therefore capacitance) of the 3DIC device 200 to be flexibly adjusted depending on the design needs and / or manufacturing requirements.Referring now to FIG. 6, a removal process 480 may be performed on the 3DIC device 200 from the backside 231 to partially remove the insulation film 460. For example, the removal process 480 may include dry etching processes, CMP processes, or combinations thereof. The removal process 480 is configured to stop when the substrate 210 is reached or when the TSV structure 350 is reached. After the removal process 480 is performed, the substrate 210 and the TSV structure 350 are exposed to the backside 231. The remaining portions of the insulation film 460 still seal the air liners 450 so that the air liners 450 are not exposed to the backside 231.Referring now to FIG. 7, a metallization process 490 may be performed on the 3DIC device 200 to form a conductive pad 500 over the backside 231 of the 3DIC device 200. For example, the conductive pad 500 is formed on the backside surfaces of the substrate 210, the TSV structure 350, and the remaining portions of the insulation film 460. The conductive pad 500 comprises a conductive material (e.g., copper or aluminum), and as such, the conductive pad 500 is electrically coupled to the conductive pads 370 and 380 through the TSV structure 350.Implementing the air liners 450 herein helps reduce the parasitic capacitance of the 3DIC device 200. More specifically, air has a relatively low dielectric constant (a value of 1) compared to other types of dielectric materials. Since parasitic capacitance directly correlates with a dielectric constant value of a dielectric material, decreasing the dielectric constant (e.g., by implementing the air liners 450 herein) would decrease the overall parasitic capacitance. A time constant—which is inversely correlated with speed—is a product of resistance and capacitance. As such, decreasing the parasitic capacitance (e.g., by implementing the air liners 450 herein) will decrease the time constant and increase the speed of the 3DIC device 200. Thus, it can be seen that the implementation of the air liners 450 herein can improve the performance of the 3DIC device 200.As previously discussed, the value of the vertical dimension 470 of the air liners 450 may be flexibly adjusted by setting the process parameters of the etch processes 440. In the embodiment shown in FIG. 7, the vertical dimension 470 of the air liners 450 is set such that a boundary between the liner layer 310 and the air liners 450 is substantially coplanar with the top surface of the substrate 210 (e.g., by approximately the same vertical height). However, this is only an example, and other embodiments may have different lengths for the air liners 450.For example, in a variation of the first embodiment shown in Fig. 8, the air liners 450 each have a vertical dimension 471 that is smaller than the vertical dimension 470 of the air liners 450 of the embodiment of Fig. 7. As shown in Fig. 8, the vertical dimension 471 of the air liners 450 is configured such that a boundary between the liner layer 310 and the air liners 450 is below the top surface of the substrate 210 (e.g., at a lower vertical height than).As another example, in another variation of the first embodiment shown in FIG. 9, the air liners 450 each have a vertical dimension 472 that is greater than the vertical dimension 470 of the air liners 450 of the embodiment of FIG. 7. As shown in FIG. 9, the vertical dimension 472 of the air liners 450 is configured such that a boundary between the liner layer 310 and the air liners 450 is above (e.g., at a higher vertical height than) the top surface of the substrate 210. Again, in any of the embodiments shown in FIG. 8 or FIG. 9, the exact value of the vertical dimensions 471 or 472 for the air liners 450 can be adjusted so that the 3DIC device 200 can achieve a desired capacity over the adjustable length of the air liners 450.It should be noted that because the liner layer 310 is not completely removed in any of the embodiments shown in Figures 7-9, the vertical dimensions 470-472 are smaller than the vertical dimension 430 of the TSV structure 350. It should also be understood that the horizontal dimension of the air liners 450 can also be adjusted by adjusting the horizontal dimension of the liner layer 310. If a thicker liner layer 310 were initially deposited, then the resulting air liner 450 would have a larger horizontal dimension. Conversely, if a narrower liner layer 310 were initially deposited, then the resulting air liner 450 would have a smaller horizontal dimension. As such, the air liners 450 herein have both an adjustable length and an adjustable width.2-9 correspond to a first embodiment of forming air liners. A second embodiment of forming air liners is discussed below with reference to FIGS. 10-15. For consistency and clarity, similar components appearing in FIGS. 2-15 will be labeled alike. Referring now to FIG. 10, the second embodiment of the present disclosure also performs the etch processes 280 previously discussed with reference to FIG. 2, the TSV formation process 330 previously discussed with reference to FIG. 3, and the backside thinning process 420 previously discussed with reference to FIG. 4. At this stage of fabrication, the TSV structure 350 has been formed, but no air liners have yet been formed.Referring now to FIG. 11, one or more etch processes 540 may be performed on the 3DIC device 200 to form air liners 550 between the substrate 210 and the TSV structure 350. The one or more etch processes 540 may include wet etch processes, dry etch processes, or combinations thereof. The one or more etch processes 540 are configured to have etch selectivity between the liner layer 310 and the substrate 210 and the TSV structure 350. For example, one or more etch processes 540 may be configured to have a substantially higher etch rate (e.g., five times higher, ten times higher, or more) for the liner layer 310 than for the substrate 210 or the TSV structure 350. As such, when the one or more etch processes 540 are performed from the backside 231 of the 3DIC device 200, portions of the liner layer 310 are etched away at the substantially higher etch rate than the substrate 210. In contrast to the first embodiment where the liner layer 310 is partially removed, in the second embodiment the liner layer 310 is completely removed. That is, after the etch processes 540 are performed, portions of the bottom surface of the conductive pad 370 are exposed to the backside 231.It should be noted that an inherent result of performing the etch processes 540 to completely remove the liner layer 310 is that the resulting air liners 550 are each wider on the top surface and narrower on the bottom surface. For example, each air liner 550 has a horizontal dimension 560 on the top surface and a horizontal dimension 570 on the bottom surface. The horizontal dimension 560 is larger than the horizontal dimension 570. In some embodiments, the horizontal dimension 560 is in a range between about 0.15 microns and about 0.5 microns, and the horizontal dimension 570 is in a range between about 0.1 microns and about 0.3 microns. Another inherent result of performing the etch processes 540 to completely remove the liner layer 310 is that the air liners 550 may have an inclined side surface 550A defined by the sidewall of the dielectric material 245.These physical characteristics of the air liners 550 (e.g., a wider top portion and a sloped side surface) in the second embodiment are inherent results of the etch processes 540, for example, due to the etch selectivity associated with the etch processes 540. More specifically, the substrate 210 (e.g., including silicon) and the liner layer 310 (e.g., including a low-k dielectric material) may have greater etch selectivity, and thus the portion of the air liner 550 formed adjacent to the substrate 210 may have substantially straight sidewalls. On the other hand, the etch selectivity between the liner layer 310 and the regions of the 3DIC device 200 including the dielectric materials 245 may be less than the etch selectivity between the liner layer 310 and the substrate 210. Therefore, the dielectric materials 245 may also be partially etched during removal of the liner layer 310. Accordingly, the air liner 550 has a larger width (e.g., horizontal dimension 560) at its upper portion.Referring now to FIG. 12, a deposition process 590 is performed to form the insulation film 460 on the backside 231 of the 3DIC device 200. As previously discussed, the insulation film 460 may comprise silicon oxide, silicon nitride, or polyimide and may partially (but not completely) fill the air liners 550. In other words, the insulation film 460 is formed to plug or otherwise seal the air liners 550 from the backside 231. At this point, the air liners 550 each have a vertical dimension 600.Similar to the first embodiment of the present disclosure, the vertical dimension 600 of the air liners 550 is also adjustable in the second embodiment of the present disclosure. However, instead of adjusting the process parameters (e.g., etch time and / or etchant) of the etching processes 540 to adjust the vertical dimension 600 of the air liners 550, the second embodiment may adjust the vertical dimension 600 by adjusting the amount of the insulation film 460 that protrudes into the air liners 550. For example, as shown in FIG. 13, the air liners 550 may have a vertical dimension 601 that is less than the vertical dimension 600 shown in FIG. 12. The smaller vertical dimension 601 is a result of a larger amount of the insulation film 460 protruding into the air liners 550, resulting in a shorter length (e.g., a smaller vertical dimension 601) for the air liners 550. Regardless of how the length of the air liners 550 is set up, the fact that it is still adjustable in the second embodiment still allows the overall dielectric constant (and therefore capacitance) of the 3DIC device 200 to also be flexibly set up depending on the design needs and / or the manufacturing requirements.Referring now to FIG. 14, the removal process 480 may be performed on the 3DIC device 200 from the backside 231 to partially remove the insulation film 460. For example, the removal process 480 may include dry etching processes, CMP processes, or combinations thereof. The removal process 480 is configured to stop when the substrate 210 is reached or when the TSV structure 350 is reached. After the removal process 480 is performed, the substrate 210 and the TSV structure 350 are exposed to the backside 231. The remaining portions of the insulation film 460 still seal the air liners 450 so that the air liners 450 are not exposed to the backside 231.Referring now to FIG. 15, a metallization process 490 may be performed on the 3DIC device 200 to form a conductive pad 500 over the backside 231 of the 3DIC device 200. For example, the conductive pad 500 is formed on the backside surfaces of the substrate 210, the TSV structure 350, and the remaining portions of the insulation film 460. The conductive pad 500 comprises a conductive material (e.g., copper or aluminum), and as such, the conductive pad 500 is electrically coupled to the conductive pads 370 and 380 through the TSV structure 350.Although the second embodiment (corresponding to Figs. 10-15) forms air liners 550 that are shaped differently than the air liners 450 of the first embodiment (corresponding to Figs. 2-9), it still achieves substantially the same advantages as the first embodiment, such as reduced parasitic capacitance, adjustable total capacitance, and faster speed.A third embodiment of forming air liners is discussed below with reference to FIGS. 16-24. For consistency and clarity, similar components appearing in FIGS. 2-24 will be labeled alike. Referring now to FIG. 16, the third embodiment of the present disclosure also performs the etching processes 280 previously discussed with reference to FIG. 2 to partially etch the opening 300 into the substrate 210. However, while the first embodiment only forms one liner layer 310 over the front side 230 of the 3DIC device 200, the third embodiment forms a plurality of liner layers 710, 711, and 712 over the front side 230. Each of the liner layers 710-712 may be formed by a respective deposition process, such as ALD, CVD, PVD, etc. In some embodiments, the liner layer 711 is formed to comprise a different dielectric material than the liner layers 710 and 712. For example, the liner layers 710 and 712 may be formed to comprise a silicon oxide material, but the liner layer 711 is formed to comprise an alumina material or other low-k dielectric material. The different material compositions between the liner layers 711 and 710 / 712 are arranged to ensure that etch selectivity may be present between them in a subsequently performed etch process.Referring now to FIG. 17, the TSV formation process 330 previously discussed with reference to FIG. 3 is performed to form the TSV structure 350 in the opening 300. Thereafter, the conductive pads 370 and 380, the conductive vias 390, and the conductive bump 400 are also formed over the front side 230 of the 3DIC device 200.Referring now to FIG. 18, the backside thinning process 420 previously discussed with reference to FIG. 4 is performed. As previously discussed, the backside thinning process 420 may include chemical etching and / or mechanical grinding processes to remove portions of the 3DIC device 200 from the backside 231 until the bottom surface of the TSV structure 350 is exposed.Referring now to FIG. 19, one or more etch processes 740 may be performed on the 3DIC device 200 to form air liners 550 between the liner layer 710 and the liner layer 712 by removing the liner layer 711. More specifically, the one or more etch processes 740 may include wet etch processes, dry etch processes, or combinations thereof. The one or more etch processes 740 are configured to have etch selectivity between the liner layer 711 and the other liner layers 710 and 712. Etch selectivity may also exist between the liner layer 711 and the substrate 210 and the TSV structure 350. For example, the one or more etch processes 740 may be configured to have a substantially higher etch rate (e.g., five times higher, ten times higher, or more) for the liner layer 711 than for the liner layers 710 and 712, the substrate 210, or the TSV structure 350. As such, when the one or more etch processes 740 are performed from the backside 231 of the 3DIC device 200, portions of the liner layer 711 are etched away at the substantially higher etch rate than the liner layers 710 and 712, the substrate 210, and the TSV structure 350. In the embodiment shown in FIG. 19, the liner layer 711 is completely removed such that portions of the bottom surface of the conductive pad 370 are exposed from the backside 231. However, in other variations of the third embodiment, it is understood that the liner layer 711 may be partially removed so that the length of the air liner 750 is shorter.Referring now to FIG. 20, a deposition process 590 is performed to form the insulation film 460 on the backside 231 of the 3DIC device 200. As previously discussed, the insulation film 460 may comprise silicon oxide, silicon nitride, or polyimide and may partially (but not completely) fill the air liners 750. In other words, the insulation film 460 is formed to plug or otherwise seal the air liners 750 from the backside 231. At this point, the air liners 750 each have a vertical dimension 760.Referring now to FIG. 21, the removal process 480 previously discussed with reference to FIG. 6 may be performed on the 3DIC device 200 from the backside 231 to partially remove the insulation film 460. For example, the removal process 480 may include dry etching processes, CMP processes, or combinations thereof. The removal process 480 is configured to stop when the substrate 210 is reached or when the TSV structure 350 is reached. After the removal process 480 is performed, the substrate 210 and the TSV structure 350 are exposed to the backside 231. The remaining portions of the insulation film 460 still seal the air liners 750 so that the air liners 750 are not exposed to the backside 231.Referring now to FIG. 22, the metallization process 490 may be performed on the 3DIC device 200 to form the conductive pad 500 over the backside 231 of the 3DIC device 200. For example, the conductive pad 500 is formed on the backside surfaces of the substrate 210, the TSV structure 350, and the remaining portions of the insulation film 460. As previously discussed, the conductive pad 500 is electrically coupled to the conductive pads 370 and 380 through the TSV structure 350.Similar to the first embodiment of the present disclosure, the vertical dimension 760 of the air liners 750 is also adjustable in the third embodiment of the present disclosure. For example, the process parameters (e.g., the etch time and / or the etchant) of the etching processes 740 may be adjusted to control the vertical dimension 760 of the air liners 750. Examples thereof are shown in FIGS. 23 and 24. In FIG. 23, the liner layer 711 is not completely removed by the etching processes 740. The remaining portions of the liner layer 711 each have a bottom surface that is below the top surface of the substrate 210 (e.g., has a lower vertical height than the top surface). As such, the air liners 750 each have a vertical dimension 761 that is less than the vertical dimension 760 of FIG. 22.Similarly, in FIG. 24, the liner layer 711 is also not completely removed by the etch processes 740. The remaining portions of the liner layer 711 each have a bottom surface that is above (e.g., has a greater vertical height than) the top surface of the substrate 210. As such, the air liners 750 each have a vertical dimension 762 that is less than the vertical dimension 760 of FIG. 22, but greater than the vertical dimension 761 of FIG. 23.In addition to setting up the etching processes 740 to adjust the vertical dimension of the air liners 750, the third embodiment may also adjust the vertical dimension of the air liners by adjusting the amount of the insulation film 460 deposited into the air liners 750. Furthermore, the horizontal dimension (e.g., width) of the air liners 750 may be adjusted by adjusting the horizontal dimension of the liner layer 711 when the liner layer 711 was initially deposited, since the formation of the air liners 750 is a direct result of removing the liner layer 711. Regardless of how the vertical dimension or the horizontal dimension of the air liners 750 are determined, the fact that it is still adjustable in the third embodiment means that the overall dielectric constant (and therefore capacitance) of the 3DIC device 200 can also be flexibly set depending on the design needs and / or the manufacturing requirements.25 illustrates an integrated circuit manufacturing system 900 that may be used to manufacture the 3DIC device 200 in accordance with embodiments of the present disclosure. The manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916 ..., N connected by a communications network 918. The network 918 may be a single network or may be a variety of different networks, such as an intranet and the Internet, and may include both wired and wireless communications channels.In one embodiment, entity 902 represents a manufacturing collaboration service system; entity 904 represents a user, such as a product engineer, monitoring the products of interest; entity 906 represents an engineer, such as a processing engineer to control the process and relevant recipes, or an equipment engineer to monitor or adjust conditions and set the processing tools; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool used to perform lithography processes to define the gate spacers of an SRAM device; entity 912 represents a virtual metrology module associated with processing tool 910; entity 914 represents an advanced processing control module associated with processing tool 910 and additionally other processing tools; and entity 916 represents a sampling tool associated with processing tool 910.Each entity may interact with other entities and may provide and / or receive an integrated circuit manufacturing function, a processing control function, and / or a computational function from the other entities. Each entity may also include one or more computer systems for performing computations and executing automation. For example, the advanced processing control module of entity 914 may include a plurality of computer hardware in which software instructions are encoded. The computer hardware may include hard drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), an input / output device (e.g., mouse and keyboard). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.The integrated circuit manufacturing system 900 enables interaction among the entities for the purpose of manufacturing an integrated circuit (IC) as well as advanced processing control of the IC manufacturing. In one embodiment, the advanced processing control includes setting the processing conditions, settings and / or recipes of a processing tool that can be applied to the relevant wafers according to the metrology results.In another embodiment, the metrology results are measured on a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, the metrology results are measured on selected fields and points of the subset of processed wafers according to an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.One of the functions provided by the IC manufacturing system 900 may enable collaboration and information access in areas such as design, engineering and processing, metrology, and advanced processing control. Another function provided by the IC manufacturing system 900 may integrate systems between facilities, such as between the metrology tool and the processing tool. Such integration allows facilities to coordinate their activities. For example, integrating the metrology tool and the processing tool may enable manufacturing information to be more efficiently incorporated into the manufacturing process or APC module, and may enable wafer data from online or on-site metrology with the metrology tool integrated with the associated processing tool.26 is a flow diagram illustrating a method 1000 for manufacturing a semiconductor device. The method 1000 includes a step 1010 of etching an opening extending partially into a substrate from a first side to a second side.The method 1000 includes a step 1020 of depositing a liner structure in the opening.The method 1000 includes a step 1030 of forming a through substrate via (TSV) structure in the opening. The TSV structure is formed over the liner structure.The method 1000 includes a step 1040 of thinning the substrate from the second side. The TSV structure is exposed from the second side after thinning the substrate.The method 1000 includes a step 1050 of removing at least a portion of the liner structure, thereby forming an air liner in place of the removed portion of the liner structure.In some embodiments, at least a first guard ring structure and a second guard ring structure are disposed over the first side of the substrate. The opening separates the first guard ring structure from the second guard ring structure. The air liner is formed between the first guard ring structure and the TSV structure or between the second guard ring structure and the TSV structure.In some embodiments, step 1020 includes depositing a dielectric liner having a dielectric constant less than a dielectric constant of silicon dioxide.In some embodiments, step 1050 includes completely removing the liner structure.In some embodiments, step 1020 includes depositing a first liner layer as a bottom layer of the liner structure, a second liner layer as a middle layer of the liner structure, and a third liner layer as a top layer of the liner structure. The TSV structure is deposited over the third liner layer. Step 1050 includes at least partially removing the second liner layer without substantially affecting the first liner layer or the second liner layer. In some embodiments, step 1050 includes completely removing the second liner layer. In some embodiments, step 1020 includes depositing a first type of oxide material as the first liner layer and the third liner layer and depositing a second type of oxide material as the second liner layer. In some embodiments, step 1050 includes performing an etch process having an etch selectivity between the first type of oxide material and the second type of oxide material.It is understood that additional steps may be performed before, during, or after steps 1010-1050. For example, in some embodiments, method 1000 may further include a step performed after step 1050. In this step, the air liner from the second side is sealed with an insulating film. Method 1000 may also include a step performed after the TSV structure is formed but before the substrate from the second side is thinned. In this step, a first conductive pad is formed over the TSV from the first side. After the air liner is sealed, a second conductive pad is formed over the TSV from the second side. The TSV is electrically coupled to the first conductive pad and the second conductive pad. For simplicity, additional processes are not discussed in detail herein.Based on the previous discussions, it can be seen that the present disclosure implements air liners around TSV structures for a 3DIC device. More specifically, a dielectric liner layer is deposited in an opening that extends partially through a substrate. A TSV structure is formed in the opening. The dielectric liner is at least partially removed (e.g., by etching) to form air liners around the TSV structure. An insulation film may be deposited to seal the air liners as well.The unique manufacturing process flow and resulting device structure of the present disclosure provide advantages over conventional devices. However, it should be understood that no particular advantage is required, other embodiments may provide other advantages, and that not all advantages are necessarily disclosed herein. One advantage is the reduction of parasitic capacitance. For example, air has a lower dielectric constant than other types of dielectric materials. Thus, implementing air liners (as opposed to other types of dielectric liners) around a TSV structure will result in a reduction in the overall dielectric constant, which in turn will result in a reduction in parasitic capacitance. The reduction in parasitic capacitance may lead to device improvements such as speed. Another advantage is the adjustability of capacitance. In particular, the length of the air liners may be flexibly adjusted by adjusting process parameters (e.g., the etch time) of the etch processes used to form the air liners or by adjusting the amount of insulation film deposited into the air liners. By adjusting the size of the air liners, the appropriate capacity associated with the air liners can be established, which also affects the overall capacity of the 3DIC device. Other benefits may include ease of manufacturing and compatibility with existing manufacturing processes.The advanced lithography process, method, and materials described above may be used in many applications, including IC devices that utilize fin-type field effect transistors (FinFETs). For example, the fins may be patterned to provide relatively close spacing between elements, for which the previous disclosure is well suited. Additionally, spacers used in forming fins of FinFETs, also referred to as mandrels, may be processed according to the previous disclosure. It is also understood that the various aspects of the present disclosure discussed above may be applied to multi-channel devices, such as gate-all-around (GAA) devices. To the extent that the present disclosure relates to a fin structure or FinFET devices, these discussions may equally apply to the GAA devices.One aspect of the present disclosure relates to an IC device. A first conductive pad is disposed over a first side of a substrate in a first direction. A second conductive pad is disposed over a second side of the substrate in the first direction. A substrate via (TSV) extends into the substrate in the first direction. The TSV is disposed between the first conductive pad and the second conductive pad in the first direction. An air liner is disposed between the TSV and the substrate in a second direction different from the first direction.One aspect of the present disclosure relates to an IC device. The IC device includes a substrate. The IC device includes a first guard ring structure and a second guard ring structure each disposed over the substrate. The IC device includes a substrate via (TSV) extending partially through the substrate. The TSV separates the first guard ring structure and the second guard ring structure. The IC device includes an air gap disposed between the TSV and the substrate.Yet another aspect of the present disclosure pertains to a method. An opening is etched partially extending into a substrate from a first side to a second side. A liner structure is deposited in the opening. A substrate via (TSV) structure is formed in the opening. The TSV structure is formed over the liner structure. The substrate is thinned from the second side. The TSV structure is exposed to the second side after thinning the substrate. At least a portion of the liner structure is removed, thereby forming an air liner in place of the removed portion of the liner structure.The foregoing has explained features of various embodiments so that one skilled in the art can better understand the detailed description that follows. One skilled in the art should realize that he can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments presented herein. One skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and he can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.QUOTES INCLUDED IN THE DESCRIPTIONThis list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions.Cited patent literatureUS 63 / 486411

[0001]

Claims

A device comprising: a substrate; a first conductive pad disposed over a first side of the substrate in a first direction; a second conductive pad disposed over a second side of the substrate in the first direction; a substrate via (TSV) extending into the substrate in the first direction, the TSV disposed between the first conductive pad and the second conductive pad in the first direction; and an air liner disposed between the TSV and the substrate in a second direction different from the first direction.The apparatus of claim 1, wherein a dimension of the air liner in the first direction is smaller than a dimension of the TSV in the first direction.The device of claim 1 or 2, wherein: a first portion of the air liner is wider than a second portion of the air liner in the second direction; and the first portion of the air liner is located closer to the first conductive pad in the first direction than the second portion of the air liner.The device of any of claims 1 to 3, further comprising a guard ring structure disposed between the substrate and the first conductive pad in the first direction, the guard ring structure disposed adjacent to the TSV in the second direction.The apparatus of claim 4, wherein a portion of the air liner is disposed between the guard ring structure and the TSV in the second direction.The device of claim 4 to 5, further comprising a dielectric liner disposed between the air liner and the first conductive pad in the first direction, the dielectric liner also disposed between the guard ring structure and the TSV in the second direction.The device of claim 6, further comprising an insulating film disposed between the air liner and the second conductive pad in the second direction, the insulating film also disposed between the substrate and the TSV in the second direction.The device of any of claims 4 to 7, further comprising a first dielectric liner and a second dielectric liner each disposed between the first conductive pad and the second conductive pad in the first direction, wherein the air liner is disposed between the first dielectric liner and the second dielectric liner in the second direction.A device comprising: a substrate; a first guard ring structure and a second guard ring structure each disposed over the substrate; a substrate via (TSV) extending partially through the substrate, the TSV separating the first guard ring structure and the second guard ring structure; and an air gap disposed between the TSV and the substrate.The device of claim 9, wherein at least a portion of the air gap is disposed between the TSV and the first guard ring structure or between the TSV and the second guard ring structure.The device of claim 9 or 10, further comprising: a first dielectric liner disposed between the air gap and the substrate; and a second dielectric liner disposed between the air gap and the TSV.A method comprising: etching an opening extending partially into a substrate from a first side to a second side; depositing a liner structure in the opening; forming a through substrate via (TSV) structure in the opening, wherein the TSV structure is formed over the liner structure; thinning the substrate from the second side, wherein the TSV structure is exposed to the second side after thinning the substrate; and removing at least a portion of the liner structure, thereby forming an air liner in place of the removed portion of the liner structure.The method of claim 12, wherein: at least a first guard ring structure and a second guard ring structure are disposed over the first side of the substrate; the opening separates the first guard ring structure from the second guard ring structure; and the air liner is formed between the first guard ring structure and the TSV structure or between the second guard ring structure and the TSV structure.The method of claim 12 or 13, further comprising, after removing, sealing the air liner from the second side with an insulation film.The method of claim 14, further comprising: after forming the TSV structure but before thinning, forming a first conductive pad over the TSV from the first side; and after sealing, forming a second conductive pad over the TSV from the second side, wherein the TSV is electrically coupled to the first conductive pad and the second conductive pad.The method of any of claims 12 to 15, wherein depositing the liner structure comprises depositing a dielectric liner having a dielectric constant less than a dielectric constant of silicon dioxide.A method according to any one of claims 12 to 16, wherein the removal comprises completely removing the lining structure.The method of any of claims 12 to 17, wherein: depositing comprises depositing a first liner layer as a bottom layer of the liner structure, a second liner layer as a middle layer of the liner structure, and a third liner layer as a top layer of the liner structure; depositing the TSV structure over the third liner layer; and removing comprises at least partially removing the second liner layer without substantially affecting the first liner layer or the second liner layer.The method of claim 18, wherein removing comprises completely removing the second liner layer.The method of claim 18 or 19, wherein: the depositing comprises depositing a first type of oxide material as the first liner layer and the third liner layer, and depositing a second type of oxide material as the second liner layer; and the removing comprises performing an etch process with an etch selectivity between the first type of oxide material and the second type of oxide material.