INDICATOR DEVICE AND METHOD FOR MANUFACTURING AN INDICATOR DEVICE

Abstract

A method for manufacturing a display device (DSP), comprising: preparing a carrier (10) by forming a lower electrode (LE, LE1, LE2, LE3) over a printed circuit board, forming a rib (5) having an opening (AP1, AP2, AP3) superimposed on the lower electrode (LE, LE1, LE2, LE3), and forming a partition (6) comprising a lower section (61) located on the rib (5) and an upper section (62) located on the lower section (61) and projecting from a side face (S1A, S1B, S3A, S3B) of the lower section (61), forming an organic layer (OR, OR1, OR2, OR3) on the lower electrode (LE, LE1, LE2, LE3) at the opening (AP1, AP2, AP3), and forming an upper electrode (UE, UE1, UE2, UE3) on the organic layer. (OR,OR1,OR2,OR3), Formation of a transparent layer (TL,TL1,TL2,TL3) on the upper electrode (UE,UE1,UE2,UE3) and Formation of an inorganic layer (IL,IL1,IL2,IL3) on the transparent layer (TL,TL1,TL2,TL3),wherein in the step of forming the upper electrode (UE,UE1,UE2,UE3) a first vapor deposition source (110B) is inclined with respect to a normal (N) of a processing carrier (SUB) and, as the processing carrier (SUB) is transported, material deposited by the first vapor deposition source (110B) is deposited, and in the step of forming the inorganic layer (IL,IL1,IL2,IL3) a second vapor deposition source (110A) is inclined with respect to the normal (N) of the processing carrier (SUB) in a direction opposite to that of the first vapor deposition source (110B) and, as the processing carrier (SUB) is transported, material deposited by the second vapor deposition source (110A) is deposited.

Description

Cross-reference to related registration

[0001] The present application claims priority over Japanese application no. 2022-074873, filed on 28 April 2022, the full contents of which are hereby incorporated into the present subject matter. Area

[0002] One embodiment of the present invention relates to a display device and a method for manufacturing a display device. background

[0003] For several years now, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. These display elements comprise a pixel circuit containing a thin-film transistor, a bottom electrode connected to the pixel circuit, an organic layer covering the bottom electrode, and an upper electrode covering the organic layer. In addition to an emitter layer, the organic layers also include functional layers such as a hole conduction layer and an electron conduction layer.

[0004] The manufacturing process for such a display element requires a technique to prevent a reduction in reliability. Brief description of the characters Fig. 1 is a view of an example design of a DSP display device. Fig. Figure 2 is a view showing an example of a layout of subpixels SP1, SP2, SP3. Fig. Figure 3 is a schematic sectional view of the DSP display device on line AB. Fig. 2. Fig. Figure 4 is a view showing an example of the design of display elements 201 to 203. Fig. Figure 5 is a schematic sectional view of the DSP display device on the CD line. Fig. 2. Fig. Figure 6 is a schematic sectional view of the DSP display device on line EF. Fig. 2. Fig. Figure 7 is an illustrative view of an EVA vapor deposition device. Fig. Figure 8 is an explanatory view of a vapor deposition device EVB. Fig. Figure 9 is an explanatory view of a manufacturing process for forming an upper electrode UE and an inorganic layer IL. Fig. Figure 10 is an illustrative view of another manufacturing process for forming the upper electrode UE and the inorganic layer IL. Fig. Figure 11 is an explanatory flowchart of an example of a method for manufacturing the DSP display device. Fig. Figure 12 is a view of an example of a manufacturing apparatus applicable to a step to form a first thin film 31, a step to form a second thin film 32 and a step to form a third thin film 33. Fig. Figure 13 is a view of another example of a manufacturing apparatus applicable to a step to form a first thin film 31, a step to form a second thin film 32 and a step to form a third thin film 33. Fig. Figure 14 is an explanatory view of a method for manufacturing the DSP display device. Fig. Figure 15 is an explanatory view of a method for manufacturing the DSP display device. Fig. Figure 16 is an explanatory view of a process for forming the first thin film 31. Fig. Figure 17 is an explanatory view of a method for manufacturing the DSP display device. Fig. Figure 18 is an explanatory view of a method for manufacturing the DSP display device. Fig. Figure 19 is an explanatory view of the process for removing the first thin film 31. Fig. Figure 20 is an explanatory view of a method for manufacturing the DSP display device. Detailed description

[0005] One embodiment has the objective of providing a display device that can prevent a decrease in reliability and a method for manufacturing the display device.

[0006] According to one embodiment, a method for manufacturing a display device comprises preparing a processing carrier by forming a lower electrode over a printed circuit board, forming a rib having an opening that overlays the lower electrode, forming a partition comprising a lower section located on the rib and an upper section located on the lower section and projecting from a side face of the lower section, forming an organic layer on the lower electrode at the opening, forming an upper electrode on the organic layer, forming a transparent layer on the upper electrode, and forming an inorganic layer on the transparent layer.wherein in the step of forming the upper electrode a first vaporization source is inclined with respect to a normal of the processing carrier and, as the processing carrier is transported, a material emitted from the first vaporization source is deposited, and wherein in the step of forming the inorganic layer a second vaporization source is inclined with respect to the normal of the processing carrier in a direction opposite to that of the first vaporization source and, as the processing carrier is transported, a material emitted from the second vaporization source is deposited.

[0007] A display device according to one embodiment comprises a carrier, a lower electrode arranged above the carrier, a rib having an opening that overlaps the lower electrode, a partition comprising a lower section arranged on the rib and an upper section arranged on the lower section and projecting from a side face of the lower section, an organic layer arranged at the opening on the lower electrode, an upper electrode arranged on the organic layer, a transparent layer arranged on the upper electrode, an inorganic layer arranged on the transparent layer, and a sealing layer covering the inorganic layer and adjoining the lower section of the partition, wherein the upper electrode has a first end section and a second end section opposite the first end section.wherein the first end section is covered by the inorganic layer and the second end section is exposed from the inorganic layer and covered by the sealing layer.

[0008] According to one embodiment, a display device that can prevent a decrease in reliability and a method for manufacturing the display device can be provided.

[0009] The following describes one embodiment with reference to the figures.

[0010] The disclosure is merely exemplary, and any modifications made by a person skilled in the art, while preserving the essence of the invention and readily arriving at them, are of course also included within the scope of the invention. The figures serve to clarify the description, and their individual components schematically represent width, thickness, shape, and the like in comparison to an actual embodiment; therefore, they are merely exemplary and are not intended to restrict the interpretation of the present invention. In this description and the figures, elements already mentioned with reference to another figure that perform an identical or similar function are designated with the same reference numerals, thus eliminating the need for a further detailed description.

[0011] For ease of understanding, the figures include X-axis, Y-axis, and Z-axis, which are orthogonal to each other. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis as the second direction, and the direction along the Z-axis as the third direction. Viewing the individual elements parallel to the third direction, Z, corresponds to a top-down view.

[0012] A display device according to the present embodiment is an organic electroluminescent display device comprising organic light-emitting diodes (OLEDs) as display elements and can be installed in television sets, PCs, on-board vehicle equipment, tablet devices, smartphones, mobile phones and the like.

[0013] Fig. 1 is a view of an example design of a DSP display device.

[0014] The display device DSP has a display area DA, in which images are displayed, and a non-display area SA around the display area DA, on an insulating carrier 10. The carrier 10 can be glass or a flexible plastic film.

[0015] In the present embodiment, the support 10 is rectangular in plan view. However, the shape of the support 10 in plan view is not limited to a rectangular shape and can also be another shape such as a square, a circle, or an oval.

[0016] The display area DA comprises pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX contains multiple subpixels SP. In one example, the pixels PX contain subpixel SP1 of a first color, subpixel SP2 of a second color, and subpixel SP3 of a third color. The first, second, and third colors are distinct. The pixels PX can contain subpixels SP of a different color, such as white, or alternatively, either in addition to or instead of any of the subpixels SP1, SP2, SP3.

[0017] The subpixel SP comprises a pixel circuit 1 and a display element 20 controlled by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a control transistor 3, and a capacitor 4. The pixel switch 2 and the control transistor 3 are switching elements, which are, for example, formed by thin-film transistors.

[0018] One gate electrode of pixel switch 2 is connected to a scanning line GL. One of the source and one of the drain electrodes of pixel switch 2 is connected to a signal line SL, and the other is connected to a gate electrode of the control transistor 3 and capacitor 4. In the case of the control transistor 3, one of the source and one of the drain electrodes is connected to a power supply line PL and capacitor 4, and the other is connected to an anode of the display element 20.

[0019] The design of pixel circuit 1 is not limited to the example shown. For example, pixel circuit 1 can include a larger number of thin-film transistors and capacitors.

[0020] The display element 20 is an organic light-emitting diode (OLED) serving as a light-emitting element, which is also referred to as an organic EL element.

[0021] Fig. Figure 2 is a view showing an example of a layout of subpixels SP1, SP2, SP3.

[0022] In the example from Fig. Subpixels SP2 and SP3 are aligned in the second direction Y. Furthermore, subpixels SP2 and SP3 are each aligned in the first direction X with subpixel SP1.

[0023] With such a layout of subpixels SP1, SP2, SP3, in the display area DA, a row is formed in which the subpixels SP2, SP3 are arranged alternately in the second direction Y, and a row is formed in which several subpixels SP1 are repeatedly arranged in the second direction Y. These rows are arranged alternately in the first direction X.

[0024] The layout of subpixels SP1, SP2, SP3 is not based on the example in Fig. 2 limited. As another example, the subpixels SP1, SP2, SP3 in the individual pixels PX can be arranged sequentially in the first direction X.

[0025] In the display area DA, a rib 5 and a partition 6 are arranged. The rib 5 has openings AP1, AP2, AP3 at the subpixels SP1, SP2, SP3.

[0026] In plan view, the partition 6 overlaps the rib 5. The partition 6 has several first partitions 6x extending in the first direction X and several second partitions 6y extending in the second direction Y. The multiple first partitions 6x are each arranged between openings AP2, AP3 adjacent in the second direction Y and between two openings AP1 adjacent in the second direction Y. The second partitions 6y are each arranged between openings AP1, AP2 adjacent in the first direction X and between openings AP1, AP3 adjacent in the first direction X.

[0027] In the example from Fig. The first partitions 6x and the second partitions 6y are connected to each other. In this way, partition 6 is formed as a grid shape that surrounds the openings AP1, AP2, and AP3. It is also possible that partition 6, like rib 5, has openings at subpixels SP1, SP2, and SP3.

[0028] The subpixels SP1, SP2, SP3 each comprise a display element 20, a display element 201, 202, 203 respectively.

[0029] Subpixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each superimposed on aperture AP1. Subpixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each superimposed on aperture AP2. Subpixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each superimposed on aperture AP3.

[0030] In the example from Fig. Figure 2 shows the outer shapes of the lower electrodes LE1, LE2, LE3 with dotted lines, while the outer shapes of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 are shown with dashed lines. A portion of the outer edge of each of the lower electrodes LE1, LE2, LE3 overlaps with rib 5. The outer shapes shown for the lower electrodes, organic layers, and upper electrodes do not necessarily reflect their exact form.

[0031] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 form the display element 201 of subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 form the display element 202 of subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 form the display element 203 of subpixel SP3.

[0032] The lower electrodes LE1, LE2, LE3 correspond, for example, to the anode of the indicator element. The upper electrodes UE1, UE2, UE3 correspond to the cathode or a common terminal of the indicator element.

[0033] The lower electrode LE1 is connected to the pixel circuit 1 of subpixel SP1 via a contact hole CH1 (see Fig. 1) connected. The lower electrode LE2 is connected to pixel circuit 1 of subpixel SP2 via a contact hole CH2. The lower electrode LE3 is connected to pixel circuit 1 of subpixel SP3 via a contact hole CH3.

[0034] In the example from Fig. 2. The surface area of ​​opening AP1 is larger than the surface area of ​​opening AP2, and the surface area of ​​opening AP2 is larger than the surface area of ​​opening AP3. In other words, the surface area of ​​the lower electrode LE1 exposed from opening AP1 is larger than the surface area of ​​the lower electrode LE2 exposed from opening AP2, and the surface area of ​​the lower electrode LE2 exposed from opening AP2 is larger than the surface area of ​​the lower electrode LE3 exposed from opening AP3.

[0035] For example, the indicator element 201 of subpixel SP1 is configured to emit light in the blue wavelength range. The indicator element 202 of subpixel SP2 is configured to emit light in the green wavelength range, and the indicator element 203 of subpixel SP3 is configured to emit light in the red wavelength range.

[0036] Fig. Figure 3 is a schematic sectional view of the DSP display device on line AB. Fig. 2.

[0037] Circuit layer 11 is arranged on the support 10 described above. Circuit layer 11 includes various types of wiring, such as circuits like pixel circuit 1. Fig. 1, the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 acts as a flattening layer, smoothing out any unevenness created by the circuit layer 11.

[0038] The lower electrodes LE1, LE2, and LE3 are arranged on the insulating layer 12. The rib 5 is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The end sections of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. Thus, the end sections of the lower electrodes LE1, LE2, and LE3 are located between the insulating layer 12 and the rib 5. At the lower electrodes LE1, LE2, and LE3 that are adjacent to each other, the insulating layer 12 is covered by the rib 5.

[0039] The partition 6 comprises a lower section (strut) 61 arranged on the rib 5 and an upper section (shield) 62 arranged on the lower section 61. The lower section 61 of the partition 6, shown on the left in the figure, is located between opening AP1 and opening AP2. The lower section 61 of the partition 6, shown on the right in the figure, is located between opening AP2 and opening AP3. The upper section 62 is wider than the lower section 61. This allows the openings to project into... Fig. 3. The two end sections of the upper section 62 project from the side surfaces of the lower section 61. Thus, the shape of the partition 6 can also be described as an overhang shape. The part of the upper section 62 that projects towards the opening AP1 relative to the lower section 61 is called the projection section 621, the part that projects towards the opening AP2 relative to the lower section 61 is called the projection section 622, and the part that projects towards the opening AP3 relative to the lower section 61 is called the projection section 623.

[0040] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1, and overlaps with part of the rib 5. The upper electrode UE1 is opposite the lower electrode LE1 and is located on the organic layer OR1. The upper electrode UE1 is also in contact with a side surface of the lower section 61. The organic layer OR1 and the upper electrode UE1 are located below the upper section 62.

[0041] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2, and overlaps with part of the rib 5. The upper electrode UE2 is opposite the lower electrode LE2 and is located on the organic layer OR2. The upper electrode UE2 is also in contact with a side surface of the lower section 61. The organic layer OR2 and the upper electrode UE2 are located below the upper section 62.

[0042] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3, and overlaps with part of the rib 5. The upper electrode UE3 is opposite the lower electrode LE3 and is located on the organic layer OR3. The upper electrode UE3 is also in contact with a side surface of the lower section 61. The organic layer OR3 and the upper electrode UE3 are located below the upper section 62.

[0043] The subpixels SP1, SP2, SP3 contain in the Fig. In the example shown, there is also a top layer (optical regulating layer) CP1, CP2, CP3 for adjusting the optical characteristics of the light emitted through the phosphor layer of the organic layers OR1, OR2, OR3.

[0044] The cover layer CP1 is located at opening AP1, below the upper section 62, and on the upper electrode UE1. The cover layer CP2 is located at opening AP2, below the upper section 62, and on the upper electrode UE2. The cover layer CP3 is located at opening AP3, below the upper section 62, and on the upper electrode UE3.

[0045] Sealing layers SE1, SE2, SE3 are arranged at each of the subpixels SP1, SP2, SP3.

[0046] The sealing layer SE1 borders the cover layer CP1 and the lower section 61 and the upper section 62 of the partition 6 and continuously covers the individual elements of subpixel SP1. The sealing layer SE2 borders the cover layer CP2 and the lower section 61 and the upper section 62 of the partition 6 and continuously covers the individual elements of subpixel SP2. The sealing layer SE3 borders the cover layer CP3 and the lower section 61 and the upper section 62 of the partition 6 and continuously covers the individual elements of subpixel SP3.

[0047] The sealing layers SE1, SE2, SE3 are covered by the protective layer 13.

[0048] In the Fig. In the 3 examples shown, a part of the organic layer OR1, a part of the upper electrode UE1 and a part of the cover layer CP1 are located between the partition wall 6 and the sealing layer SE1, arranged on the upper section 62 and away from a part below the upper section 62.

[0049] Part of the organic layer OR2, part of the upper electrode UE2 and part of the cover layer CP2 are located between the partition wall 6 and the sealing layer SE2, arranged on the upper section 62 and removed from a part below the upper section 62.

[0050] Part of the organic layer OR3, part of the upper electrode UE3 and part of the cover layer CP3 are located between the partition wall 6 and the sealing layer SE3, arranged on the upper section 62 and removed from a part below the upper section 62.

[0051] Insulation layer 12 is an organic insulation layer. Rib 5 and sealing layers SE1, SE2, SE3 are inorganic insulation layers.

[0052] The sealing layers SE1, SE2, SE3, for example, are made of the same inorganic material.

[0053] Rib 5 is made of silicon nitride (SiNx), which is an example of an inorganic material. Rib 5 can also be formed as a single-layer body from any other inorganic material such as silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3). Rib 5 can also be formed as a layered body from a combination of two or more silicon nitride layers, silicon oxide layers, silicon oxynitride layers, and aluminum oxide layers.

[0054] The sealing layers SE1, SE2, and SE3 are made of silicon nitride (SiNx), an example of an inorganic material. These sealing layers could also be formed as single-layer bodies made of any other inorganic material such as silicon dioxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Alternatively, they could be layered bodies consisting of a combination of two or more silicon nitride layers, silicon dioxide layers, silicon oxynitride layers, and aluminum oxide layers. Therefore, it is possible that the sealing layers SE1, SE2, and SE3 are made of the same material as rib 5.

[0055] The lower section 61 of the partition 6 is made of an electrically conductive material and is electrically connected to the individual upper electrodes UE1, UE2, UE3. Both the lower section 61 and the upper section 62 of the partition 6 can be electrically conductive.

[0056] The thickness of rib 5 is sufficiently small compared to the thickness of partition 6 and insulating layer 12. In one example, the thickness of rib 5 is at least 200 nm and at most 400 nm.

[0057] The thickness of the lower section 61 of the partition 6 (thickness from the upper surface of the rib 5 to the lower surface of the upper section 62) is greater than the thickness of the rib 5.

[0058] The thickness of the sealing layer SE1, the thickness of the sealing layer SE2 and the thickness of the sealing layer SE3 are approximately the same.

[0059] The lower electrodes LE1, LE2, LE3 can be made of a transparent, electrically conductive material such as ITO or the like, or they can have a layered structure consisting of a metallic material such as silver (Ag) or the like and a transparent, electrically conductive material. The upper electrodes UE1, UE2, UE3 are made of a metallic material such as a magnesium-silver alloy (MgAg). The upper electrodes UE1, UE2, UE3 can also be made of a transparent, electrically conductive material such as ITO or the like.

[0060] The organic layers OR1, OR2, and OR3 contain several functional layers, such as a hole injection layer, a hole conduction layer, an electron blocking layer, a hole blocking layer, an electron conduction layer, an electron injection layer, and the like. Organic layer OR1 contains a phosphor layer EM1. Organic layer OR2 contains a phosphor layer EM2. The phosphor layer EM2 is made of a different material than the phosphor layer EM1. Organic layer OR3 contains a phosphor layer EM3. The phosphor layer EM3 is made of a different material than the phosphor layers EM1 and EM2.

[0061] The material from which the luminescent layer EM1 is formed, the material from which the luminescent layer EM2 is formed, and the material from which the luminescent layer EM3 is formed, are materials that emit light in different wavelength ranges.

[0062] In one example, the luminescent layer EM1 is made of a material that emits light in the blue wavelength range, the luminescent layer EM2 is made of a material that emits light in the green wavelength range, and the luminescent layer EM3 is made of a material that emits light in the red wavelength range.

[0063] The cover layers CP1, CP2, and CP3, for example, are formed as multilayered bodies composed of transparent thin films. The multilayered body can include, as thin films, one thin film made of an inorganic material and one thin film made of an organic material. These multiple thin films have different refractive indices. The material of the thin films forming the multilayered body differs from the material of the upper electrodes UE1, UE2, and UE3, and from the material of the sealing layers SE1, SE2, and SE3. The cover layers CP1, CP2, and CP3 can also be omitted.

[0064] The protective layer 13 can be formed by the multilayer body from thin films and can include, as the thin films, a thin film formed from an inorganic material and a thin film formed from an organic material.

[0065] A common voltage is applied to the partition 6. This common voltage is applied to each of the individual upper electrodes UE1, UE2, UE3, which are in contact with the side surface of the lower section 61. A pixel voltage is applied to the lower electrodes LE1, LE2, LE3 via the respective pixel circuit 1 of the subpixels SP1, SP2, SP3.

[0066] When a potential difference exists between the lower electrode LEI and the upper electrode UE1, the phosphor layer EM1 on the organic layer OR1 emits light in the blue wavelength range. When a potential difference exists between the lower electrode LE2 and the upper electrode UE2, the phosphor layer EM2 on the organic layer OR2 emits light in the green wavelength range. When a potential difference exists between the lower electrode LE3 and the upper electrode UE3, the phosphor layer EM3 on the organic layer OR3 emits light in the red wavelength range.

[0067] Fig. Figure 4 shows an example of how the display elements 201 to 203 can be configured. The description is based on the example that the lower electrode corresponds to the anode and the upper electrode to the cathode.

[0068] The indicator element 201 includes the organic layer OR1 between the lower electrode LE1 and the upper electrode UE1.

[0069] The organic layer OR1 consists of a hole injection layer HIL1, a hole conduction layer HTL1, an electron blocking layer EBL1, the phosphor layer EM1, a hole blocking layer HBL1, an electron conduction layer ETL1 and an electron injection layer EIL1, layered on top of each other in this order.

[0070] The top layer CP1 comprises a transparent layer TL1 and an inorganic layer IL1. The transparent layer TL1 is arranged on the upper electrode UE1. The inorganic layer IL1 is arranged on top of the transparent layer TL1. The sealing layer SE1 is arranged on top of the inorganic layer IL1.

[0071] The indicator element 202 includes the organic layer OR2 between the lower electrode LE2 and the upper electrode UE2.

[0072] The organic layer OR2 consists of a hole injection layer HIL2, a hole conduction layer HTL2, an electron blocking layer EBL2, the phosphor layer EM2, a hole blocking layer HBL2, an electron conduction layer ETL2 and an electron injection layer EIL2, layered on top of each other in this order.

[0073] The top layer CP2 comprises a transparent layer TL2 and an inorganic layer IL2. The transparent layer TL2 is located on the upper electrode UE2. The inorganic layer IL2 is located on top of the transparent layer TL2. The sealing layer SE2 is located on top of the inorganic layer IL2.

[0074] The indicator element 203 includes the organic layer OR3 between the lower electrode LE3 and the upper electrode UE3.

[0075] The organic layer OR3 consists of a hole injection layer HIL3, a hole conduction layer HTL3, an electron blocking layer EBL3, the phosphor layer EM3, a hole blocking layer HBL3, an electron conduction layer ETL3 and an electron injection layer EIL3, layered on top of each other in this order.

[0076] The top layer CP3 comprises a transparent layer TL3 and an inorganic layer IL3. The transparent layer TL3 is located on the upper electrode UE3. The inorganic layer IL3 is located on top of the transparent layer TL3. The sealing layer SE3 is located on top of the inorganic layer IL3.

[0077] The transparent layers TL1, TL2, TL3 are, for example, organic layers made of organic material and have a high refractive index, meaning their refractive index is higher than that of the upper electrodes UE1, UE2, UE3. The inorganic layers IL1, IL2, IL3 are, for example, thin films made of lithium fluoride (LiF) and have a low refractive index, meaning their refractive index is lower than that of the transparent layers TL1, TL2, TL3.

[0078] The cover layers CP1, CP2, CP3 can be layered bodies with three or more layers.

[0079] The organic layers OR1, OR2, OR3 can, in addition to the functional layers described above, include further functional layers as needed, such as a support generation layer and the like; and at least one of the functional layers described above can also be omitted.

[0080] The functional layers described above are created individually for each display element 201 to 203. Therefore, the thickness of the functional layers described above may differ for each display element 201 to 203.

[0081] When considering the same functional layer, it is possible that in display elements 201 to 203 the functional layer of the display element is made of a different material than the functional layers of the other two display elements, or that the functional layers of all display elements 201 to 203 are made of different materials.

[0082] It is also possible that the layer composition of one display element 201 to 203 differs from the layer composition of the other two display elements, or that the layer composition of all display elements 201 to 203 is different. For example, when considering a functional layer, one display element 201 to 203 may not contain the layer in question, or only one display element 201 to 203 may contain the layer in question. Furthermore, the functional layer in question may be multilayered on one of the display elements 201 to 203.

[0083] The transparent layers TL1 to TL3 are separated from each other and formed separately. Therefore, it is possible that all transparent layers TL1 to TL3 are made of the same material, or that one of the transparent layers TL1 to TL3 is made of a different material than the other two, or that all transparent layers TL1 to TL3 are made of different materials. The thickness of the transparent layers TL1 to TL3 can be the same or different.

[0084] The inorganic layers IL1 to IL3 are separated from each other and formed separately. Therefore, it is possible that all inorganic layers IL1 to IL3 are made of the same material, or that one of the inorganic layers IL1 to IL3 is made of a different material than the other two, or that all inorganic layers IL1 to IL3 are made of different materials. The thickness of the inorganic layers IL1 to IL3 can be the same or different.

[0085] It is possible that the layer composition of all cover layers CP1 to CP3 is the same, or that the layer composition of one cover layer CP1 to CP3 differs from the layer composition of the other two cover layers, or that the layer composition of all cover layers CP1 to CP3 is different.

[0086] In the Fig. In the example shown, the upper electrode UE1 and the inorganic layer IL1 serve as etch stop layers on display element 201 during the dry etching of the sealing layer SE1. On display element 202, the upper electrode UE2 and the inorganic layer IL2 serve as etch stop layers during the dry etching of the sealing layer SE2. On display element 203, the upper electrode UE3 and the inorganic layer IL3 serve as etch stop layers during the dry etching of the sealing layer SE3.

[0087] When comparing the etching rate during dry etching of the etch-stop layer and the sealing layer under identical conditions, the etching rate of the etch-stop layer (top electrode and inorganic layer) is lower than the etching rate of the sealing layer. Therefore, when dry etching is performed on a layered body where the sealing layer is layered on top of the etch-stop layer, the sealing layer is removed, while the etching process at the etch-stop layer can be halted.

[0088] The upper electrodes UE1, UE2, UE3, which serve as etch stop layers, are made of a different material than rib 5 and are made of a different material than the sealing layers SE1, SE2, SE3. While rib 5 and the sealing layers SE1, SE2, SE3 are made of silicon nitride, the upper electrodes UE1, UE2, UE3 are made of a magnesium-silver alloy, a material that exhibits high resistance to dry etching compared to silicon nitride.

[0089] The upper inorganic layers IL1, IL2, and IL3, which serve as etch-stopping layers, are also made of a different material than rib 5 and are made of a different material than the sealing layers SE1, SE2, and SE3. While rib 5 and the sealing layers SE1, SE2, and SE3 are made of silicon nitride, the inorganic layers IL1, IL2, and IL3 are made of lithium fluoride, a material that exhibits high resistance to dry etching compared to silicon nitride.

[0090] Fig. Figure 5 is a schematic sectional view of the DSP display device on the CD line. Fig. 2. The section view from Fig. 5 contains several SP1 subpixels arranged side by side in the second direction Y. Fig. 5. The carrier, the circuit layer, and the protective layer were made of Fig. 3 omitted.

[0091] The subpixel SP1 located in the center of the figure is considered. On a YZ cross-sectional surface defined by the second direction Y and the third direction Z, the lower section 61 of the partition 6 has a side surface S1A and a side surface S1B that are opposite each other and enclose the subpixel SP1 between them. The side surface S1B extends along one side of the subpixel SP1 where the Fig. The contact hole CH1 shown in the image is provided.

[0092] On the organic layer OR1, the two end sections in the second direction Y are located on rib 5 and away from the side surfaces S1A and S1B. This means that rib 5 lies freely between the partition 6 and the organic layer OR1.

[0093] The upper electrode UE1 has an end section UE1B extending in the second direction Y opposite end section UE1A and end section UE1B. End section UE1A faces side surface S1A, and end section UE1B faces side surface S1B. The upper electrode UE1 covers the organic layer OR1 and, between the organic layer OR1 and the partition 6, covers the rib 5. In the example shown, the upper electrode UE1 borders side surfaces S1A and S1B. The contact area between the upper electrode UE1 and side surface S1B is larger than the contact area between the upper electrode UE1 and side surface S1A.

[0094] The cover layer CP1 is arranged on the upper electrode UE1. At least the inorganic layer IL1 on the cover layer CP1 covers the end section UE1A of the upper electrode UE1 and borders the side surface S1A. In the example shown, the inorganic layer IL1 exposes the end section UE1B of the upper electrode UE1 and is located away from the side surface S1B. The end section UE1B is covered by the sealing layer SE1.

[0095] The contact surface between side surface S1A and the inorganic layer IL1 is larger than the contact surface between side surface S1A and the upper electrode UE1. The contact surface between side surface S1B and the upper electrode UE1 is larger than the contact surface between side surface S1B and the inorganic layer IL1.

[0096] In this way, at least one of the upper electrode UE1 and the inorganic layer IL1 is located between the organic layer OR1 and the partition 6, between the rib 5 and the sealing layer SE1.

[0097] In the Fig. In example 5, the end section UE1A corresponds to the first end section, the end section UE1B to the second end section, the side surface S1A to the first side surface and the side surface S1B to the second side surface.

[0098] Fig. Figure 6 is a schematic sectional view of the DSP display device on line EF. Fig. 2. The section view from Fig. 6 contains subpixel SP2 and subpixel SP3, which are located next to each other in the second direction Y. Fig. 6. The carrier, the circuit layer, and the protective layer were made of Fig. 3 omitted.

[0099] The subpixel SP3, located on the left in the figure, is considered. At the YZ interface, the lower section 61 of the partition 6 has a side surface S3A and a side surface S3B, which are opposite each other and accommodate the subpixel SP3 between them. The side surface S3B runs along one side of the subpixel SP3, where the Fig. The contact hole CH3 shown in Figure 2 is provided. On the organic layer OR3, the two end sections in the second direction Y are located on rib 5 and away from the side surfaces S3A and S3B. That is, rib 5 lies freely between the partition 6 and the organic layer OR3.

[0100] The upper electrode UE3 has an end section UE3B extending in the second direction Y opposite end section UE3A and end section UE3B. End section UE3A faces side surface S3A, and end section UE3B faces side surface S3B. The upper electrode UE3 covers the organic layer OR3 and, between the organic layer OR3 and the partition 6, covers the rib 5. In the example shown, the upper electrode UE3 borders side surfaces S3A and S3B. The contact area between the upper electrode UE3 and side surface S3B is larger than the contact area between the upper electrode UE3 and side surface S3A.

[0101] The cover layer CP3 is arranged on the upper electrode UE3. At least the inorganic layer IL3 on the cover layer CP3 covers the end section UE3A of the upper electrode UE3 and borders the side surface S3A. In the example shown, the inorganic layer IL3 exposes the end section UE3B of the upper electrode UE3 and is located away from the side surface S3B. The end section UE3B is covered by the sealing layer SE3.

[0102] The contact surface between side surface S3A and the inorganic layer IL3 is larger than the contact surface between side surface S3A and the upper electrode UE3. The contact surface between side surface S3B and the upper electrode UE3 is larger than the contact surface between side surface S3B and the inorganic layer IL3.

[0103] In this way, at least one of the upper electrode UE3 and the inorganic layer IL3 is located between the organic layer OR3 and the partition 6, between the rib 5 and the sealing layer SE1.

[0104] When considering the subpixel SP2 located on the right in the figure, the two end sections in the second direction Y are located on the rib 5 of the organic layer OR2 and away from the partition 6.

[0105] The upper electrode UE2 covers the organic layer OR2, and the top layer CP2 is arranged on the upper electrode UE2. The upper electrode UE2 borders the middle partition 6 in the figure, and at least the inorganic layer IL2 (omitted from the figure) of the top layer CP2 borders the right-hand partition 6 in the figure.

[0106] In this way, at least one of the upper electrode UE2 and the inorganic layer IL2 is located between the organic layer OR2 and the partition 6, between the rib 5 and the sealing layer SE2.

[0107] Next, a vapor deposition device for forming an etch stop layer is described.

[0108] Fig. Figure 7 is an illustrative view of an EVA vapor deposition device.

[0109] The vapor deposition device EVA comprises a transport mechanism 100A, a vapor deposition source 110A, and a chamber 130A. The chamber 130A has a transport inlet 131A for transporting a processing carrier SUB into it and a transport outlet 132A for transporting the processing carrier SUB out of it. The manufacturing device for the display device described in this document is an inline device; therefore, the transport inlet 131A is connected to another vapor deposition device, and the transport outlet 132A is connected to yet another vapor deposition device.

[0110] The transport mechanism 100A is designed to transport the processing carrier SUB. The processing carrier SUB, for example, comprises the circuit layer 11, the insulation layer 12, the lower electrode LE, the rib 5, the partition 6, and the organic layer OR on the carrier 10. The transport mechanism 100A transports the processing carrier SUB from the transport input 131A to the transport output 132A. The transport direction TD of the processing carrier SUB is, for example, parallel to the second direction Y of the display device DSP.

[0111] The vapor deposition source 110A is configured to dispense a material MA to form an etch stop layer ES. The vapor deposition source 110A is housed in the chamber 130A and fixed within the chamber 130A by means of a support (not shown). The vapor deposition source 110A has a nozzle 120A for restricting the dispensing direction of the material MA. A dispensing opening 121A is formed at the front end of the nozzle 120A. The vapor deposition source 110A is inclined with respect to the normal N of the processing carrier SUB (or the normal of the carrier 10).

[0112] The vapor deposition source 110A shown in the figure is inclined to the right with respect to normal N. The discharge opening 121A is directed towards the transport inlet 131A. This means that the vapor deposition source 110A discharges the material MA in the direction opposite to the arrow indicating the transport direction TD of the processing carrier SUB. The inclination angle θA of the vapor deposition source 110A can be defined in a section plane defined by the transport direction TD of the processing carrier SUB and normal N of the processing carrier SUB as an angle formed by normal N and the extension direction of the nozzle 120A. The inclination angle θA of the vapor deposition source 110A is an acute angle clockwise with respect to normal N. The inclination angle θA is, for example, 5° or more and 40° or less.

[0113] In the vapor deposition device EVA, the following processing is carried out on the processing carrier SUB, which is transported into chamber 130A through the transport inlet 131A.

[0114] First, material MA is dispensed from the vapor deposition source 110A. While the transport mechanism 100A transports the processing carrier SUB, the processing carrier SUB is vapor-deposited with the material MA dispensed from the vapor deposition source 110A. The material MA dispensed from the vapor deposition source 110A is deposited on the organic layer OR and flows around the lower section 61 of the partition 6 on the left in the figure. In this way, the etch-stopper layer ES with the cross-sectional area shown by the dotted line is formed, and the rib 5 between the organic layer OR and the partition 6 is covered with the etch-stopper layer ES.

[0115] Fig. Figure 8 is an explanatory view of a vapor deposition device EVB.

[0116] The vapor deposition device EVB comprises a transport mechanism 100B, a vapor deposition source 110B and a chamber 130B. The chamber 130B has a transport inlet 131B for transporting the processing carrier SUB into it and a transport outlet 132B for transporting the processing carrier SUB out of it.

[0117] The in Fig. The vapor deposition device EVB shown in section 8 differs from the one shown in [reference missing]. Fig. 7 of the vapor deposition device EVA, that the vapor deposition source 110B is inclined in the direction opposite to the vapor deposition source 110A with respect to the normal N of the processing carrier SUB.

[0118] The vapor deposition source 110B is designed to blast a material MB to form the etch stop layer ES. The vapor deposition source 110B is housed in chamber 130B and fixed in chamber 130B by means of a holder (not shown). The vapor deposition source 110B has a nozzle 120B for restricting the discharge direction of the material MB. A discharge opening 121B is formed at the front end of the nozzle 120B.

[0119] The vapor deposition source 110B shown in the figure is inclined to the left with respect to the normal N. The discharge opening 121B is directed towards the transport outlet 132B. That is, the vapor deposition source 110B discharges the material MB in the direction of the arrow indicating the transport direction TD of the processing carrier SUB. The inclination angle θB of the vapor deposition source 110B can be defined in a section plane defined by the transport direction TD of the processing carrier SUB and the normal N of the processing carrier SUB as an angle formed by the normal N and the extension direction of the nozzle 120B. The inclination angle θB of the vapor deposition source 110B is an acute angle counterclockwise with respect to the normal N. The inclination angle θB is, for example, 5° or more and 40° or less.

[0120] In the vapor deposition device EVB, the following processing is carried out on the processing carrier SUB, which is transported into chamber 130B through the transport inlet 131B.

[0121] First, material MB is dispensed from the vapor deposition source 110B. While the transport mechanism 100B moves the processing carrier SUB, the processing carrier SUB is coated with the material MB dispensed from the vapor deposition source 110B. The material MB dispensed from the vapor deposition source 110B is deposited on the organic layer OR and flows around the lower section 61 of the partition 6 on the right side of the figure. In this way, the etch-stopper layer ES with the cross-sectional area shown by the dotted line is formed, and the rib 5 between the organic layer OR and the partition 6 is covered with the etch-stopper layer ES.

[0122] Fig. Figure 9 is an explanatory view of a manufacturing process for forming an upper electrode UE and an inorganic layer IL.

[0123] In the example shown, the Fig. Eva, the vapor deposition device shown in section 7, corresponds to the first vapor deposition source 110A and is located upstream in the transport direction TD. The in Fig. The vapor deposition device EVB shown in Figure 8 comprises vapor deposition source 110B, corresponding to the second vapor deposition source, and is located downstream in the transport direction TD. Vapor deposition source 110A and vapor deposition source 110B are each inclined as described above, but in opposite directions.

[0124] In the vapor deposition device EVA, the upper electrode UE is formed; in the vapor deposition device EVB, the inorganic layer IL is formed; and between the vapor deposition devices EVA and EVB, the transparent layer TL is formed. The material MA emitted by vapor deposition source 110A is therefore an alloy of magnesium and silver, and the material MB emitted by vapor deposition source 110B is lithium fluoride.

[0125] The processing carrier SUB has one end SUBA and another end SUBB, which are opposite each other in the direction in which the subpixels SP2 and SP3 are arranged next to each other. The transport direction TD of the processing carrier SUB is parallel to the direction in which the subpixels SP2 and SP3 are arranged next to each other.

[0126] When the upper electrode UE1, the transparent layer TL1, and the inorganic layer IL1 of subpixel SP1 are formed, the processing carrier SUB is transported with one end SUBA as the front end. First, the upper electrode UE1 is formed in the vapor deposition unit EVA. After the transparent layer TL1 has been formed, the inorganic layer IL1 is formed in the vapor deposition unit EVB.

[0127] Even when the upper electrode UE3, the transparent layer TL3 and the inorganic layer IL3 of the subpixel SP3 are formed, the processing carrier SUB is transported with one end SUBA as the front end.

[0128] When the upper electrode UE2, the transparent layer TL2, and the inorganic layer IL2 of subpixel SP2 are formed, the processing carrier SUB is transported with the other end SUBB as the front end. First, the upper electrode UE2 is formed in the vapor deposition unit EVA. After the transparent layer TL2 has been formed, the inorganic layer IL2 is formed in the vapor deposition unit EVB.

[0129] Fig. Figure 10 is an illustrative view of another manufacturing process for forming the upper electrode UE and the inorganic layer IL.

[0130] In the example shown, the Fig. The vapor deposition device EVB shown in section 8 corresponds to the first vapor deposition source 110B and is located upstream in the transport direction TD. The in Fig. The vapor deposition device EVA shown in section 7 comprises the vapor deposition source 110A corresponding to the second vapor deposition source and is located downstream in the transport direction TD. The upper electrode UE is formed in the vapor deposition device EVB, and the inorganic layer IL is formed in the vapor deposition device EVA. The material MB emitted by vapor deposition source 110B is therefore an alloy of magnesium and silver, and the material MA emitted by vapor deposition source 110A is lithium fluoride.

[0131] When the upper electrode UE1, the transparent layer TL1, and the inorganic layer IL1 of subpixel SP1 are formed, the processing carrier SUB is transported with the other end SUBB as the front end. First, the upper electrode UE1 is formed in the vapor deposition unit EVB. After the transparent layer TL1 has been formed, the inorganic layer IL1 is formed in the vapor deposition unit EVA.

[0132] Even when the upper electrode UE3, the transparent layer TL3 and the inorganic layer IL3 of the subpixel SP3 are formed, the processing carrier SUB is transported with the other end SUBB as the front end.

[0133] When the upper electrode UE2, the transparent layer TL2, and the inorganic layer IL2 of subpixel SP2 are formed, the processing carrier SUB is transported with one end SUBA as the front end. First, the upper electrode UE2 is formed in the vapor deposition unit EVB. After the transparent layer TL2 has been formed, the inorganic layer IL2 is formed in the vapor deposition unit EVA.

[0134] The vapor deposition devices EVA and EVB of the in Fig. 7 to Fig. The example shown in Figure 10 corresponds to a configuration in which the processing carrier SUB is transported in a state where the vapor deposition surface of the processing carrier SUB is located above the carrier 10 (facing upwards) and the vapor deposition sources 110A and 110B discharge the material MA and MB downwards, but this configuration is not the only limitation. The vapor deposition devices EVA and EVB can also be configured such that the processing carrier SUB is transported in a state where the vapor deposition surface of the processing carrier SUB is located below the carrier 10 (facing downwards) and the vapor deposition sources 110A and 110B discharge the material MA and MB upwards.The vapor deposition devices EVA and EVB can also be designed to transport the processing carrier SUB in a vertically upright state with respect to the horizontal plane, and the vapor deposition sources 110A and 110B can discharge the material MA and MB horizontally.

[0135] Next, an example of a method for manufacturing the DSP display device will be described.

[0136] Fig. Figure 11 is an explanatory flowchart of an example of a method for manufacturing the DSP display device.

[0137] The manufacturing process shown here roughly includes a step in which the processing carrier SUB is prepared with the subpixel SP1, the subpixel SP2 and the subpixel SP3 (step ST1), a step in which the display element 201 of the subpixel SP1 is formed (step ST2), a step in which the display element 202 of the subpixel SP2 is formed (step ST3), and a step in which the display element 203 of the subpixel SP3 is formed (step ST4).

[0138] In step ST1, the processing carrier SUB is first prepared by forming the lower electrode LE1 of subpixel SP1, the lower electrode LE2 of subpixel SP2, the lower electrode LE3 of subpixel SP3, the rib 5, and the partition 6 on the carrier 10. As in Fig. As shown in Figure 3, the circuit layer 11 and the insulation layer 12 are also formed between the carrier 10 and the lower electrodes LE1, LE2, LE3.

[0139] In step ST2, the first thin layer 31, which contains the phosphor layer EM1, is formed spanning subpixels SP1, SP2, and SP3 (step ST21). Then, a first resist 41, structured with a defined shape, is formed on the first thin layer 31 (step ST22). Next, a portion of the first thin layer 31 is removed by etching using the first resist 41 as a mask (step ST23). Finally, the first resist 41 is removed (step ST24). In this way, subpixel SP1 is formed. Subpixel SP1 comprises the display element 201, which has the first thin layer 31 in a defined shape.

[0140] In step ST3, the second thin layer 32, which contains the phosphor layer EM2, is first formed spanning subpixels SP1, SP2, and SP3 (step ST31). Then, a second resist 42, structured with a defined shape, is formed on the second thin layer 32 (step ST32). Next, a portion of the second thin layer 32 is removed by etching using the second resist 42 as a mask (step ST33). Finally, the second resist 42 is removed (step ST34). In this way, subpixel SP2 is formed. Subpixel SP2 comprises the display element 202, which has the second thin layer 32 in a defined shape.

[0141] In step ST4, the third thin layer 33, which contains the phosphor layer EM3, is first formed spanning subpixels SP1, SP2, and SP3 (step ST41). Then, a third resist 43, structured with a defined shape, is formed on the third thin layer 33 (step ST42). Next, a portion of the third thin layer 33 is removed by etching using the third resist 43 as a mask (step ST43). Finally, the third resist 43 is removed (step ST44). In this way, subpixel SP3 is formed. Subpixel SP3 comprises the display element 203, which has the third thin layer 33 in a defined shape.

[0142] Details of the second thin film 32, the second resist 42, the third thin film 33 and the third resist 43 have been omitted from the illustration.

[0143] Fig. Figure 12 is a view of an example of a manufacturing apparatus applicable to a step to form a first thin film 31, a step to form a second thin film 32 and a step to form a third thin film 33.

[0144] The processing carrier SUB, prepared by step ST1, is transported with one end SUBA as the front end.

[0145] First, the processing carrier SUB is transported into a vapor deposition device 301. The hole injection layer HIL1 is formed in the vapor deposition device 301.

[0146] Subsequently, the perforated conductor layer HTL1 is formed in a vapor deposition device 302.

[0147] Then, in a vapor deposition device 303, the electron blocking layer EBL1 is formed.

[0148] The luminescent layer EM1 is then formed in a vapor deposition device 304.

[0149] Then, in a vapor deposition device 305, the hole-blocking layer HBL1 is formed.

[0150] Then, in a vapor deposition device 306, the electron conduction layer ETL1 is formed.

[0151] Subsequently, the electron injection layer EIL1 is formed in a vapor deposition device 307. In this way, the organic layer OR1 is formed.

[0152] Then in the Fig. The upper electrode UE1 is formed in the vapor deposition device EVA1 shown in 9.

[0153] Subsequently, the transparent layer TL1 is formed in a vapor deposition device 308.

[0154] Then in the Fig. In the vapor deposition device EVB1 shown in Figure 9, the inorganic layer IL1 is formed. In this way, the top layer CP1 is formed.

[0155] Then, in a CVD (Chemical Vapor Deposition) device 309, the sealing layer SE1 is formed.

[0156] After completing the in Fig. In steps ST22 to ST24, shown in Figure 11, the processing carrier SUB is transported into the vapor deposition device 311 with one end SUBA as the front end. The hole injection layer HIL2 is formed in the vapor deposition device 311.

[0157] Subsequently, the perforated conductor layer HTL2 is formed in a vapor deposition device 312.

[0158] Then, in a vapor deposition device 313, the electron blocking layer EBL2 is formed.

[0159] The luminescent layer EM2 is then formed in a vapor deposition device 314.

[0160] Then, in a vapor deposition device 315, the hole-blocking layer HBL2 is formed.

[0161] Then, in a vapor deposition device 316, the electron conduction layer ETL2 is formed.

[0162] Subsequently, the electron injection layer EIL2 is formed in a vapor deposition device 317. In this way, the organic layer OR2 is formed.

[0163] Then in the Fig. The upper electrode UE2 is formed in the vapor deposition device EVB2 shown in 10.

[0164] Subsequently, the transparent layer TL2 is formed in a vapor deposition device 318.

[0165] Then in the Fig. In the vapor deposition device EVA2 shown in 10, the inorganic layer IL2 is formed. In this way, the top layer CP2 is formed.

[0166] Then, in a CVD device 319, the sealing layer SE2 is formed.

[0167] After completing the in Fig. In steps ST32 to ST34, shown in Figure 11, the processing carrier SUB is transported into the vapor deposition device 321 with one end SUBA as the front end. The hole injection layer HIL3 is formed in the vapor deposition device 321.

[0168] Subsequently, the perforated conductor layer HTL3 is formed in a vapor deposition device 322.

[0169] Then, in a vapor deposition device 323, the electron blocking layer EBL3 is formed.

[0170] The luminescent layer EM3 is then formed in a vapor deposition device 324.

[0171] Then, in a vapor deposition device 325, the hole-blocking layer HBL3 is formed.

[0172] Then, in a vapor deposition device 326, the electron conduction layer ETL3 is formed.

[0173] Subsequently, the electron injection layer EIL3 is formed in a vapor deposition device 327. In this way, the organic layer OR3 is formed.

[0174] Then in the Fig. The upper electrode UE3 is formed in the vapor deposition device EVA3 shown in 9.

[0175] Subsequently, the transparent layer TL3 is formed in a vapor deposition device 328.

[0176] Then in the Fig. In the vapor deposition device EVB3 shown in Figure 9, the inorganic layer IL3 is formed. In this way, the top layer CP3 is formed.

[0177] Then, in a CVD device 329, the sealing layer SE3 is formed.

[0178] Then the in Fig. The 11 steps shown, ST42 to ST44, were carried out.

[0179] The combination of the vapor deposition device EVA1 and the vapor deposition device EVB1 and the combination of the vapor deposition device EVA3 and the vapor deposition device EVB3 are identical to that described in Fig. 9 shown combination of the vapor deposition device EVA and the vapor deposition device EVB.

[0180] The combination of the vapor deposition device EVB2 and the vapor deposition device EVA2 is identical to that in Fig. 10 combination of the vapor deposition device EVB and the vapor deposition device EVA shown.

[0181] Fig. Figure 13 is a view of another example of a manufacturing apparatus applicable to a step to form a first thin film 31, a step to form a second thin film 32 and a step to form a third thin film 33.

[0182] The processing carrier SUB, prepared by step ST1, is placed on a rotary table TT and transported with one end SUBA as the front end.

[0183] First, the processing carrier SUB is transported into a vapor deposition device 301. The hole injection layer HIL1 is formed in the vapor deposition device 301.

[0184] Subsequently, the perforated conductor layer HTL1 is formed in a vapor deposition device 302.

[0185] Then, in a vapor deposition device 303, the electron blocking layer EBL1 is formed.

[0186] The luminescent layer EM1 is then formed in a vapor deposition device 304.

[0187] Vaporizing devices 314 and 324 allow the processing carrier SUB to pass through without releasing any material.

[0188] Then, in a vapor deposition device 305, the hole-blocking layer HBL1 is formed.

[0189] Then, in a vapor deposition device 306, the electron conduction layer ETL1 is formed.

[0190] Subsequently, the electron injection layer EIL1 is formed in a vapor deposition device 307. In this way, the organic layer OR1 is formed.

[0191] Then in the Fig. The upper electrode UE1 is formed in the vapor deposition device EVA shown in 9.

[0192] Subsequently, the transparent layer TL1 is formed in a vapor deposition device 308.

[0193] Then in the Fig. In the vapor deposition device EVB shown in section 9, the inorganic layer IL1 is formed. In this way, the top layer CP1 is formed.

[0194] Then, in a CVD device 309, the sealing layer SE1 is formed.

[0195] After completing the in Fig. In steps ST22 to ST24, as shown in 11, the processing carrier SUB is positioned on the rotary table TT, with the other end SUBB positioned as the front end and transported.

[0196] The processing carrier SUB is transported back into the vapor deposition device 301. The hole injection layer HIL2 is formed in the vapor deposition device 301.

[0197] Subsequently, the perforated conductor layer HTL2 is formed in the vapor deposition device 302.

[0198] Then the electron blocking layer EBL2 is formed in the vapor deposition device 303.

[0199] The luminescent layer EM2 is then formed in a vapor deposition device 314. Vapor deposition devices 304 and 324 allow the processing carrier SUB to pass through without releasing any material.

[0200] Then the hole-blocking layer HBL2 is formed in the vapor deposition device 305.

[0201] Then the electron conduction layer ETL2 is formed in the vapor deposition device 306.

[0202] Subsequently, the electron injection layer EIL2 is formed in the vapor deposition device 307. In this way, the organic layer OR2 is formed.

[0203] Then the upper electrode UE2 is formed in the vapor deposition device EVA.

[0204] The transparent layer TL2 is then formed in the vapor deposition device 308.

[0205] Then, in the vapor deposition device EVB, the inorganic layer IL2 is formed. In this way, the top layer CP2 is formed.

[0206] Then, in a CVD device 309, the sealing layer SE2 is formed.

[0207] After completing the... in Fig. In steps ST32 to ST34, shown in 11, the processing carrier SUB is arranged on the rotary table TT, with one end SUBA positioned as the front end and transported.

[0208] The processing carrier SUB is transported back into the vapor deposition device 301. The hole injection layer HIL3 is formed in the vapor deposition device 301.

[0209] Subsequently, the perforated conductor layer HTL3 is formed in the vapor deposition device 302.

[0210] Then the electron blocking layer EBL3 is formed in the vapor deposition device 303.

[0211] The luminescent layer EM3 is then formed in a vapor deposition device 324.

[0212] Vaporizing devices 304 and 314 allow the processing carrier SUB to pass through without releasing any material.

[0213] Then the hole-blocking layer HBL3 is formed in the vapor deposition device 305.

[0214] Then the electron conduction layer ETL3 is formed in the vapor deposition device 306.

[0215] Subsequently, the electron injection layer EIL3 is formed in the vapor deposition device 307. In this way, the organic layer OR3 is formed.

[0216] Then the upper electrode UE3 is formed in the vapor deposition device EVA.

[0217] The transparent layer TL3 is then formed in the vapor deposition device 308.

[0218] Then, in the vapor deposition device EVB, the inorganic layer IL3 is formed. In this way, the top layer CP3 is formed.

[0219] Then, in a CVD device 309, the sealing layer SE3 is formed.

[0220] Then the in Fig. The 11 steps shown, ST42 to ST44, were carried out.

[0221] Steps ST1 and ST2 are described with reference to Fig. 14 to Fig. 20 described. The in Fig. 14, Fig. 15, Fig. 17, Fig. 18 and Fig. The 20 shown cross-sectional areas correspond, for example, to the cross-sectional area at line AB in Fig. 2.

[0222] In step ST1, as in Fig. Figure 14 shows the processing carrier SUB being prepared. The step of preparing the processing carrier SUB comprises a step to form the circuit layer 11 on the carrier 10, a step to form the insulation layer 12 on the circuit layer 11, a step to form the lower electrode LE1 of subpixel SP1, the lower electrode LE2 of subpixel SP2, and the lower electrode LE3 of subpixel SP3 on the insulation layer 12, a step to form the rib 5, which has the openings AP1, AP2, AP3, each overlapping the lower electrodes LE1, LE2, LE3, and a step to form the partition 6, which includes the lower section 61 arranged on the rib 5 and the upper section 62 arranged on the lower section 61 and projecting from the side face of the lower section 61. Fig. 15, Fig. 17, Fig. 18 and Fig. In Figure 20, the representation of the layers of the carrier 10 and the circuit layer 11 below the insulation layer 12 was omitted.

[0223] Rib 5, for example, is made of silicon nitride.

[0224] Then, as in Fig. Figure 15 shows that in step ST21, the first thin film 31 is formed spanning subpixels SP1, SP2, and SP3. The step for forming the first thin film 31 includes a step for forming the organic layer OR1, which contains the phosphor layer EM1, on the substrate SUB; a step for forming the upper electrode UE1 on the organic layer OR1; a step for forming the top layer CP1 on the upper electrode UE1; and a step for forming the sealing layer SE1 on the top layer CP1. In the example shown, the first thin film 31 thus includes the organic layer OR1, the upper electrode UE1, the top layer CP1, and the sealing layer SE1.

[0225] The organic layer OR1 is formed on the lower electrode LE1, the lower electrode LE2, and the lower electrode LE3, and also on the partition 6. The portion of the organic layer OR1 formed on the upper section 62 is separated from the portion formed on the individual lower electrodes.

[0226] The upper electrode UE1 is formed directly above the lower electrodes LE1, LE2, and LE3 on the organic layer OR1, covers rib 5, and borders the lower section 61 of the partition 6. The upper electrode UE1 is also formed directly above the upper section 62 on the organic layer OR1. The portion of the upper electrode UE1 formed directly above the upper section 62 is separated from the portion formed directly above the lower individual electrodes.

[0227] The cover layer CP1 comprises the transparent layer TL1 and the inorganic layer IL1, which are not shown. The cover layer CP1 is formed directly above the lower electrode LE1, the lower electrode LE2, and the lower electrode LE3 on the upper electrode UE1, and is also formed directly above the upper section 62 on the upper electrode UE1. The portion of the cover layer CP1 formed directly above the upper section 62 is separated from the portion formed directly above the individual lower electrodes.

[0228] The sealing layer SE1 is formed in such a way that it covers the top layer CP1 and the partition wall 6. That is, the sealing layer SE1 is formed directly above the lower electrode LE1, the lower electrode LE2, and the lower electrode LE3 on the top layer CP1, and is also formed directly above the upper section 62 on the top layer CP1. The portion of the sealing layer SE1 formed directly above the upper section 62 is in contact with the portion formed directly above the lower electrodes. The sealing layer SE1 is formed, for example, from silicon nitride.

[0229] Fig. Figure 16 is an illustrative view of a process for forming the first thin film 31. Here, an example of the process for forming the first thin film 31 on the lower electrode LE1 is described. The cross-sectional areas of the first thin film 31 on the lower electrode LE1 are arranged in the figure from left to right in the order of formation.

[0230] First, the organic layer OR1 is formed on the lower electrode LE1. The organic layer OR1 contains, as described in [reference], Fig. Section 4 describes various functional layers and the luminescent layer. The individual layers of the organic layer OR1 are formed using a vacuum evaporation process.

[0231] Then the upper electrode UE1 is formed on the organic layer OR1. The upper electrode UE1 is formed from a magnesium-silver alloy using a vacuum vapor deposition process. The upper electrode UE1 can be described in the following with reference to Fig. 7 described vapor deposition device EVA or in the with reference to Fig. The vapor deposition device EVB described in section 8 is formed.

[0232] Then, the transparent layer TL1 of the top layer CP1 is formed on the upper electrode UE1. The transparent layer TL1 is formed, for example, using a vacuum evaporation process.

[0233] Then, the inorganic layer IL1 of the top layer CP1 is formed on the transparent layer TL1. The inorganic layer IL1 is formed from lithium fluoride using a vacuum evaporation process.

[0234] Then, the sealing layer SE1 is formed on the inorganic layer IL1. The sealing layer SE1 is formed, for example, using the CVD process.

[0235] Then, in step ST22, as described in Fig. As shown in Figure 17, the structured first resist 41 is formed on the sealing layer SE1. The first resist 41 covers the first thin layer 31 of subpixel SP1 and exposes the first thin layer 31 of subpixels SP2 and SP3. The first resist 41 thus overlays the sealing layer SE1, which is located directly above the lower electrode LE1. The first resist 41 extends from subpixel SP1 across the partition 6. On the partition 6 between subpixel SP1 and subpixel SP2, the first resist 41 is located on the side of subpixel SP1 (left in the figure), and the sealing layer SE1 is exposed on the side of subpixel SP2 (right in the figure). The first resist 41 exposes the sealing layer SE1 at subpixels SP2 and SP3.

[0236] Then in step ST23, as in Fig. Figure 18 shows that etching is performed with the first resist 41 as a mask. The first thin layer 31 of subpixels SP2 and SP3, exposed by the first resist 41, is removed, while the first thin layer 31 of subpixel SP1 remains. This exposes the lower electrode LE2 at subpixel SP2, and the rib 5 surrounding the lower electrode LE2 is exposed. At subpixel SP3, the lower electrode LE3 is exposed, and the rib 5 surrounding the lower electrode LE3 is exposed. At the partition 6 between subpixels SP1 and SP2, the side of subpixel SP2 is exposed. The partition 6 between subpixels SP2 and SP3 is also exposed.

[0237] Fig. Figure 19 is an illustrative view of the process for removing the first thin film 31. Here, an example of the procedure for removing the first thin film 31 formed on the lower electrode LE2 of subpixel SP2 is described. The cut surfaces of the first thin film 31 on the lower electrode LE2 are arranged in the figure from left to right in the order of removal.

[0238] First, dry etching is performed using the first Resist 41 as a mask, and the sealing layer SE1 exposed from the first Resist 41 is removed.

[0239] Then, using the first Resist 41 as a mask, wet application is carried out and the inorganic layer IL1 of the top layer CP1, exposed from the sealing layer SE1, is removed.

[0240] Then, dry etching is performed using the first resist 41 as a mask, and the transparent layer TL1 of the top layer CP1 exposed from the inorganic layer IL1 is removed.

[0241] Then, wet sampling is performed with the first Resist 41 as a mask, and the upper electrode UE1 exposed from the transparent layer TL1 is removed.

[0242] Then, using the first resist 41 as a mask, dry etching is performed, removing the organic layer OR1 exposed from the upper electrode UE1 and exposing the lower electrode LE2.

[0243] Likewise, the sealing layer SE1, the cover layer CP1, the upper electrode UE1 and the organic layer OR1 are removed from the subpixel SP3.

[0244] Then in step ST24, as in Fig. Figure 20 shows the removal of the first resist 41. This exposes the sealing layer SE1 of subpixel SP1. During steps ST21 to ST24, the display element 201 is formed on subpixel SP1. The display element 201 consists of the lower electrode LE1, the organic layer OR1 (which includes the phosphor layer EM1), the upper electrode UE1, and the cover layer CP1. The display element 201 is covered by the sealing layer SE1.

[0245] On the partition 6 between subpixel SP1 and subpixel SP2, a layered body is formed consisting of the organic layer OR1, which includes the luminescent layer EM1, the upper electrode UE1, the cover layer CP1, and the sealing layer SE1. The part of the partition 6 located on the side of subpixel SP1 is covered by the sealing layer SE1. It is also possible that the in Fig. The layered body shown on partition wall 6 is completely removed.

[0246] According to the present method, before the sealing layer SE1 is etched, at least one of the subpixels SP2 and SP3 is covered by the upper electrode UE1 and the inorganic layer IL1 of the cover layer CP1 between the partition 6 and the organic layer OR1 by the rib 5. Therefore, the sealing layer SE1 does not abut the rib 5. The upper electrode UE1 and the inorganic layer IL1 serve as an etch stop layer, and the etching rate of the upper electrode UE1 and the inorganic layer IL1 is lower than the etching rate of the sealing layer SE1. During dry etching of the sealing layer SE1, the sealing layer SE1 is therefore completely removed, whereupon the progress of the dry etching can be stopped at the upper electrode UE1 or the inorganic layer IL1. Therefore, during dry etching of the sealing layer SE1, the rib 5 is hardly damaged.The formation of unwanted holes (moisture penetration paths) that extend from rib 5 to insulation layer 12 is also prevented. Furthermore, discoloration of the lower electrode due to unwanted moisture is prevented. Finally, the formation of pixel defects, where the organic EL element fails to emit light due to damage to the organic EL element or the anode, is prevented.

[0247] This prevents a reduction in reliability.

[0248] As described above, according to the embodiment, an indicator device with which a decrease in reliability can be prevented and the production yield increased, and a method for manufacturing the same, can be provided.

[0249] Display devices and their manufacturing methods, which the person skilled in the art can obtain by suitable modification on the basis of the display device described as an embodiment of the present invention and its manufacturing method, also fall within the scope of the present invention, as long as they contain the core of the invention.

[0250] Within the framework of the basic concept of the present invention, a person skilled in the art can arrive at various modified examples, and these modified examples are also to be understood as falling within the scope of the present invention. For example, in the embodiment described above, a person skilled in the art can, as required, add, omit, or modify structural elements, or add, omit, or modify the conditions of steps, and all such modifications also fall within the scope of the present invention, as long as they contain the core of the invention.

[0251] Other effects resulting from the discussed aspects of the above embodiment, whether obvious from the description or achieved through considerations of the person skilled in the art, are of course also considered to be brought about by the present invention. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2022074873

[0001]

Claims

[1] Method for manufacturing a display device, comprising: Preparing a carrier by forming a bottom electrode over a printed circuit board, forming a rib having an opening that overlays the bottom electrode, and forming a partition comprising a bottom section located on the rib and an upper section located on the bottom section and projecting from a side face of the bottom section. Formation of an organic layer on the lower electrode at the opening, Formation of an upper electrode on the organic layer, Forming a transparent layer on the upper electrode and Formation of an inorganic layer on the transparent layer, wherein in the step of forming the upper electrode a first vaporization source is inclined with respect to a normal of the processing carrier and, while transporting the processing carrier, a material emitted from the first vaporization source is vaporized, and wherein in the step of forming the inorganic layer a second vaporization source is inclined in a direction opposite to the first vaporization source with respect to the normal of the processing carrier and material emitted from the second vaporization source is vaporized while the processing carrier is transported. [2] Method for manufacturing a display device according to claim 1, further comprising forming an inorganic layer on the sealing layer, Forming a structured resist on the sealing layer and Performing dry etching of the sealing layer using the resist as a mask, where, during dry etching of the sealing layer, the etching rate of the upper electrode and the inorganic layer is lower than the etching rate of the sealing layer. [3] Method for manufacturing a display device according to claim 2, wherein the rib and the sealing layer are formed from silicon nitride. [4] Method for manufacturing a display device according to claim 3, wherein the upper electrode is formed from an alloy of magnesium (Mg) and silver (Ag). [5] Method for manufacturing a display device according to claim 4, wherein the inorganic layer is formed from lithium fluoride (LiF). [6] Display device, comprising: a carrier a lower electrode positioned above the support, a rib that has an opening which overlaps the lower electrode, a partition wall comprising a lower section which is arranged on the rib and an upper section which is arranged on the lower section and projects from a side face of the lower section, an organic layer located at the opening on the lower electrode, an upper electrode positioned on the organic layer, a transparent layer that is arranged on the upper electrode, an inorganic layer arranged on top of the transparent layer, and a sealing layer that covers the inorganic layer and adjoins the lower section of the partition wall, wherein the upper electrode has a first end section and a second end section opposite the first end section, wherein the first end section is covered by the inorganic layer and the second end section is exposed from the inorganic layer and covered by the sealing layer. [7] Display device according to claim 6, wherein the lower section of the partition has a first side surface facing the first end section and a second side surface facing the second end section, wherein the inorganic layer borders the first side surface, and where the upper electrode borders the second side surface. [8] Display device according to claim 7, wherein a contact surface between the first side surface and the inorganic layer is larger than a contact surface between the first side surface and the upper electrode and a contact surface between the second side surface and the upper electrode is larger than a contact surface between the second side surface and the inorganic layer. [9] Display device according to claim 6, wherein the organic layer is removed from the partition, wherein at least one of the upper electrode and the inorganic layer is located between the rib and the sealing layer between the organic layer and the partition. [10] Display device according to claim 6, wherein the rib and the sealing layer are formed from silicon nitride. [11] Display device according to claim 6, wherein the upper electrode is formed from an alloy of magnesium (Mg) and silver (Ag). [12] Display device according to claim 6, wherein the inorganic layer is formed from lithium fluoride (LiF).

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