Lateral high-voltage semiconductor device and method for forming a lateral high-voltage semiconductor device

Abstract

Lateral high-voltage semiconductor device (1), comprising: a semiconductor substrate (2) having a front side; a semiconductor element (10) comprising: a first semiconductor region (11) of a first conductivity type formed within the semiconductor substrate, a second semiconductor region (12) formed within the semiconductor substrate and spaced from the first semiconductor region (11) in a first lateral direction (x) parallel to the front side, and an extension region (13) adjacent to the second semiconductor region (12), wherein the semiconductor device (1) is configured to generate a load current between the first semiconductor region and the second semiconductor region; wherein the extension region (13) extends along the front side of the semiconductor substrate and comprises at least one mesa (14) projecting from the front side (101) of the semiconductor substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a lateral high-voltage semiconductor device. In particular, the lateral high-voltage semiconductor device may be a lateral power device with a breakdown voltage of at least 80 V or even at least 300 V. BACKGROUND

[0002] HV (high-voltage) semiconductor devices in CMOS (complementary metal-oxide semiconductor) technology form or include an interface between standard CMOS devices with input voltages below 5 V on the one hand and industrial or consumer circuits operating at voltages above 30 V on the other. Applications for such HV semiconductor devices exist in robotics, the automotive industry, and as drivers for MEMS (microelectromechanical systems). Typically, the majority of the signal processing takes place at low operating voltage in a CMOS part, and only the output signal interface to and / or the input signal interface operates at higher signal levels and / or requires higher current driving and sinking capability.An example of such a high-voltage semiconductor device is a gate driver circuit that enables a microcontroller or DSP (digital signal processor) to efficiently turn power semiconductor switches on and off. Signals containing information about the operation of the power semiconductor switches can be fed back to the CMOS part from the interfaces to the power semiconductor switches.

[0003] For example, from DE 11 2016 007 213 B4 a semiconductor device is known which has a high-side circuit region, a low-side circuit region and a RESURF isolation structure surrounding an outer edge region of the high-side circuit region in order to isolate the high-side circuit region and the low-side circuit region from one another, wherein the RESURF isolation structure has a high-voltage isolation region, a high-voltage N-channel MOS and a high-voltage P-channel MOS.

[0004] DE 10 2013 215 378 A1 discloses a lateral high-voltage transistor comprising a semiconductor layer of a second conductivity type provided on a main surface of a semiconductor substrate of the first conductivity type, a source region selectively provided in a surface of the semiconductor layer, a drain region of the first conductivity type selectively provided in the surface of the semiconductor layer such that it is spaced from the source region, a gate electrode, and a drift region. A strip-shaped diffusion layer contains linear diffusion layers, each containing strip-shaped diffusion regions that adjoin one another in such a way that double diffusion occurs in a portion where the strip-shaped diffusion regions adjoin one another.

[0005] There is a constant need to further improve the data exchange between different parts of a high-voltage semiconductor device, such as a gate driver circuit, with little additional effort. SUMMARY

[0006] The general invention relates to a lateral high-voltage semiconductor device, wherein the high-voltage semiconductor device comprises a semiconductor substrate having a front side and a semiconductor device. The semiconductor device comprises a first semiconductor region of a first conductivity type formed within the semiconductor substrate, a second semiconductor region formed within the semiconductor substrate and spaced from the first semiconductor region in a first lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region. The semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region.

[0007] An embodiment of the present disclosure relates to a lateral high voltage semiconductor device, the high voltage semiconductor device comprising a semiconductor substrate having a front side and a semiconductor device region.The semiconductor device comprises a first semiconductor region of a first conductivity type formed within the semiconductor substrate, a second semiconductor region formed within the semiconductor substrate and spaced from the first semiconductor region in a first lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region, and wherein the extension region extends along the front side of the semiconductor substrate and comprises at least one mesa protruding at the front side of the semiconductor substrate.

[0008] Another embodiment of the present disclosure relates to a lateral high-voltage semiconductor device comprising a semiconductor substrate having a front side and a semiconductor element. The semiconductor element comprises a first semiconductor region of a first conductivity type formed within the semiconductor substrate, a second semiconductor region spaced from the first semiconductor region in a first lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region.The high-voltage semiconductor device further comprises a first field plate structure in electrical connection with the first semiconductor region and a second field plate structure in electrical connection with the second semiconductor region, wherein at least one of the first and second field plate structures comprises a stack of at least three interconnected field plates one above the other, wherein at least one of the field plates of the stack comprises polysilicon and at least one of the field plates of the stack comprises a metal.

[0009] Another embodiment of the present disclosure relates to a lateral high-voltage semiconductor device comprising a semiconductor substrate having a front side and a semiconductor element, wherein the semiconductor element comprises: a first semiconductor region of a first conductivity type formed within the semiconductor substrate, a second semiconductor region spaced from the first semiconductor region in a first lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region. The high-voltage semiconductor device further comprises a first field plate structure in electrical connection with the first semiconductor region, a second field plate structure in electrical connection with the second semiconductor region,a third field plate structure in electrical connection with a first portion of the extension region and a fourth field plate structure in electrical connection with a second portion of the extension region, wherein the third field plate structure is connected to the first portion of the extension region on a side of the third field plate structure closer to the first semiconductor region along a first lateral direction than a center of gravity of the third field plate structure, and wherein the fourth field plate structure is connected to the second portion of the extension region on a side of the fourth field plate structure closer to the second semiconductor region along a first lateral direction than a center of gravity of the fourth field plate structure.

[0010] The at least one mesa protruding from the front side along the extension region and / or the respective field plate structures arranged along the extension region enable improved electrical performance of the lateral high-voltage semiconductor device.

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various illustrated examples may be combined, provided they are not mutually exclusive. Fig. 1 illustrates a schematic plan view of a power semiconductor device. Fig. 2 illustrates a schematic section of a power semiconductor device. Fig. 3 illustrates a schematic section of a power semiconductor device. Fig. Figure 4 illustrates a schematic section of a power semiconductor device and shows various examples of field plate structures in more detail. Fig. 5 to Fig. 7 illustrate more schematic portions of exemplary power semiconductor devices. Fig. 8 to Fig. 11 illustrate more schematic portions of exemplary power semiconductor devices in a transistor configuration. DETAILED DESCRIPTION

[0013] The examples described herein provide embodiments of a lateral high-voltage semiconductor device. The lateral high-voltage semiconductor device may have a breakdown voltage of at least 80 V or even at least 300 V.

[0014] Embodiments of the present disclosure relate to a lateral high-voltage semiconductor device, wherein the high-voltage semiconductor device comprises a semiconductor substrate having a front side and a semiconductor device region. The semiconductor device comprises a first semiconductor region of a first conductivity type formed within the semiconductor substrate, a second semiconductor region formed within the semiconductor substrate and spaced from the first semiconductor region in a first lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region, and wherein the extension region extends along the front side of the semiconductor substrate.In a section through the device, the lateral load current can flow parallel to the first lateral direction.

[0015] The first semiconductor region may be arranged near or on the front side of the semiconductor substrate. The second semiconductor region may be arranged near or on the front side of the semiconductor substrate.

[0016] The extension region may have the same conductivity type as the second semiconductor region, but with a lower doping concentration compared to the second region. The average doping concentration within the extension region may be at least one order of magnitude, or at least two orders of magnitude, or even at least three orders of magnitude lower compared to the second semiconductor region. The extension region may be configured to accommodate a reverse voltage of the semiconductor element or semiconductor device in a reverse state of the semiconductor element. Therefore, in the reverse state, at least 50% of the breakdown voltage of the semiconductor device may be dropped across the extension region. The extension region may be configured to relax the electric field between the first and second semiconductor regions.The extension region may extend primarily in the lateral direction parallel to the front side. Therefore, a main extension direction of the extension region may be parallel to the front side of the substrate. The extension region may be arranged near or at the front side of the semiconductor substrate.

[0017] The semiconductor element can implement an electronic component or an electronic device. For example, the semiconductor element can be a transistor (e.g., a bipolar junction transistor (BJT), a field-effect transistor (FET), or a junction-gate field-effect transistor (JFET), a diode (e.g., a pn diode or a Zener diode), an insulated-gate bipolar transistor (IGBT), a thyristor, or the like.

[0018] If the semiconductor element is a transistor, the semiconductor element may further comprise a body region of a second conductivity type laterally adjacent to the first semiconductor region and the extension region, and a gate structure configured to control the lateral load current between the first and second semiconductor regions. The gate region may be insulated from the body region. The gate region may be configured to form an inversion channel in the body region for controlling the lateral load current. The first semiconductor region may be a source or emitter region of the transistor, and the second semiconductor region may be a drain or collector region of the transistor. The first region may be adjacent to the body region. The body region may be adjacent to the extension region. The second semiconductor region may have the first conductivity type.The extension area can also have the first conductivity type.

[0019] If the semiconductor element is a diode, the first semiconductor region may be an anode and the second semiconductor region may be a cathode of the semiconductor element. The first and second semiconductor regions may have opposite conductivity types. For example, the first semiconductor region may have the first conductivity type and the second semiconductor region may have the second conductivity type. The extension region may also have the second conductivity type. The first region may be adjacent to the extension region. The pn junction may be formed between the first semiconductor region and the extension region.

[0020] According to some embodiments, the lateral high voltage semiconductor device comprises at least one mesa protruding from the front side of the semiconductor substrate.

[0021] Alternatively or in addition to the above at least one mesa, the lateral high-voltage semiconductor device may comprise a first field-plate structure in electrical connection with the first semiconductor region and a second field-plate structure in electrical connection with the second semiconductor region. The first and / or second field-plate structure may comprise one, two, three, or more field plates, wherein the field plates of the same field-plate structure partially or completely overlap each other laterally.

[0022] According to some embodiments, the at least one of the first and second field plate structures comprises a stack of at least three interconnected field plates one above the other, wherein at least one of the field plates of the stack comprises polysilicon and at least one of the field plates of the stack comprises a metal.Alternatively or additionally, the lateral high-voltage semiconductor device may further comprise a third field plate structure in electrical connection with a first portion of the extension region and a fourth field plate structure in electrical connection with a second portion of the extension region, wherein the third field plate structure is connected to the first portion of the extension region on a side of the third field plate structure closer to the first semiconductor region along a first lateral direction than a centroid of the third field plate structure, and wherein the fourth field plate structure is connected to the second portion of the extension region on a side of the fourth field plate structure closer to the second semiconductor region along a first lateral direction than a centroid of the fourth field plate structure.In other words, both the third and the fourth field plate structure are connected asymmetrically with respect to their lateral center, wherein a projection of the respective field plate structure over the connection facing a lateral center of the extension region is greater than a projection of the respective field plate structure over the connection facing away from the lateral center of the extension region.

[0023] The first and second portions of the extension region, where the third and fourth field plate structures are connected to the extension region, may comprise a respective mesa protruding from the front side of the semiconductor substrate. Thus, the third field plate structure may be connected to a first of the at least one mesa protruding from the front side of the semiconductor substrate. Similarly, the fourth field plate structure may be connected to a second mesa protruding from the front side of the semiconductor substrate.

[0024] The field plate structures can be arranged at least partially or completely over the at least one mesa. Each of the field plate structures can at least partially laterally overlap the respective mesa connected to it.

[0025] The third and fourth field plate structures may comprise a stack of at least three interconnected field plates one above the other. At least one of the field plates of the stack may comprise polysilicon, and at least one of the field plates of the stack may comprise a metal.

[0026] In one or more of the field plate structures, e.g., the first and second field plate structures and / or the third and fourth field plate structures, the uppermost of the at least three interconnected field plates may comprise a metal or even be made of a metal, while the lowermost of the at least three interconnected field plates may comprise polysilicon. Each of the field plates of a respective field plate structure may partially or completely laterally overlap all lower field plates of the same field plate structure. Thus, the uppermost of the at least three interconnected field plates may completely laterally overlap all field plates of the same field plate structure.

[0027] The at least one mesa may be a raised region compared to surrounding portions of the extension region. In other words, the substrate at the mesa may extend higher than portions adjacent to the mesa. In the mesa regions, the substrate may even have a greater thickness compared to neighboring portions.

[0028] The at least one mesa may be part of a field ring within the semiconductor substrate. In the case of two or more such mesas, each mesa may be part of a respective field ring. The field rings may extend below and / or adjacent to the mesa. The field rings may be part of the extension region. In each field ring, the doping concentration may be higher than in surrounding sections of the extension region. The conductivity type of the doping within the field ring may be the same or opposite to the surrounding sections of the extension region. The field rings may be laterally centered around the respective mesa.

[0029] The lateral high-voltage semiconductor device may further comprise a first insulating layer laterally adjacent to the at least one mesa on both sides of the at least one mesa. In other words, the portions adjacent to the at least one mesa may be covered with the first insulating layer. The first insulating layer may have the same vertical extent as the at least one mesa, and / or an upper surface of the insulating layer and an upper surface of the mesa may form an at least substantially flat surface.

[0030] Portions of the insulating layer can be arranged between the at least one mesa and the first semiconductor region and between the at least one mesa and the second semiconductor region. Alternatively or additionally, portions of the insulating layer can be arranged between at least two separate portions of the at least one mesa.

[0031] The lateral high-voltage semiconductor device may further comprise at least a second insulating layer over the first insulating layer and the at least one mesa. The second insulating layer thereover may comprise a same material or even a same composition as the first insulating layer. The first and second insulating layers may be formed in a single or separate manufacturing steps. The first and / or second layers may comprise an oxide, e.g., silicon oxide, or a nitride, e.g., silicon nitride. The first layer may, for example, comprise a thermally grown oxide, and the second layer may, in contrast, comprise a deposited oxide.

[0032] The respective electrical connection connecting one of the field plates to a semiconductor section or a semiconductor region may be configured to provide a low-resistance contact between the field plate structure and the semiconductor sections or the semiconductor region, or may comprise a pn junction or a Schottky junction between the field plate structure and the mesa. The region of the electrical connection may be structured laterally along a main extension direction of the respective mesa to which the electrical connection is assigned. The main extension direction of the mesa may be parallel to the front side of the substrate and perpendicular to the current flow between the first and second semiconductor regions (or an imaginary line between the first and second semiconductor regions).In the section through the device, the main extension direction of the mesa can be parallel to the front side and perpendicular to the first lateral direction. Thus, the main extension direction of the mesa in the section can be parallel to the second lateral direction.

[0033] The electrical connection may be configured to provide a low-resistance contact between the third and fourth field-plate structures and the respective section of the extension region. Alternatively or additionally, the electrical connection may comprise a rectifying junction, e.g., a pn junction or a Schottky junction, between the field-plate structure and the respective section of the extension region.

[0034] If the third and fourth field-plate structures are connected to a respective mesa, the electrical connection may be configured to provide a low-resistance contact between the third and fourth field-plate structures and the respective mesa. Alternatively or additionally, the electrical connection may comprise a rectifying junction, e.g., a pn junction or a Schottky junction, between the field-plate structure and the respective mesa.

[0035] The field plate structures can be embedded in an insulating material, e.g., the second insulating layer. For example, each field plate structure can be completely enclosed by the insulating material, with only the electrical connection being connected by the insulating material.

[0036] Each rectifying junction may comprise a first portion and a second portion, wherein a connecting surface between the portions forms the junction, wherein the mesa is laterally structured into the first and second portions. In the case of a pn junction, the first portion may have the first conductivity type and the second portion may have the second conductivity type, wherein the pn junction is formed between the first and second portions.

[0037] For example, the mesa is structured along the first lateral direction, resulting in the bonding surface extending in a second lateral direction perpendicular to the first lateral direction. For example, the mesa is structured along the second lateral direction, resulting in the bonding surface extending in the first lateral direction.

[0038] For example, in the case of an ohmic connection, the electrical connection may only connect the mesa asymmetrically, e.g., near a lateral edge. For example, in the case of a pn junction, one of the sections of the junction may have a larger lateral extension than the other. In this case, the smaller section of the junction may only extend near a lateral edge of the mesa.

[0039] The lateral high-voltage semiconductor device may further comprise a high-voltage (HV) conductive layer over the at least one field-plate structure. The high-voltage conductive layer may be insulated from the at least one field-plate structure by an insulating layer, e.g., the second insulating layer.

[0040] For example, at least 50%, or even at least 70%, or even at least 85% of the semiconductor element can be laterally overlapped by the field plate structures. This can provide effective shielding of the semiconductor element from the HV conductive layer.

[0041] The semiconductor substrate may include a backside opposite the frontside. The lateral high-voltage semiconductor device may include a backside insulating layer disposed on the backside of the semiconductor substrate. The insulating layer may include an oxide layer. The oxide layer may have a thickness of 0.5 µm to 20 µm, and preferably 2 µm to 20 µm. The oxide layer may be deposited on the backside. This enables high scalability of the voltage class of the semiconductor device, since the thickness of the deposited oxide can be easily selected depending on the desired breakdown voltage. A combined thickness of the semiconductor substrate and the backside insulating layer may range from 20.5 µm to 100 µm ((20 µm to 100 µm for the semiconductor substrate) + (0.5 µm to 20 µm for the insulating layer)).

[0042] The lateral high-voltage semiconductor device may further comprise an additional silicon layer beneath the backside of the semiconductor substrate. For example, the additional silicon layer may be directly or indirectly attached to the backside insulating layer. For example, one or more adhesion-promoting layers may be disposed between the backside insulating layer and the additional silicon layer. The one or more adhesion-promoting layers may include a tape, e.g., a DAF tape. For example, alternatively or in addition to the one or more adhesion-promoting layers, one or more further layers may be disposed between the backside insulating layer and the additional silicon layer. The one or more further layers may include one or more dielectrics and / or one or more metal layers.

[0043] The lateral high-voltage semiconductor device may further comprise at least one isolation trench that electrically isolates the semiconductor element from another semiconductor element adjacent to the semiconductor element on the same semiconductor substrate. The isolation trench may comprise a trench electrode. The trench electrode may comprise doped or undoped polysilicon. The trench electrode may be floating or connected to any potential. The at least one isolation trench may extend from the front side to the back side of the substrate, where it adjoins the back side insulation layer.

[0044] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which a gate driver device may be practiced. Other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment may be used on or in conjunction with other embodiments to yield yet another embodiment. It is intended that the present disclosure include such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference numerals throughout the various drawings unless otherwise indicated.

[0045] The terms "having," "containing," "including," "comprising," and the like are open-ended and indicate the presence of the specified structures, elements, or features, but do not preclude the presence of additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0046] The term “electrically connected” describes a permanent low-resistance ohmic connection between electrically connected elements, for example a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material.

[0047] The term “power semiconductor device” refers to semiconductor devices with a high voltage blocking capability of at least 30 V, for example 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV or more and with a nominal forward current or forward current of at least 200 mA, for example 1 A, 10 A or more.

[0048] The semiconductor element can be configured as a diode, any type of FET (MOSFET, JFET, etc.), a bipolar transistor, an IGBT, or the like. MOSFETs (metal-oxide-semiconductor field-effect transistors) are voltage-controlled devices and include all types of IGFETs (insulated-gate field-effect transistors) with gate electrodes based on doped semiconductor material and / or metal, and with gate dielectrics made of oxide and / or dielectric materials other than oxides.

[0049] An ohmic contact describes a non-rectifying electrical junction between two conductors, e.g., between a semiconductor material and a metal. The ohmic contact exhibits a linear or nearly linear current-voltage curve (IV curve) in the first and third quadrants of the IV diagram according to Ohm's law.

[0050] Ranges specified for physical dimensions include the limits. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a limit such as "at most" and "at least."

[0051] The term "on" should not be interpreted to mean only "directly on." Rather, when an element is positioned "on" another element (e.g., a layer is positioned "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).

[0052] Two adjacent doping regions in a semiconductor layer form a semiconductor junction. Two adjacent doping regions of the same conductivity type and with different dopant concentrations form a unipolar junction, e.g., an n / n+ or p / p+ junction along an interface between the two doping regions. At the unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may exhibit a step or inflection point where the dopant concentration profile changes from concave to convex or vice versa. Two adjacent doping regions of complementary conductivity types form a pn junction.

[0053] The first conductivity type may be n-type, and the second conductivity type may be p-type. In this case, semiconductor regions of the first conductivity type may comprise an excess of donor-type dopants, and semiconductor regions of the second conductivity type may comprise an excess of acceptor-type dopants. Alternatively, the first conductivity type may be p-type, and the second conductivity type may be n-type. In this case, semiconductor regions of the first conductivity type may comprise an excess of acceptor-type dopants, and semiconductor regions of the second conductivity type may comprise an excess of donor-type dopants.

[0054] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p." For example, "n-" indicates a doping concentration lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.

[0055] Embodiments of the present disclosure relate to a high-voltage semiconductor device including a low-side part and a high-side part. The high-voltage semiconductor device may be a gate driver device. The low-side part outputs a first gate drive signal between a first gate output and a first reference potential VSS. The high-side part outputs a second gate drive signal between a second gate output and a second reference potential VS.

[0056] The low-side portion includes electrical circuitry of a low-voltage domain. The low-voltage domain outputs the first gate drive signal and may further include electrical circuitry of a CMOS interface for communicating with standard CMOS devices with input voltages below 5 V. The electrical circuitry for the CMOS interface and the electrical circuitry for driving the first gate drive signal may be isolated from each other or may be parts of a single voltage domain.

[0057] The first gate drive signal output by the low-side part may be capable of driving a gate of a low-side switch of an electronic half-bridge.

[0058] The second gate drive signal output by the high-side part may be capable of driving a high-side switch of the same half-bridge. The half-bridge may be part of an H-bridge that switches the polarity of a voltage applied to a load.

[0059] The above-mentioned breakdown voltage of at least 80 V or even at least 300 V can be present between the low side and the high side. The breakdown voltage within the respective voltage domain of the low side and / or the high side can be smaller, e.g., less than 80 V or less than 50 V. However, the breakdown voltage of the semiconductor element can also be at least 80 V or even at least 300 V. The semiconductor element can establish and / or control an electrical connection between the different voltage domains of the high-voltage semiconductor device, e.g., the high side and the low side in the case of a gate driver device.

[0060] The semiconductor substrate may include a conductive, e.g., doped, semiconductor material. The substrate may be a homogeneous layer or a layer stack comprising two or more sublayers of different composition and / or internal structure of the semiconductor material. For example, the semiconductor substrate is a silicon (Si) or gallium arsenide (GaAs) or gallium nitride (GaN) or silicon carbide (SiC) wafer. The thickness of the semiconductor substrate may be in a range from 4 µm to 200 µm, or in particular in a range from 20 µm to 150 µm.

[0061] Fig. 1 to Fig. 4 each show a lateral high-voltage semiconductor device 1. Fig. 1 is a highly schematic top view of the device, while all other figures show lateral sections through the device. The semiconductor device 1 comprises a semiconductor substrate 2, which comprises, for example, silicon, Si, or silicon carbide, SiC. The device 1 comprises at least one semiconductor element 10. The semiconductor element 10 comprises at least a first semiconductor region 11 of a first conductivity type formed within the semiconductor substrate 2, and a second semiconductor region 12 formed within the semiconductor substrate 2. The first semiconductor region 11 and the second semiconductor region 12 are spaced apart from each other along a first lateral direction x parallel to the front side. The substrate 2 can have the first or the second conductivity type. Typically, the substrate 2 can have p-type doping.

[0062] Both regions 11, 12 may be connected via an extension region 13 that adjoins the second semiconductor region 12. The extension region 13 has the second conductivity type. The extension region 13 may be configured to shield or absorb an electric field between the first and second semiconductor regions 11, 12. Therefore, the extension region 13 may be configured to absorb a nominal voltage or breakdown voltage of the device 1 between both regions 11, 12. The extension region 13 may be lighter doped than the second semiconductor region 12. The doping concentration of the extension region 13 may, for example, be at least two, at least three, or at least five orders of magnitude lower than the doping concentration of the second semiconductor region 12.The doping concentration of the extension region 13 may, for example, be at least two, at least three or at least five orders of magnitude smaller than the doping concentration of the first semiconductor region 11.

[0063] With reference to Fig. 2 to Fig. 4, the lateral high-voltage semiconductor device 1 comprises a plurality of mesas 14 protruding from the front side of the semiconductor substrate 2. The mesas 14 are a raised area compared to surrounding portions of the extension region 13. In other words, the substrate 2 may extend higher at the mesa 13 than in portions (where a substrate 2 is covered with the insulating layer 16) adjacent to the mesa 14. In the mesa regions 14, the substrate 2 may even have a greater thickness compared to adjacent portions (where a substrate 2 is covered with the insulating layer 16).

[0064] A main extension direction of the mesa 14 may be parallel to the front side of the substrate and perpendicular to the current flow between the first and second semiconductor regions 11, 12 (or an imaginary line between the first and second semiconductor regions 11, 12). In the section through the device, the main extension direction of the mesa 14 extends parallel to the y-axis. The main extension direction of the mesas 14 may be parallel to the front side and perpendicular to the first lateral direction x. Thus, the main extension direction of the mesas 14 in the section may be parallel to the second lateral direction y.

[0065] Portions of the insulating layer 16 are disposed between the respective mesas 14. One portion of the insulating layer 16 is disposed between a mesa 14 and the first semiconductor region 11 because the first semiconductor region 11 includes a raised portion protruding from the front side. Another portion of the insulating layer 16 is disposed between a mesa 14 and the second semiconductor region 12 because the second semiconductor region 12 includes a raised portion protruding from the front side.

[0066] The lateral high-voltage semiconductor device further comprises a plurality of first field plate structures 15. The first field plate structures 15 are electrically connected to one of the first semiconductor region 11, the second semiconductor region 12, or the mesa 14. A first field plate structure 151 is connected to the first semiconductor region 11. A second field plate structure 152 is connected to the second semiconductor region 12. A third field plate structure 153 is connected to a first mesa 14. A fourth field plate structure 154 is connected to a second mesa 14. The field plate structures 15 can each comprise one, two, three, or more field plates, wherein the field plates 154, 155, 156 of the same field plate structure 15 partially or completely overlap each other laterally. For example, the larger of the field plates can completely overlap the smaller of the field plates of the same field plate structure.Each of the field plate structures 15 associated with a mesa 14 at least partially laterally overlaps the respective mesa 14 connected thereto.

[0067] Various designs of the field plate structures are shown in Fig. 4. The field plates 154, 155, 156 of the same field plate structure 15 can be connected to one another via connections 159. The lowest field plate 154 of the respective field plate structures 15 can be connected to one of the mesas 14 or one of the first and second semiconductor regions 11, 12 via a bottom connection 159. The third and fourth field plate structures 153, 154 are connected to the extension region 13 via the respective associated mesa 14.

[0068] The at least one mesa 14 can be part of a field ring within the semiconductor substrate (cf. Fig. 1 to Fig. 3). In the case of two or more such mesas 14, each mesa 14 can be part of a respective field ring. The field rings can extend below and / or adjacent to the mesa 14. The field rings can be part of the extension region 13. In each field ring, the doping concentration can be higher than in surrounding sections of the extension region. The conductivity type of the doping within the field ring can be the same or opposite to the surrounding sections of the extension region. The field ring associated with the mesa 14 can be laterally centered around the respective mesa 14. The field rings can each have a field ring doping region 142 (cf. Fig. 4) of the same or opposite conductivity type as the extension region 13.

[0069] According to some in Fig. 4, the field plate structures 15 comprise a stack of at least three interconnected field plates 154, 155, 156 one above the other, wherein at least one of the field plates 154 of the stack comprises polysilicon and at least one of the field plates 155, 156 of the stack 15 comprises a metal.

[0070] In one or more of the field plate structures 15, e.g., the first and second field plate structures 151, 152 and / or the third and fourth field plate structures 153, 154, the uppermost field plate 156 of the at least three interconnected field plates 154, 155, 156 may comprise a metal or even be made of a metal, while the lowermost 154 of the at least three interconnected field plates 154, 155, 156 of the structure 15 comprises polysilicon. Each of the field plates of a respective field plate structure may partially or completely laterally overlap all lower field plates of the same field plate structure. Thus, the uppermost of the at least three interconnected field plates may completely laterally overlap all field plates 154, 155, 156 of the same field plate structure 15.

[0071] With reference to Fig. 4, the third field plate structure 153 is connected to a first portion of the extension region 13 on a side of the third field plate structure 153 closer to the first semiconductor region 11 along a first lateral direction x as a center of gravity of the third field plate structure 153. The fourth field plate structure 154 is connected to a second portion of the extension region 13 on a side of the fourth field plate structure 154 closer to the second semiconductor region 12 along the first lateral direction x as a center of gravity of the fourth field plate structure 154.In other words, both the third and the fourth field plate structure 153, 154 are connected asymmetrically with respect to their lateral center, wherein a projection of the respective field plate structure 153, 154 over the connection 159 facing a lateral center of the extension region 13 is greater than a projection of the respective field plate structure 153, 154 over the connection facing away from the lateral center of the extension region 13.

[0072] The respective electrical connection 158, 159 connecting one of the field plates 154 of a field plate structure 15 to a semiconductor section or a semiconductor region may be configured to provide a low-resistance contact between the field plate structure 15 and the semiconductor sections or a semiconductor region, or comprises a pn junction or a Schottky junction between the field plate structure 15 and the mesa 14. In the three lower examples of Fig. 4, the field plate structures 15 are connected to the mesas 14 / the extension region via doped regions 141. The doped regions 14 may have the same conductivity type as the extension region 13 with a higher dose to improve the contact resistance. The doped regions 14 may have the opposite conductivity type as the extension region 13 with a higher dose to form a rectifying junction. The electrical connection region may be structured laterally along the main extension direction of the respective mesa to which the electrical connection is assigned.

[0073] The insulating layer 16 may comprise a first insulating layer 161 laterally adjacent to the at least one mesa on both sides of the at least one mesa. In other words, the portions adjacent to the at least one mesa 14 may be covered with the first insulating layer. The first insulating layer 161 may have the same vertical extent as the at least one mesa 14 and / or an upper surface of the insulating layer 161 and an upper surface of the mesa 14 may form an at least substantially flat surface.

[0074] The insulating layer 16, which comprises a first insulating layer 161, may further comprise at least one second insulating layer 162 over the first insulating layer 161 and the at least one mesa 14. The second insulating layer 162 thereover may comprise a same material or even a same composition as the first insulating layer 161. The first and second layers 161, 162 may have a different composition, e.g., a different material or different physical properties. The first and second insulating layers 161, 162 may be formed in a single or separate manufacturing steps. The first and / or second layers 161, 162 may comprise an oxide, e.g., silicon oxide, or a nitride, e.g., silicon nitride. The first layer 161 may, for example, comprise a thermally grown oxide, and the second layer may, in contrast, comprise a deposited oxide.

[0075] The semiconductor element 10 may implement an electronic component or an electronic device. For example, the semiconductor element may be a transistor (e.g., a bipolar junction transistor (BJT), a field-effect transistor (FET), or a junction-gate field-effect transistor (JFET), a diode (e.g., a pn diode or a Zener diode), an insulated-gate bipolar transistor (IGBT), a thyristor, or the like.

[0076] With reference to Fig. 8 to Fig. 11, if the semiconductor element 10 is a transistor-like device, the semiconductor element 10 may further comprise a body region 110 of a second conductivity type laterally adjacent to the first semiconductor region 11 and the extension region 13, and a gate structure 113 configured to control the lateral load current between the first and second semiconductor regions 11, 12. The gate region 113 may be isolated from the body region 110. The gate region may be configured to form an inversion channel in the body region for controlling the lateral load current. The first semiconductor region 11 may be a source or emitter region 111 of the transistor, and the second semiconductor region may be a drain or collector region 112 of the transistor. The second semiconductor region 12 or the drain or collector region 112 may have the first conductivity type.The extension region 13 can also have the first conductivity type.

[0077] With reference to Fig. 10, some of the mesa regions 14 may be configured as a base region 144. Associated field plate structures are connected to the base regions 144. Referring to FIG. 9, the device 1 includes an additional extension region of the opposite conductivity type compared to the extension region 13.

[0078] The field plate structures can be embedded in an insulating material, e.g. the second insulating layer 162 (see Fig. 5 to Fig. 7). For example, each field plate structure 15 may be completely enclosed by the insulating material 162, with only the electrical connection 158, 159 being connected by the insulating material 162.

[0079] For example, the mesa 14 is structured along the first lateral direction, resulting in the bonding surface extending in a second lateral direction perpendicular to the first lateral direction. For example, the mesa is structured along the second lateral direction, resulting in the bonding surface extending in the first lateral direction.

[0080] For example, in the case of an ohmic connection, the electrical connection 158, 159 may only connect the mesa 14 asymmetrically, e.g., near a lateral edge of the mesa 14. For example, in the case of a pn junction, one of the sections of the junction may have a larger lateral extent than the other. In this case, the smaller section of the junction may only extend near a lateral edge of the mesa 14.

[0081] The lateral high-voltage semiconductor device 1 may further comprise a high-voltage (HV) conductive layer 19 (cf. Fig. 3) above the at least one field plate structure 15. The high-voltage conductive layer 19 can be insulated from the at least one field plate structure 15 by an insulating layer 16, e.g., the second insulating layer 162.

[0082] For example, at least 50%, or even at least 70%, or even at least 85% of the semiconductor element 10 can be jointly laterally overlapped by the field plate structures 15. This can provide effective shielding of the semiconductor element 10 from the HV conductive layer 19.

[0083] The semiconductor substrate 2 may include a backside opposite the frontside. The lateral high-voltage semiconductor device may include a backside insulating layer 30 arranged on the backside of the semiconductor substrate 2. The backside insulating layer 30 may include an oxide layer. The oxide layer may have a thickness of 0.5 µm to 20 µm, and preferably 2 µm to 20 µm. The oxide layer may be deposited on the backside. This enables great scalability of the voltage class of the semiconductor device 1, since the thickness of the deposited oxide can be easily selected depending on the desired breakdown voltage. A combined thickness of the semiconductor substrate 2 and the backside insulating layer 30 may be in the range of 20.5 µm to 100 µm ((20 µm to 100 µm for the semiconductor substrate) + (0.5 µm to 20 µm for the insulating layer)).

[0084] The lateral high-voltage semiconductor device may further comprise an additional silicon layer beneath the backside of the semiconductor substrate. For example, the additional silicon layer may be directly or indirectly attached to the backside insulating layer. For example, one or more adhesion-promoting layers may be disposed between the backside insulating layer and the additional silicon layer. The one or more adhesion-promoting layers may include a tape, e.g., a DAF tape. For example, alternatively or in addition to the one or more adhesion-promoting layers, one or more further layers may be disposed between the backside insulating layer and the additional silicon layer. The one or more further layers may include one or more dielectrics and / or one or more metal layers.

[0085] The lateral high-voltage semiconductor device may further comprise at least one isolation trench 31 electrically isolating the semiconductor element from another semiconductor element adjacent to the semiconductor element 10 on the same semiconductor substrate 2. The isolation trench 31 may comprise a trench electrode 33. The trench electrode 33 may comprise doped or undoped polysilicon. The trench electrode 33 may be floating or connected to any potential (e.g., the potential of the first or second semiconductor region 11, 12). The at least one isolation trench 31 may extend from the front side to the back side of the substrate, where it adjoins the back side isolation layer 30. The isolation trench 31 may comprise one or more trench isolation layers 34, which may comprise, for example, an oxide layer.

Claims

[1] Lateral high-voltage semiconductor device (1) comprising: a semiconductor substrate (2) having a front side; a semiconductor element (10) comprising: a first semiconductor region (11) of a first conductivity type formed within the semiconductor substrate, a second semiconductor region (12) formed within the semiconductor substrate and spaced from the first semiconductor region (11) in a first lateral direction (x) parallel to the front side, and an extension region (13) adjacent to the second semiconductor region (12), wherein the semiconductor device (1) is configured to generate a load current between the first semiconductor region and the second semiconductor region; wherein the extension region (13) extends along the front side of the semiconductor substrate and comprises at least one mesa (14) projecting from the front side (101) of the semiconductor substrate. [2] The lateral high voltage semiconductor device of claim 1, further comprising at least one field plate structure (15) at least partially over a respective one of the at least one mesa and an electrical connection connecting the field plate structure to the mesa. [3] Lateral high-voltage semiconductor device (1) comprising: a semiconductor substrate (2) having a front side; a semiconductor element (10) comprising: a first semiconductor region (11) of a first conductivity type formed within the semiconductor substrate (2), a second semiconductor region (12) spaced from the first semiconductor region (11) in a first lateral direction (x) parallel to the front side, and an extension region (13) adjacent to the second semiconductor region (12), wherein the semiconductor device (1) is configured to generate a lateral load current between the first semiconductor region and the second semiconductor region steer; a first field plate structure (15, 151) in electrical connection with the first semiconductor region (11); and a second field plate structure (15, 152) in electrical connection with the second semiconductor region (13); wherein at least one of the first and second field plate structures comprises a stack of at least three interconnected field plates (154, 155, 156) one above the other; wherein at least one of the field plates (154, 155, 156) of the stack comprises polysilicon and at least one of the field plates (154, 155, 156) of the stack comprises a metal. [4] Lateral high-voltage semiconductor device (1) comprising: a semiconductor substrate (2) having a front side; a semiconductor element (10) comprising: a first semiconductor region (11) of a first conductivity type formed within the semiconductor substrate, a second semiconductor region (12) spaced from the first semiconductor region in a first lateral direction (x) parallel to the front side, and an extension region (13) adjacent to the second semiconductor region, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region; a first field plate structure (15, 151) in electrical connection with the first semiconductor region; a second field plate structure (15, 152) in electrical connection with the second semiconductor region; a third field plate structure (15, 153) in electrical connection with a first portion of the extension region; a fourth field plate structure (15, 154) in electrical communication with a second portion of the extension region; wherein the third field plate structure is connected to the first portion of the extension region at a side of the third field plate structure closer to the first semiconductor region along a first lateral direction than a center of gravity of the third field plate structure; wherein the fourth field plate structure is connected to the second portion of the extension region at a side of the fourth field plate structure closer to the second semiconductor region along a first lateral direction than a center of gravity of the fourth field plate structure. [5] The lateral high voltage semiconductor device of claim 4, wherein at least one of the field plates of the stack comprises polysilicon and at least another of the field plates of the stack comprises a metal. [6] The lateral high-voltage semiconductor device according to any one of claims 3 to 5, wherein the extension region extends along the front side of the semiconductor substrate and includes at least one mesa projecting from the front side of the semiconductor substrate. [7] A lateral high voltage semiconductor device according to any one of claims 1, 2 or 5 or 6, further comprising a first insulating layer laterally adjacent to the at least one mesa on both sides of the at least one mesa. [8] The lateral high-voltage semiconductor device of claim 7, wherein the first insulating layer has a same vertical extent as the at least one mesa and / or an upper surface of the first insulating layer and an upper surface of the mesa form an at least substantially flat surface. [9] A lateral high-voltage semiconductor device according to claim 7 or 8, wherein portions of the first insulating layer - between the at least one mesa and the first semiconductor region and between the at least one mesa and the first semiconductor region and / or - are arranged between at least two separate mesas. [10] The lateral high voltage semiconductor device of any one of claims 7 to 9, further comprising at least one second insulating layer over the first insulating layer and the at least one mesa. [11] The lateral high voltage semiconductor device of any one of claims 1, 2 or 5 to 10, further comprising at least one field ring, wherein the at least one field ring is at least partially disposed within the at least one mesa. [12] The lateral high-voltage semiconductor device of any one of claims 2 to 11, wherein each electrical connection is configured to provide a low-resistance contact between the field plate structure and the respective portion of the extension region. [13] A lateral high voltage semiconductor device according to any one of claims 2 to 11, wherein each electrical connection comprises a rectifying junction between the field plate structure and the mesa. [14] The lateral high voltage semiconductor device of claim 13, wherein the rectifying junction comprises a first portion and a second portion, a connecting surface between the portions forming the junction, the mesa being laterally structured into the first and second portions. [15] A lateral high-voltage semiconductor device according to claim 14, wherein - the mesa is structured along the first lateral direction, resulting in the connecting surface extending in a second lateral direction perpendicular to the first lateral direction; or - the mesa is structured along the second lateral direction, resulting in the bonding surface extending in the first lateral direction. [16] A lateral high-voltage semiconductor device according to any one of the preceding claims, further comprising a high-voltage conductive layer over the at least one field plate structure. [17] Lateral high-voltage semiconductor device according to claim 13, wherein at least 50% or even at least 70% of the semiconductor element are jointly laterally overlapped by the field plate structures. [18] A lateral high-voltage semiconductor device according to any one of the preceding claims, wherein the semiconductor element further comprises: - a body region of a second conductivity type laterally adjacent to the first semiconductor region and the extension region, and - a gate structure configured to control the lateral load current between the first and second semiconductor regions. [19] A lateral high-voltage semiconductor device according to any one of the preceding claims, wherein the first semiconductor region is arranged near or at the front side and / or the second semiconductor region is arranged near or at the front side. [20] A lateral high-voltage semiconductor device according to any one of the preceding claims, wherein the semiconductor substrate comprises a backside opposite the frontside, the lateral high-voltage semiconductor device comprising a backside insulating layer disposed on the backside. [21] A lateral high-voltage semiconductor device according to any one of the preceding claims, wherein the semiconductor device comprises at least one isolation trench electrically isolating the semiconductor element from another semiconductor element adjacent to the semiconductor element on the same semiconductor substrate. [22] A lateral high-voltage semiconductor device according to the preceding claims 20 and 21, wherein the at least one isolation trench extends from the front side to the back side of the substrate where it adjoins the back side insulation layer. [23] A method of forming a lateral high-voltage semiconductor device, the method comprising: Providing a semiconductor substrate having a front side; Formation of mesa areas; Forming a semiconductor cell comprising: a first semiconductor region of a first conductivity type formed within the semiconductor substrate, a second semiconductor region spaced from the first semiconductor region in a lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region; wherein the semiconductor cell is configured to control a lateral load current between the first semiconductor region and the second semiconductor region; wherein the extension region extends along the front side of the semiconductor substrate and the at least one mesa protrudes at the front side of the semiconductor substrate.

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