TRANSISTOR DEVICE AND METHOD

Abstract

In one embodiment, a transistor device (10, 10') comprises a semiconductor substrate comprising at least one transistor cell (12), the transistor cell (12) comprising an elongated trench (13) and an elongated mesa (14). The elongated trench (13) is arranged in the first main surface (15) of the semiconductor substrate (11) and comprises an elongated gate electrode (16) that is electrically separated from the semiconductor substrate (11) by a gate dielectric (17). A first insulating layer (23) is arranged on the first main surface (15) and covers the gate trench (13), and an elongated contact connection strip (24) is arranged on the first insulating layer (23) and extends over and parallel to the elongated trench (13). The elongated contact connecting strip (24) is electrically connected to the elongated gate electrode (16) in the elongated trench (13) by at least one first contact (25) which extends through the first insulating layer (23).

Description

BACKGROUND

[0001] Transistor devices used in power electronics applications can be fabricated using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated-gate bipolar transistors (IGBTs).

[0002] Generally, an n-channel trench-gate power MOSFET comprises a semiconductor substrate, which may include an n-type base substrate on which an n-type epitaxial layer is formed. The base substrate provides the drain of the MOSFET. A p-type body region extends into the epitaxial layer, and an n-type source region is formed on or in the body region. Trench-gate MOSFETs comprise a plurality of trenches extending through the body region and into the epitaxial layer. Each trench is lined by a gate dielectric layer formed on the sidewalls and bottom of each trench. A gate electrode is formed in each of the trenches, and a dielectric layer covers the trenches and also partially extends over the source regions. The gate electrode is typically formed of polysilicon. A top-side metal layer electrically contacts the source regions and the body regions.Some designs of trench power MOSFETs further include a field plate located in the trench below the gate electrode.

[0003] Improvements in transistor performance can be achieved by reducing the gate resistance in such trench-gate transistor devices. For example, WO 2009 / 079473 A1 describes a transistor device with a metallic gate electrode in a gate trench with the goal of reducing the gate resistance. Further improvements in the performance of trench-gate transistor devices are desirable.

[0004] DE 102015121497 B4 discloses a semiconductor device comprising a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa structure is arranged between the first gate trench and the second gate trench. The mesa structure separates the first gate trench from the second gate trench. Each of the first and second gate trenches comprises first sections extending in a first direction and second sections connecting adjacent ones of the first sections. The second sections of the first gate trench are arranged opposite the second sections of the second gate trench with respect to a plane perpendicular to the first direction.The semiconductor device further comprises a plurality of gate contact trenches connected to the first gate trench, and a plurality of gate contacts arranged in the gate contact trenches and connected to a gate electrode within the first gate trench, wherein a distance between adjacent gate contact trenches is greater than a first distance between adjacent first portions of the first gate trench and the second gate trench.

[0005] US 6215149 B1 discloses a semiconductor device having a gate in a trench.

[0006] It is therefore the object of the present invention to provide an improved transistor device with a contact to a gate electrode in a trench and a corresponding method.

[0007] This problem is solved by the subject matter of the independent claims.

[0008] Preferred embodiments are given by the dependent claims. SUMMARY

[0009] In an exemplary embodiment, a transistor device is provided comprising a semiconductor substrate comprising at least one transistor cell. The transistor cell comprises an elongated trench and an elongated mesa; wherein the elongated trench is arranged in a first main surface of the semiconductor substrate and comprises an elongated gate electrode electrically separated from the semiconductor substrate by a gate dielectric. The transistor device further comprises a first insulating layer arranged on the first main surface and covering the elongated trench, and an elongated contact interconnect strip arranged on the first insulating layer and extending above and parallel to the elongated trench. The elongated contact interconnect strip is electrically connected to the elongated gate electrode in the elongated trench by at least one first contact extending through the first insulating layer.

[0010] In an exemplary embodiment, a method comprises forming a first insulating layer on a first main surface of a semiconductor substrate comprising at least one transistor cell, the transistor cell comprising an elongated trench and an elongated mesa, the elongated trench being arranged in the first main surface of the semiconductor substrate and comprising an elongated gate electrode electrically separated from the semiconductor substrate by a gate dielectric, the first insulating layer covering the elongated trench.The method further comprises forming at least one first contact in the first insulating layer connected to the elongated gate electrode in the elongated trench; forming an elongated contact interconnect strip on the first insulating layer and on the at least one first contact, the elongated contact interconnect strip extending vertically above and parallel to the gate trench; forming a second insulating layer on the elongated contact interconnect strip; forming a source metal layer on the second insulating layer; and electrically connecting the source metal layer to the mesa. The source metal layer extends above the elongated contact interconnect strip and is electrically insulated therefrom by the second insulating layer.

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The elements of the drawings are not necessarily to scale relative to one another. Like reference numerals indicate corresponding similar parts. The features of the various illustrated embodiments may be combined, provided they are not mutually exclusive. Exemplary embodiments are illustrated in the drawings and are described in detail in the following description. Fig. 1, which the Fig. 1A to Fig. 1J illustrates various views of a transistor device according to various embodiments. Fig. Figure 2 illustrates a graph of gate resistance and voltage simulated for transistor devices comprising different contact ratios (collective gate contact lengths). Fig. 3, which the Fig. 3A to Fig. 3H illustrates a method of manufacturing a transistor device. Fig. 4 illustrates a flowchart of a method of manufacturing a transistor device according to an embodiment. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "rear", "leading", "trailing", etc., is used with reference to the orientation of the described components. Since components of the embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention.The following detailed description thereof is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0014] A number of exemplary embodiments are explained below. In this case, identical structural features are identified by identical or similar reference numerals in the figures. In the context of the present description, "lateral" or "lateral direction" should be understood to mean a direction or extent that is generally parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction that is generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.

[0015] As used in this specification, when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "toward" another element, it may be directly on or directly extending to the other element, or there may also be intervening elements. Conversely, when an element is referred to as being "directly on" or extending "directly to" another element, there are no intervening elements.

[0016] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0017] As used herein, various device types and / or doped semiconductor regions may be identified as being n-type or p-type, but this is merely for convenience of description and is not intended to be limiting, and such identification may be replaced by the more general description of being of a "first conductivity type" or a "second, opposite conductivity type", where the first type may be either n-type or p-type and the second type may then be either p-type or n-type.

[0018] The figures illustrate relative doping concentrations by indicating “-” or “+” next to the doping type “n” or “p”. For example, “n - ” a doping concentration that is lower than the doping concentration of an “n” doping region, while an “n +"-doping region has a higher doping concentration than an "n"-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doping regions can have the same or different absolute doping concentrations.

[0019] According to the present disclosure, a transistor device with a reduced gate resistance can be provided that can avoid the use of a gate electrode formed entirely of a metal, such as tungsten, and thus avoid the potential disadvantages of metal gates, such as the introduction of stress into the silicon substrate, which can increase the on-resistance (Rdson), and the introduction of additional parasitic capacitance between gate and source.

[0020] In a metal gate, the gate electrode in the gate trench is formed of only one metal, and the metal is in contact with the gate insulator. In a hybrid gate, two different materials are present in the gate trench to form the gate electrode. The gate of the present disclosure can be described as a partial hybrid gate because, according to the present disclosure, two materials, e.g., a metal contact and a polysilicon gate electrode in contact with the gate insulator, are only present in the contact regions of the gate trench, and outside the contact regions, the gate electrode is formed of only polysilicon, which is in contact with the gate insulator.

[0021] In some embodiments, the transistor device is a MOSFET (metal oxide semiconductor field-effect transistor) device, such as a power MOSFET, for example, a vertical power MOSFET with a drift path perpendicular to the main surfaces. In some embodiments, the transistor device is an insulated gate bipolar transistor (IGBT) device or a bipolar transistor (BJT).

[0022] The electrodes or terminals of the transistor device are referred to herein as source, drain, and gate. As used herein, these terms also include the functionally equivalent terminals of other types of transistor devices, such as an insulated-gate bipolar transistor (IGBT). For example, the term "source" as used herein includes not only a source of a MOSFET device and a superjunction device, but also an emitter of an insulated-gate bipolar transistor (IGBT) device and an emitter of a bipolar transistor (BJT) device; the term "drain" includes not only a drain of a MOSFET device or a superjunction device, but also a collector of an IGBT device and a collector of a BJT device; and the term "gate" includes not only a gate of a MOSFET device or a superjunction device, but also a gate of an IGBT device and a base of a BJT device.

[0023] According to embodiments, the present disclosure proposes reducing the gate resistance of a transistor device, such as a power MOSFET, by using electrically conductive strips, e.g., tungsten strips, extending above the interlayer dielectric (ILD) parallel to the gate trenches in which the gate electrode is positioned. The gate electrode itself may be formed of polysilicon. The trench in which the gate electrode is arranged may have an elongated strip-like shape having a length (its longest dimension) extending parallel to the first main surface. The length may be measured along a first lateral direction of the semiconductor substrate. The length of the trench may be greater than its depth from the first main surface, which in turn may be greater than a width of the trench. The width may be measured along a second lateral direction of the semiconductor substrate (e.g.,in a direction parallel to the first main surface and orthogonal to the direction in which the length of the trench is taken). The electrically conductive strips may be contacted with the gate polysilicon in the corresponding trenches only at specific points of the chip layout, i.e., only at one or more specific points along the length of the gate trench. A plurality of contacts may be used, spaced at intervals along the length of the trench and at intervals along the length of the gate electrode. The electrically conductive strips connected to the gate electrode are located at least partially beneath the current source metal electrically connected to the source regions of the power MOSFET and are electrically insulated from the overlying current source metal by a further interlayer dielectric.One or more of the contacts between the gate electrode and the overlying electrically conductive strip are located below the power source metal.

[0024] The number of contacts per trench combined with the length of each contact can be referred to as the contact duty cycle or the collective contact length, and defines the trade-off between gate resistance, parasitic gate-source capacitance, and Rdson increase caused by voltage. The contact duty cycle is smaller than the trench length. For example, the collective contact length can be between 10% and 90%, or between 10% and 60% of the trench length, and / or between 10% and 90%, or between 10% and 60% of the gate electrode length. In other words, the duty cycle / collective length can specify the rate at which a gate electrode in a given trench is brought into contact with the overlying conductive stripe via the contacts.The fabrication of the electrically conductive strips can be integrated into a back-end-of-line (BEOL) process, and only one additional (tungsten) lithography may be required. The structures described here can provide gate resistance reduction with less penalty, such as a smaller increase in parasitic capacitance and voltage-induced Rdson. Furthermore, layout flexibility can also be provided, as the trade-off between gate resistance, parasitic capacitance, and voltage-induced Rdson penalty can be controlled by the duty cycle of the gate contacts (i.e., the selection of the number of contacts per trench and the length of each contact). Reduced gate resistance can improve the efficiency of the transistor device.

[0025] Fig. 1, which the Fig. 1A to Fig. 1H illustrates various views of a transistor device 10 according to various embodiments.

[0026] Fig. 1A illustrates a plan view of the transistor device 10, Fig. 1B a cross-sectional view along the Fig. Line A-A' shown in Figure 1A, Fig. 1C a cross-sectional view along the line B-B', Fig. 1D is a cross-sectional view taken along line CC' according to one embodiment. Fig. 1E illustrates a cross-sectional view along line CC' for a transistor device 10' according to an alternative embodiment. Fig. Figure 1F illustrates a top view of the transistor device 10 showing the line DD', and Fig. Figure 1G illustrates a cross-sectional view along line DD' of the Fig. 1D illustrated transistor device 10. Fig. Figure 1H illustrates a cross-sectional view along line DD' for the transistor device 10' of the alternative embodiment of Fig. 1E.

[0027] The transistor device 10 comprises a semiconductor substrate 11 comprising at least one transistor cell 12. Typically, the transistor device 10 comprises a plurality of transistor cells 12 electrically coupled in parallel to provide a single transistor device, e.g., a switch. The semiconductor substrate 11 may comprise silicon, for example, a single-crystal silicon wafer or a monocrystalline silicon epitaxial layer formed on a base substrate. Each transistor cell 12 comprises an elongated trench 13 and an elongated mesa 14. The elongated trench 13 is arranged in a first main surface 15 of the semiconductor substrate 11. The elongated trenches 13 each have a strip-like shape having a length extending parallel to the first main surface 15. The length of the trench 13 is greater than its depth in a direction perpendicular to the first main surface 15, and the depth is greater than its width.The elongated trenches 13 extend parallel to each other, such that an elongated mesa 14 is formed by the portion of the semiconductor substrate 11 positioned between two adjacent elongated trenches 13, i.e., extending between opposite sidewalls 18 of two adjacent trenches 13. An elongated gate electrode 16 is formed in the elongated strip-like trench 13 and is electrically separated from the semiconductor substrate 11 by a gate dielectric 17 located on the sidewalls 18 of the trench 13.

[0028] In some embodiments, such as the Fig. 1, the trench 13 further comprises an electrically conductive field plate 19 positioned towards the lower portion of the trench 13 below the gate electrode 16. The field plate 19 may be electrically insulated from the semiconductor substrate 11 and from the gate electrode 16, which is positioned towards the top of the trench 13, by a field plate dielectric 20 lining the base 21 and sidewalls 18 of the trench 13 and the region between the field plate 19 and the gate electrode 16. The field plate 19 is also elongated and strip-like. The gate electrode 16 and the field plate 19 may be formed of polysilicon and are electrically conductive. The gate electrode 16 may be covered by dielectric material 22 that fills the top of the trench 13 and that is substantially coplanar with the first main surface 15 of the semiconductor substrate 11.The gate dielectric 17, the field plate dielectric 20 and the dielectric material 22 may be formed, for example, from silicon oxide.

[0029] A first electrically insulating layer 23, which may be an oxide such as silicon oxide, is disposed on the first main surface 15 and covers the trench 13 and also the mesa 14. In some embodiments, the first insulating layer 23 comprises two or more sublayers, for example, silicon nitride and silicon oxide. An elongated contact connection strip 24 is disposed on the first insulating layer 23 and extends above and parallel to the elongated trench 13. The elongated contact connection strip 24 is electrically conductive and has a strip-like structure and is positioned vertically above the gate electrode 16 and has a length that is greater than its width and its height. The contact connection strip 24 can be considered to be vertically aligned with the elongated trench 13.In some embodiments, the contact connection strip 24 has a width that is smaller than the width of the gate electrode 16 and the trench 13. The elongated contact connection strip 24 is electrically connected to the elongated gate electrode 16 in the elongated trench 13 by at least one gate contact 25 extending through the first insulating layer 23. The gate contact 25 is in the configuration shown in FIG. Fig. 1C, which shows the plane along the axis shown in Fig. 1A. The gate contact 25 extends between the contact connection strip 24 and the gate electrode 16 and through the first insulating layer 23 disposed on the first main surface 15. The gate contact 25 may also extend through the dielectric 22 disposed on the top surface of the gate electrode 16. In some embodiments, the base of the gate contact 25 may be positioned within the height and within the material of the gate electrode 16.

[0030] A plurality of gate contacts 25 is typically provided for each trench and for each gate electrode 16. As shown in the plan view of Fig. 1A and also in a comparison of the cross-sectional views along the line AA' of Fig. 1B and line BB' from Fig. 1C, in embodiments in which a plurality of gate contacts 25 are provided, the individual gate contacts 25 are spaced from each other at intervals along the length of the trench 13. Each of the gate contacts 25 may be elongated, e.g., its length in the direction of the length of the trench 13 is greater than its width in the direction of the width of the trench 13. The plurality of gate contacts 25 for each trench 23 and for the gate electrode 16 arranged in this trench are electrically connected to each other by the electrically conductive contact connection strip 24 located above this trench 13 and on the first electrically insulating layer 23.

[0031] A second electrically insulating layer 28 may be positioned on the first insulating layer 23 and may cover the contact connection strip 24. The second electrically insulating layer may be formed from an oxide, e.g., silicon oxide. Alternatively, the second electrically insulating layer may comprise two or more sublayers, e.g., silicon nitride and silicon oxide. A source metal layer 26 and a gate metal layer 27 may be positioned on the first main surface 15 and on the second electrically insulating layer 28, respectively. The gate metal layer 27 may be laterally spaced from the source metal layer 26.The source metal layer 26 may extend over the contact connection strip 24 and may be electrically insulated from the contact connection strip 24 by the second electrically insulating layer 28, which may be positioned on the first electrically insulating layer 23 and may cover the elongated contact connection strip 24.

[0032] As shown in the top view of Fig. 1A and the cross-sectional view along line BB of Fig. As can be seen in Figure 1C, one or more of the gate contacts 25 are located below the source metal layer 26 and are electrically insulated from the overlying source metal layer 26 by the second electrically insulating layer 28. The plurality of gate contacts 25 are electrically connected to each other by the contact interconnect strip 24. The contact interconnect strip 24 may extend below the source metal layer 26 and may also extend below the gate metal layer 27.

[0033] As shown in the cross-sectional view along the line DD' along the length of the trench 13 (such as along the first lateral direction) shown in Fig. 1F and Fig. 1G, the gate metal contacts 25 may be electrically connected to the gate metal layer 27 via the contact connection strip 24. The second electrically insulating layer 28 may include a first opening 29 exposing a portion of the contact connection strip 24 at a location laterally adjacent to the source metal layer 26 and below the gate metal layer 27. In this embodiment, the gate metal layer 27 may extend through the first opening 29 and may form an electrical contact 38 with the contact connection strip 24. Alternatively, as shown in Fig. 1I illustrates, a separate contact 39 may be formed in the first opening 29, and a planar gate metal layer 27 may be formed extending onto the contact 39 in the first opening 29 and onto the second electrically insulating layer 28. The contact 39 may be formed of the same material as the planar gate metal layer 27, for example, tungsten or aluminum.

[0034] Each of the gate contacts 25 can have a length L ind (such as its longest direction) which may extend in the longest direction of the trench 13. Since each of the gate contacts 25 has an individual length L ind the gate contacts 25 together can have a collective length L c which is the sum of the individual lengths L ind For example, for n gate contacts 25, each with an individual length L ind where n is a natural number, L c = n L ind . In Fig. 1F, three gate contacts 25 are shown so that L c = 3 L ind . If a single gate contact 25 is used, then L c = L ind . The gate trench 13 has a length Lt. The number of gate contacts 25 and the length of the individual gate contacts 25, L ind , can be selected so that the collective length L c has a value between 10% and 90% of the total length Lt of trench 13, ie 0.1L t ≤ L c ≤ 0.9Lt. This value is also referred to as duty cycle above. In some embodiments, 0.1L t ≤ L c ≤ 0.6Lt.

[0035] In some embodiments, the contact connection strip 24 has a length L s and the length of the contact connection strip 24 is at least 70% of the length It of the trench 13, ie L s ≥ 0.7Lt. In some embodiments, 0.7lt ≤ L s ≤ According to

[0036] With reference to the Fig. 1A to Fig. 1C, the source metal layer 26 may be electrically connected to the mesa 14 by a mesa contact 30, which may extend from the source metal layer 26 through the first and second insulating layers 23, 28 and into the upper portion of the mesa 14.

[0037] The mesa 14 may include a drift region 31 of a first conductivity type, e.g., n-type, a body region 32 disposed on the drift region 31, wherein the body region 32 comprises a second conductivity type opposite to the first conductivity type, e.g., p-type if the first conductivity type is n-type, and a source region 33, which may be disposed on or in the body region 32 and which may comprise the first conductivity type. A drain region comprising the first conductivity type may be formed on the second main surface of the semiconductor substrate 11, which may be opposite to the first main surface 15 and which is not illustrated in the drawings. The mesa contact 30 typically extends through the source region 33 and is in contact with the body region 32. As shown in the top view of Fig. As can be seen in Figure 1A, the mesa contact 30 may be elongated and may have a longer length than the individual gate contacts 25. The transistor device 10 may be a MOSFET device, such as a power MOSFET with a vertical drift path, often referred to as a vertical MOSFET because the drift path typically extends perpendicular to the first main surface 15 of the substrate 11.

[0038] The lateral extent of the source region 33 may correspond to the lateral extent of the active area of ​​the transistor device 10 and is in the plan view of Fig. 1A by the dashed line 37. At least one, and in some embodiments, all, of the contacts 25 to the gate electrode 16 in the trench 13 may be located within the boundary of the active area 37 and below the source metal layer 26. The contacts 30 to the mesa 15 may be located in the active area 37 and below the source metal layer 26. In some embodiments, a portion of the contact 30 is located outside the active area 37 in a region of the semiconductor substrate 11 that includes a body region but no source region. This arrangement may be used to suppress parasitic bipolars.

[0039] Fig. Figure 1D illustrates a cross-sectional view along the Fig. Line C-C' shown in Figure 1A. Fig. 1D illustrates a portion of the transistor device 10 outside the active region 37 of the transistor device 10. The contact 35 to the field plate 19, located in the lower portion of the trenches 13, may be positioned in this portion of the transistor device 10. In at least a portion of the trench 13 positioned outside the active region 37, the trench 13 may be without a gate electrode 16. The length of the gate electrode 16 may therefore be smaller than the length of the trench 13. The electrical contact 35 to the field plate 19, positioned on the lower portion of the trench 13, may be positioned in portions of the length of the trench 13 that are not occupied by the gate electrode 16.

[0040] Fig. Figure 1G illustrates a cross-sectional view along the length of the trench 13 along the line D-D' shown in the plan view of Fig. 1F. With reference to the Fig. 1D and Fig. 1G, the field plate 19 may have an extension in the portion of the trench 13 free of the gate electrode, such that the extension extends almost to the first main surface 15. The field plate 19 may have a top surface 34 that is substantially coplanar with the top surface of the gate electrode 17 in this portion of the trench 13. The extension may be formed of the same material as the field plate 19, for example, polysilicon.

[0041] In one embodiment, the elongated contact interconnect strip 24 is divided into two separate sections 24', 24'' and spaced apart by a gap. The first section 24' may be positioned in the active area 37 of the transistor device 10 and may provide the contact interconnect strip 24 that is electrically connected to the gate contacts 25. The second section 24'', laterally spaced apart from the first section 24', may be positioned outside the active area 37 of the transistor device 10. A portion of the first section 24' and the second section 24'' may be positioned outside the active area 37.

[0042] The first portion 24' may provide the contact connection layer 24' and may be electrically connected to the gate electrode 16 through the plurality of gate contacts 25. The second portion 24'' may be positioned over the extension of the field plate 19 and may be electrically connected to the field plate 19 through a field plate contact 35 extending between the field plate 19 and the second portion 24''. The second portion 24'' may be positioned over and may overlap the trench 13 and be aligned with the first portion 24' in the longitudinal direction of the trench 13. The field plate contact 35 may be formed from a metal, for example, tungsten.

[0043] The second portion 24" is electrically connected to the source metal layer 26 by a contact 50 extending through a third opening 36 in the second insulating layer 28. The contact 50 extends between the second portion 24" and the source metal layer 26. In some embodiments, such as the one shown in Fig. 1H, the contact 50 is integral with the source metal layer 26. In other embodiments, the contact 50 is a separate contact and the source metal layer 26 is located on this separate contact.

[0044] In some embodiments, such as the Fig. 1J, the field plate contact 35 may be located at a lateral position that is below the source metal layer 26, but separated from the overlying source metal layer 26 by the second electrically insulating layer 28. The field plate contact 35 is electrically connected to the source metal layer 26 by the contact 50, which is located in another portion of the trench 13 and extends through the second insulating layer 28 and between the second portion 24'' of the contact connection layer 24 and the overlying source metal layer 26. In this embodiment, the contact 50 is a separate contact 51, and the source metal layer 26 is disposed on the contact 51. The second portion 24'' may form part of a redistribution structure between the field plate 19 and the source metal layer 26, as can be seen, for example, in the cross-sectional view along line DD', as shown in Fig. 1G and Fig. 1J.

[0045] In some embodiments, the field plate 19 may extend toward the upper portion of the trench 13, as shown in the cross-sectional views of Fig. 1D and Fig. 1G for the transistor device 10.

[0046] Fig. 1E and Fig. 1H illustrate an alternative embodiment of the transistor device 10' in which the height of the field plate 19 is substantially uniform over the entire length of the trench 13 (e.g., also in the regions of the trench 13 not occupied by the gate electrode 16). In this embodiment, the field plate contact 35 may have a greater depth and may extend from the top surface of the first insulating layer 23 through the insulating material 18 located in the trench to the field plate 19 located toward the lower portion of the trench 13. The other features of the transistor device 10' correspond to those described for the transistor device 10.

[0047] As can be seen in the cross-sectional views along the length of the trench 13 of the transistor devices 10, 10' shown in Fig. 1G or Fig. 1H, the second insulating layer 28 may include a second opening 36 located above the second portion 24" of the contact connection strip, which may expose the second portion 24". The source metal layer 26 may extend into the second opening 36 and may be in contact with the second portion 24" to electrically connect the field plate 19 located in the bottom of the trench 13 to the source metal layer 26 via the field plate contact 35 and the second portion 24".

[0048] The field plate contact 35 may have an elongated structure. In some embodiments, more than one field plate contact 35 may be provided for each trench 13. In some embodiments, two or more field plate contacts 35 may be provided located at different regions along the length of the trench 13. At each of the regions of the trench 13 where a field plate contact 35 is located, the gate contact 16 is omitted. In these embodiments, two or more separate portions of the source metal layer 26 may be provided.

[0049] In some embodiments, the gate electrode 16 and the field plate 19 are formed of polysilicon. The gate contact 24, the mesa contact 30, the field plate contact 35, and the contact connection strip 24 and the separate sections 24', 24'', if present, may be formed of tungsten. The source metal layer 26 may comprise aluminum, for example, an aluminum-copper alloy. In some embodiments, the source metal layer 26 comprises two or more sublayers, for example, a first sublayer formed of tungsten and a second sublayer formed of aluminum-copper alloy formed on the first sublayer. The gate metal layer 27 may comprise aluminum, for example, an aluminum-copper alloy.In some embodiments, the gate metal layer 27 comprises two or more sublayers, for example, a first sublayer formed of tungsten and a second sublayer formed of aluminum-copper alloy formed on the first sublayer.

[0050] Fig. Figure 2 illustrates a plot of gate resistance and normalized voltage simulated for transistor devices comprising different gate contact duty cycles. The duty cycle refers to the number of individual gate contacts and the length of each of the individual gate contacts, resulting in a collective gate contact length relative to the total gate electrode length.

[0051] Fig. Figure 2 shows that for the simulated conditions, there is a trade-off between gate resistance Rg and normalized voltage. As the collective gate contact length increases from 0% to 100%, the normalized voltage increases monotonically from 0 to 1. As the collective gate contact length increases from 0%, the gate resistance Rg rapidly decreases from about 1.75 ohms for a collective contact length of 1% to a value of just over 0.1 ohms for a collective contact length of up to about 5%. For increased contact ratios up to 100%, the gate resistance Rg is essentially constant around 0.1 ohms or decreases slightly. A contact ratio of 0% corresponds to a device with a polysilicon gate electrode. In practice, a device with a polysilicon gate electrode includes a contact with the polysilicon gate electrode, which is often formed of a metal.Therefore, for a practical device, the contact ratio for a device comprising a polysilicon gate is slightly greater than 0%, for example, 0.1% or 0.5%. A contact ratio of 100% corresponds to a device with a metal gate electrode, for example, a tungsten gate electrode. A tungsten gate has a low gate resistance Rg but a high normalized voltage ("stress"), whereas a polysilicon gate electrode has a low normalized voltage ("stress") but a higher gate resistance.

[0052] This compromise between gate resistance Rg and normalized voltage ("stress") can be tuned by varying the contact ratio of the gate contacts along a particular trench, i.e., by varying the collective length of the gate contacts relative to the length of the gate electrode within the trench. This could be achieved by varying the length of the gate contacts 25 and / or by varying the number of gate contacts 25.

[0053] Out of Fig. Figure 2 shows that for these simulation conditions, a duty cycle of 10% enables a reduced gate resistance with a much lower stress penalty compared to a tungsten gate (100%). In other words, the collective length of a large number of gate contacts, approximately 10% of the total gate electrode length, results in a low gate resistance Rg and a low normalized stress.

[0054] A method of manufacturing a transistor device will now be described with reference to Fig. 3, which describes the Fig. 3A to Fig. 3H. The process can be used to produce the Fig. 1 illustrated transistor devices 10, 10'. Each of the Fig. 3A to Fig. Figure 3H illustrates a cross-sectional view at two positions along the length of trench 13 corresponding to lines AA' and BB' of Fig. 1A.

[0055] Fig. 3A illustrates cross-sectional views of the semiconductor substrate 11 in which the elongated strip-like trenches 13 have been formed, including the field plate 19 toward the bottom of the trench 13 and the gate electrode 16 toward the top of the trench 13. The field plate 19 is electrically separated from the semiconductor substrate 11 by at least one electrically insulating layer 20, which may cover the base 21 and sidewalls 18 of the trench 13 and the space between the field plate 19 and the gate electrode 16. The gate electrode 16 is separated from the sidewalls 18 of the trench 13 by a gate insulating layer 17 and may be covered or covered at the top by the electrically insulating layer 22. The upper surface of the insulating layer 22 may be coplanar with the first main surface 15 of the substrate 11.The body region 32 and the source region 33 may be formed in the elongated strip-like mesas 14 formed by the portions of the semiconductor substrate 11 between the sidewalls of adjacent trenches 13. The semiconductor substrate 11 may be formed of silicon, and the transistor device to be formed in the substrate 11 may be a MOSFET device with a vertical drift path.

[0056] With reference to Fig. 3B, a first insulating layer 23 may be formed on the first main surface 15 of the semiconductor substrate 11 and may cover the elongated strip-like mesas 14 and the elongated trenches 13. Referring to Fig. 3C, a first opening 40 may be formed at a predetermined position along the length of the trench 13. The first opening 40 may extend through the first insulating layer 23 and into the trench 13 and may have a base formed through or within the material of the gate electrode 16, which may be made of polysilicon, for example. Typically, two or more openings 40 are formed, spaced at intervals along the length of the trench 13. The length of the trench 13 is its longest direction extending into the plane of the drawing. The spacing of the first openings 40, each of which may have a length less than the length of the trench 13, may be Fig. 3C in that the opening 40 is visible in the cross-sectional view along line B-B', but not in the cross-sectional view along line AA'. A second opening 41 may be formed, positioned above the mesa 14, and may extend along most of the length of the mesa 14. The second opening 41 may be visible in the cross-sectional view along line BB' and in the cross-sectional view along line AA' and may have a greater length than the first opening 40. The first and second openings 40, 41 may be formed in the same process, for example, by appropriately patterning a mask formed on the first insulating layer 23 and etching the exposed portions of the first insulating layer 23, the insulating layer 22, and possibly the gate electrode 16 in the trench 13, or the first insulating layer 23 and the semiconductor material of the mesa 14.

[0057] With reference to Fig. 3D, an electrically conductive layer 43, made of tungsten, for example, is formed on the upper surface 42 of the first insulating layer 23, which may fill the first and second openings 40, 41, thereby forming one or more contacts 25 to the gate electrode 16 in each trench 13 and a contact 30 to the mesa 14, respectively. The electrically conductive layer 43 may also extend over the upper surface 42 of the first insulating layer 23.

[0058] With reference to Fig. 3E, the electrically conductive layer 43 is patterned to form an electrically conductive stripe 24 positioned above each of the trenches 13. The individual stripes 24 may each have a width greater than the width of the first opening 40 and therefore greater than the width of each of the gate contacts 25. A single stripe 24 may be in contact with several and / or all of the gate contacts 25 formed on the gate electrode 16 within this trench 13 and may form a gate contact connection stripe 24 positioned in a plane above the gate electrode 16.

[0059] The conductive layer 43 may also be patterned to provide an elongated stripe 44 positioned above the mesa 14 and in contact with the mesa contact 30. The conductive layer 43 may therefore be patterned to provide a plurality of separate stripe-like structures 24, 44 positioned on the upper surface 42 of the first insulating layer 23 and spaced apart from each other, e.g., such that the stripes 24, 44 are alternately positioned on the first insulating layer 23. In some positions along the length of the trench 13, as in the cross-sectional view along the line AA' in Fig. 3E, the stripe 24 is vertically spaced and electrically insulated from the gate electrode 16 at this position by the electrically insulating layer 22 arranged on top of the trench 13 and by the first insulating layer 23. In other positions, such as the one shown in the cross-sectional view along the line 14 in Fig. 3E, the connecting strip 24 is arranged directly on the gate contacts 25 such that the connecting strip 24 is electrically connected to the elongated gate electrode 16 at intervals.

[0060] With reference to Fig. 3F, a second electrically insulating layer 28 is formed covering the strips 24, 44 and the first electrically insulating layer 23. Referring to Fig. 3G, a third opening 45 is formed in the second electrically insulating layer 28. The third opening 45 is positioned above the mesa 14 and may expose the strip 44 disposed on the first insulating layer 23 above the mesa 14. The third opening 45 may have a width such that contiguous regions of the second electrically insulating layer 28 are exposed. The third opening 45 may have a length corresponding to the length of the elongated mesa 14.

[0061] With reference to Fig. 3H, an electrically conductive material 26 may then be formed in the third opening 45, which may also extend over the top surface 46 of the second electrically insulating layer 28. The electrically conductive material 26 may be electrically connected to the mesa 14 (such as to one or more of the source region 33 and the body region 32) and may provide a source metallization layer. The source metallization layer 26 may extend over the gate contact connection strip 24 and be electrically insulated therefrom by the intervening second insulating layer 28.

[0062] In some embodiments, such as the Fig. 3H, the source metal layer 26 comprises two or more sublayers. A first sublayer 47 is deposited over the top surface 46 and sidewalls 47 of the opening 45 and over the exposed portions 49 of the top surface 42 of the first electrically insulating layer 23 and on the electrically conductive strip 44. The first sublayer 47 may be formed of tungsten, for example. A second sublayer 48 is then deposited, filling the remainder of the third opening 45 extending beyond the first sublayer 47. The second sublayer 48 may comprise aluminum and / or copper, or may comprise aluminum-copper alloy. Thus, the electrically conductive layer 26 is electrically connected to the mesa 14 via the mesa contact 30 formed in the second opening 41.

[0063] As an alternative to the above with reference to Fig. In the process discussed in Figure 3, a dual damascene process can be used to realize the electrically conductive strip 24 above the trench 13, in which the polysilicon gate 16 is formed, and the contacts 25 to the polysilicon gate electrode 16. In other words, the contacts 25 and the strip 24 are formed in a single deposition process and are integral. Likewise, the contact 30 and the strip 44 of the mesa can be formed using the same dual damascene process and be integral.

[0064] In this alternative process, a first lithography mask and etch step defines the position of the first contact holes 40. The first contact holes are initially etched into the dielectric material 23 to a given depth, but do not reach the polysilicon gate electrode 16. A second lithography mask and etch step is used to pattern elongated openings for the stripes 24 within the dielectric material 23. In this second etch step, the first contact holes 40 are etched further downward, i.e., their depth is extended to the gate electrode 16. A TiSi sublayer is formed on the polysilicon gate electrode, and the contact holes 40 and elongated openings are filled with tungsten to form the gate contacts 25 and the stripe 24, respectively. Optionally, a CMP step can be used to remove the tungsten from the wafer surface.This alternative process sequence may be advantageous when processing in combination with the other metallization layers of the device is desirable.

[0065] Fig. 4 illustrates a flowchart 100 of a method for fabricating a transistor device. In box 101, a first insulating layer is formed on a first main surface of a semiconductor substrate comprising at least one transistor cell, wherein the transistor cell comprises an elongated trench and an elongated mesa. The elongated trench is disposed in the first main surface of the semiconductor substrate and comprises an elongated gate electrode electrically separated from the semiconductor substrate by a gate dielectric. The first insulating layer covers the elongated trench.

[0066] In box 102, at least one first contact is formed in the first insulating layer. The at least one first contact is connected to the elongated gate electrode in the elongated trench.

[0067] In box 103, a contact connection strip is formed on the first insulating layer and on the at least one first contact. The contact connection strip is located vertically above and extends parallel to the gate trench, such that the contact connection strip is vertically aligned with the gate trench.

[0068] In box 105, a second insulating layer is formed on the contact connection strip,

[0069] In box 106, a source metal layer is formed on the second insulating layer. In box 107, the source metal layer is electrically connected to the mesa. The source metal layer extends over the contact connection strip and is electrically insulated therefrom by the second insulating layer. The source metal layer may be electrically connected to the mesa by forming a mesa contact in the first insulating layer, for example, simultaneously with the formation of the at least one contact connected to the elongated gate electrode positioned in the trench.

[0070] In one embodiment, a plurality of contact connecting strips are connected to a common gate metallization layer, e.g., a gate pad or a gate slider or gate finger, by a contact extending from the contact connecting strip to the gate metallization layer. The gate metallization layer is arranged on the first main surface of the semiconductor substrate laterally adjacent to the source metallization layer, e.g., a source pad.

[0071] In summary, a transistor device, for example, a power MOSFET with a vertical drift path, is provided, which has a lower gate resistance. The gate electrode within the respective gate trenches may be formed of polysilicon and is connected to an additional gate contact connection strip located vertically above the trench by at least one, typically a plurality of, contacts located below the power source metallization. The cross-sectional area of ​​contact between the gate electrode and the metallization structure of the device is increased due to the larger contact area between the gate electrode and the plurality of gate contacts located at intervals along the length of the trench.An additional chip area is not required for the larger contact area, since the additional contacts to the gate electrode and the electrical connection of these additional contacts to each other through the additional gate contact connection strip are located under the source power metallization.

[0072] Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the disclosure. Examples

[0073] Example 1. Transistor device comprising: a semiconductor substrate comprising at least one transistor cell, the transistor cell comprising an elongated trench and an elongated mesa; wherein the elongated trench is disposed in a first major surface of the semiconductor substrate and comprises an elongated gate electrode electrically separated from the semiconductor substrate by a gate dielectric; a first insulating layer disposed on the first main surface and covering the elongated trench; an elongated contact interconnect strip disposed on the first insulating layer and extending above and parallel to the elongated trench, the elongated contact interconnect strip being electrically connected to the elongated gate electrode in the elongated trench by at least one first contact extending through the first insulating layer.

[0074] Example 2. The transistor device of Example 1, further comprising a source metal layer electrically connected to the mesa, wherein the source metal layer extends over and is electrically insulated from the contact interconnect strip.

[0075] Example 3. The transistor device of Example 2, wherein the contact connection strip is located vertically below the source metal layer and is electrically insulated from the source metal layer by a second insulating layer.

[0076] Example 4. The transistor device of Example 2 or Example 3, wherein at least one of the first contacts is located vertically below the source metal layer.

[0077] Example 5. The transistor device of any one of examples 1 to 4, wherein the at least one of the first contacts extends through the first insulating layer between the gate electrode and the elongated contact connection strip.

[0078] Example 6. The transistor device of any one of examples 1 to 5, wherein a plurality of first contacts are provided spaced along the length of the elongated trench.

[0079] Example 7. The transistor device of any one of Examples 2 to 6, wherein two or more of the first contacts are disposed below and covered by the source metal layer.

[0080] Example 8. The transistor device according to any one of examples 1 to 7, wherein the at least one first contact has a collective length L c and the gate trench has a length Lt, where 0.1L t ≤ L c ≤ 0.9Lt.

[0081] Example 9. Transistor device according to Example 8, wherein 0.1L t ≤ L c ≤ 0.6Lt.

[0082] Example 10. The transistor device according to Example 8 or Example 9, wherein the contact connection strip has a length L s where L s ≥ 0.7Lt

[0083] Example 11. Transistor device according to Example 10, wherein 0.7L s ≤ L t ≤ L s .

[0084] Example 12. The transistor device according to any one of Examples 1 to 11, further comprising: a second insulating layer disposed on the contact connection strip and on the first insulating layer; an elongated mesa contact; wherein the source metal layer is disposed on the second insulating layer and the elongated mesa contact extends from the source metal layer through the first and second insulating layers and into the mesa.

[0085] Example 13. The transistor device of Example 12, further comprising a gate metal layer disposed on the second insulating layer and laterally adjacent to and spaced from the source metal layer, the gate metal layer being electrically connected to the contact interconnect strip by a second contact extending through the second insulating layer and between the gate metal layer and the contact interconnect strip.

[0086] Example 14. The transistor device of Example 12 or Example 13, wherein the second insulating layer comprises a second opening exposing the contact connection strip, and the gate metal layer is disposed in the first opening to form the second contact.

[0087] Example 15. The transistor device of any one of Examples 1 to 14, wherein the gate trench further comprises a field plate disposed in a lower portion of the trench and electrically separated from the semiconductor substrate and the elongated gate electrode by a field dielectric.

[0088] Example 16. The transistor device of Example 15, wherein the field plate is electrically connected to the source metal layer by a field plate contact extending from the field plate through the first and second insulating layers to the source metal layer.

[0089] Example 17. The transistor device of Example 15 or Example 16, wherein the field plate contact is located in a portion of the gate trench that is laterally outside the active area of ​​the transistor device and below the source metal layer.

[0090] Example 18. The transistor device of any one of examples 15 to 17, wherein the contact connection strip comprises a first portion and a second portion laterally spaced apart by the first insulating layer, the first portion electrically connected to the first contacts and the second portion electrically connected to the field plate contact.

[0091] Example 19. The transistor device of Example 18, wherein the second portion is electrically connected to the source metal layer.

[0092] Example 20. The transistor device of Example 18 or Example 19, wherein the second insulating layer comprises a first opening exposing the second portion, and the source metal layer is disposed in the first opening.

[0093] Example 21. The transistor device of any one of Examples 1 to 20, wherein an upper surface of the gate electrode is covered by an upper portion of the gate dielectric, and the first insulating layer is disposed on the upper portion of the gate dielectric.

[0094] Example 22. The transistor device of any one of Examples 1 to 21, wherein the gate electrode is formed of polysilicon, the first contact comprises tungsten, and the contact connection strip comprises tungsten.

[0095] Example 23. The transistor device of any one of Examples 1 to 22, wherein the elongated mesa contact comprises tungsten and the source metal layer comprises Al.

[0096] Example 24. The transistor device of any one of Examples 1 to 23, wherein the first contact, the contact connecting strip, and the elongated mesa contact are formed of tungsten.

[0097] Example 25. The transistor device of any one of Examples 2 to 24, wherein the source metal layer comprises an alloy comprising Al and Cu.

[0098] Example 26. The transistor device of any one of Examples 2 to 25, wherein the source metal layer comprises a first sublayer formed of tungsten and a second sublayer formed of an AlCu alloy.

[0099] Example 27. The transistor device according to any one of Examples 1 to 26, wherein the semiconductor substrate is formed of silicon.

[0100] Example 28. The transistor device of any one of examples 1 to 27, wherein the elongated mesa comprises a drift region of a first conductivity type, a body region of a second conductivity type opposite to the first conductivity, the body region being arranged on the drift region, and a source region of the first conductivity type formed on and / or in the body region, a drain region of the first conductivity type being arranged in or on a second main surface of the semiconductor substrate opposite to the first main surface.

[0101] Example 29. The transistor device of any one of examples 1 to 28, wherein the transistor device is a MOSFET device, a vertical MOSFET device, or an IGBT.

[0102] Example 30. A method comprising: Forming a first insulating layer on a first main surface of a semiconductor substrate comprising at least one transistor cell, wherein the transistor cell comprises an elongated trench and an elongated mesa, wherein the elongated trench is arranged in the first main surface of the semiconductor substrate and comprises an elongated gate electrode electrically separated from the semiconductor substrate by a gate dielectric, wherein the first insulating layer covers the elongated trench, Forming at least one first contact in the first insulating layer connected to the elongated gate electrode in the elongated trench; Forming a contact connection strip on the first insulating layer, which is electrically connected to the at least one first contact, wherein the contact connection strip extends vertically above and parallel to the gate trench, Forming a second insulating layer on the contact connection strip, Forming a source metal layer on the second insulating layer; electrically connecting the source metal layer to the mesa, wherein the source metal layer extends over the contact connection strip and is electrically insulated therefrom by the second insulating layer.

[0103] Example 31. The method of Example 30, further comprising: Forming at least one first opening in the first insulating layer exposing the gate electrode and at least one elongated second opening in the first insulating layer extending into the mesa; Forming a first metal layer in the first and second openings and on the first insulating layer, and Patterning the first metal layer to form the elongated contact interconnect strip and the elongated mesa contact;

[0104] Example 32. The method of Example 31, further comprising: wherein electrically connecting the source metal layer to the mesa comprises: Forming an elongated third opening in the second insulating layer above the elongated mesa contact, and Forming the source metal layer in the third opening and over the second insulating layer.

[0105] Example 33. The method of any one of examples 30 to 32, wherein the elongated mesa comprises a drift region of a first conductivity type, a body region of a second conductivity type opposite to the first conductivity, the body region being arranged on the drift region, and a source region of the first conductivity type formed on and / or in the body region, a drain region of the first conductivity type being arranged in or on a second main surface of the semiconductor substrate opposite to the first main surface.

[0106] Example 34. The method of any one of examples 30 to 33, wherein forming a contact interconnect strip on the first insulating layer electrically connected to the at least one first contact is performed after forming the at least one first contact and comprises forming the contact interconnect strip on the at least one first contact and on the first insulating layer.

[0107] Example 35. The method of any one of examples 30 to 33, wherein a single deposition process is used to form the at least one first contact in the first insulating layer connected to the elongated gate electrode in the elongated trench and the contact connection strip on the first insulating layer electrically connected to the at least one first contact.

[0108] Spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like are used for ease of description to indicate the positioning of one element relative to a second. These terms are intended to encompass various orientations of the device in addition to the various orientations illustrated in the figures. Further, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the specification.

[0109] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to understand that the features of the various embodiments described herein may be combined with one another unless specifically stated otherwise.

[0110] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] Transistor device comprising: a semiconductor substrate (11) comprising at least one transistor cell (12), the transistor cell (12) comprising an elongated trench (13) and an elongated mesa (14), the elongated trench (13) being arranged in a first main surface (15) of the semiconductor substrate (11) and comprising an elongated gate electrode (16) electrically separated from the semiconductor substrate (11) by a gate dielectric (17); a first insulating layer (23) disposed on the first main surface (15) and covering the elongated trench (13); an elongated contact connecting strip (24) arranged on the first insulating layer (23) and extending over and parallel to the elongated trench (13), the elongated contact connecting strip (24) being electrically connected to the elongated gate electrode (16) in the elongated trench (13) by at least one first contact (25) extending through the first insulating layer (23); and a source metal layer (26) electrically connected to the mesa (14), the source metal layer (26) extending at least partially over and being electrically insulated from the elongated contact connection strip (24), the at least one first contact (25) being located vertically below the source metal layer (26). [2] A transistor device according to claim 1, wherein a plurality of first contacts (25) are provided spaced along the length of the elongated trench (13). [3] Transistor device according to one of claims 1 to 2, wherein the at least one first contact (25) has a collective length L c and the elongated trench (13) has a length L t where 0.1L t ≤ L c ≤ 0.9L t . [4] The transistor device of claim 1, further comprising: a second insulating layer (28) disposed on the elongated contact connecting strip (24) and on the first insulating layer (23); an elongated mesa contact (30); wherein the source metal layer (26) is disposed on the second insulating layer (28) and the elongated mesa contact (30) extends from the source metal layer (26) through the first and second insulating layers (23, 28) and into the mesa (14). [5] A transistor device according to any one of claims 1 to 3, further comprising a gate metal layer (27) disposed on the second insulating layer (28) and laterally adjacent and spaced from the source metal layer (26), the gate metal layer (27) being electrically connected to the elongated contact interconnect strip (24) by a second contact (38, 39) extending through the second insulating layer (28) and between the gate metal layer (27) and the contact interconnect strip (24). [6] A transistor device according to any one of claims 1 to 4, wherein the elongated trench (13) further comprises a field plate (19) disposed in a lower portion of the trench (13) and electrically separated from the semiconductor substrate (11) and from the elongated gate electrode (16) by a field dielectric (20). [7] A transistor device according to any one of claims 1 to 5, wherein an upper surface of the gate electrode (16) is covered by an upper portion of the gate dielectric (22) and the first insulating layer (23) is disposed on the upper portion of the gate dielectric (22). [8] A transistor device according to any one of claims 1 to 6, wherein the gate electrode (16) is formed of polysilicon, the first contact (25) comprises tungsten, and the contact connection strip (24) comprises tungsten. [9] A transistor device according to any one of claims 1 to 8, wherein the elongated mesa contact (30) comprises tungsten and the source metal layer (26) comprises aluminum. [10] The transistor device of any one of claims 1 to 9, wherein the elongated mesa (14) comprises a drift region (31) of a first conductivity type, a body region (32) of a second conductivity type opposite to the first conductivity, the body region (32) being arranged on the drift region (31), and a source region (33) of the first conductivity type formed on and / or in the body region (32), a drain region of the first conductivity type being arranged in or on a second main surface of the semiconductor substrate (11) opposite to the first main surface (15). [11] A method comprising: Forming a first insulating layer (23) on a first main surface (15) of a semiconductor substrate (11) comprising at least one transistor cell (12), wherein the transistor cell (12) comprises an elongated trench (13) and an elongated mesa (14), wherein the elongated trench (13) is arranged in the first main surface (15) of the semiconductor substrate (11) and comprises an elongated gate electrode (16) electrically separated from the semiconductor substrate (11) by a gate dielectric (17), wherein the first insulating layer (23) covers the elongated trench (13), Forming at least one first contact (25) in the first insulating layer (23) connected to the elongated gate electrode (16) in the elongated trench (13); Forming an elongated contact connection strip (24) on the first insulating layer (23) which is electrically connected to the at least one first contact (25), wherein the contact connection strip (24) extends vertically above and parallel to the gate trench (13), Forming a second insulating layer (28) on the elongated contact connection strip (24), Forming a source metal layer (26) on the second insulating layer (28); electrically connecting the source metal layer (28) to the mesa (14), wherein the source metal layer (26) extends at least partially over the contact connection strip (24) and is electrically insulated therefrom by the second insulating layer (28), wherein the at least one first contact (25) is located vertically below the source metal layer (26). [12] The method of claim 11, further comprising: Forming at least one first opening (40) in the first insulating layer (23) exposing the gate electrode (16) and at least one elongated second opening (41) in the first insulating layer (23) extending into the mesa (14); Forming a first metal layer (43) in the first and second openings (40, 41) and on the first insulating layer (23), and Structuring the first metal layer (43) to form the elongated contact connection strip (24) and the elongated mesa contact (30). [13] The method of claim 12, further comprising: wherein electrically connecting the source metal layer (26) to the mesa comprises: Forming an elongated third opening (45) in the second insulating layer (28) above the elongated mesa contact (30), and Forming the source metal layer (26) in the third opening (45) and over the second insulating layer (28).

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