TRANSISTOR DEVICE AND METHOD FOR FORMING A GATE ELECTRODE AND A FIELD PLATE IN A COLUMN-SHAPED TRENCH

Abstract

In one embodiment, a transistor device is provided comprising a semiconductor substrate with a first main surface, a columnar trench arranged in the first main surface, and a lower surface and side wall, the side wall extending from the lower surface to the first main surface. A gate electrode is positioned in the columnar trench and electrically insulated from the semiconductor substrate by a gate dielectric. A field plate is positioned in the columnar trench below the gate electrode and electrically insulated from the gate electrode and from the semiconductor substrate by a field dielectric. The gate electrode is asymmetric about a longitudinal axis of the columnar trench. The field plate includes a field plate extension that extends from the field plate to the first main surface and laterally adjacent to the gate electrode.

Description

BACKGROUND

[0001] Transistor devices used in power electronics applications are often manufactured using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs).

[0002] A transistor device for power applications may be based on the charge compensation principle and may include an active cell array comprising a plurality of trenches, each comprising a field plate for charge compensation. In some embodiments, the trenches and the mesas formed between adjacent trenches each have an elongated stripe structure. In some other embodiments, the trenches and field plates each have a columnar, needle-like shape, as disclosed, for example, in DE 10 2014 112371 A1.

[0003] Further improvements would be desirable to further improve the performance of columnar field plate transistor devices, for example by reducing the on-resistance RDS(on).Area.

[0004] DE 10 2014 101 164 A1 discloses that a semiconductor part of a semiconductor device comprises a semiconductor layer with a drift zone of a first conductivity type and at least one impurity region of a second, opposite conductivity type. The impurity region adjoins a first surface of the semiconductor part in an element region. A connecting layer directly adjoins the semiconductor layer opposite the first surface. An overcompensation region is formed at a distance from the first surface in an edge region surrounding the element region.

[0005] DE 10 2005 052 734 A1 discloses a semiconductor structure having a first main surface and a second main surface. A gate electrode region, a channel region in which a vertically conductive channel can be created, and gate electrode insulation between the gate electrode region and the channel region are provided in a substrate. A field electrode region has an extension in any direction parallel to the first main surface that is less than a maximum extension in a direction perpendicular to the first main surface; and an electrically insulating layer arranged between the field electrode region and the drain region.

[0006] DE 10 2016 106 346 A1 discloses a field plate trench semiconductor device with a planar gate.

[0007] DE 2014 117 558 A1 discloses a semiconductor component with semiconductor fins. The semiconductor component further comprises gate electrode structures on two opposite sides of the respective channel / body region, as well as a field electrode structure between adjacent semiconductor fins, separated from the drift zone by a field dielectric and extending from the main surface to the base plane. The gate electrode structures associated with the adjacent semiconductor fins enclose an upper portion of the field electrode structure on two sides.

[0008] US 2013 / 0 334 565 A1 discloses a method for manufacturing a semiconductor device with an impurity source containing a metallic recombination element and semiconductor device. SUMMARY

[0009] In one embodiment, a transistor device is provided comprising a semiconductor substrate having a first main surface, a columnar trench disposed in the first main surface and comprising a bottom surface, and a sidewall, wherein the sidewall extends from the bottom surface to the first main surface. A gate electrode is positioned in the columnar trench and electrically isolated from the semiconductor substrate by a gate dielectric. A field plate is positioned in the columnar trench below the gate electrode and electrically isolated from the gate electrode and from the semiconductor substrate by a field dielectric. The gate electrode is asymmetric about a longitudinal axis of the columnar trench. The field plate comprises a field plate extension extending from the field plate to the first main surface and laterally adjacent to the gate electrode.

[0010] In one embodiment, a method for forming a gate electrode and a field plate in a columnar trench is provided. The method comprises providing a semiconductor substrate having a first main surface and a columnar trench comprising a bottom surface and a sidewall extending from the bottom surface to the first main surface, wherein the sidewall and the bottom surface are lined with a field dielectric, and the columnar trench is filled with a first conductive material. The method further comprises partially removing the field dielectric, partially removing the first conductive material from the columnar trench, and forming a gate recess arranged asymmetrically in the columnar trench with respect to a longitudinal axis of the columnar trench.The method further includes forming a dielectric material on walls of the gate recess and inserting a second conductive material into the gate recess to form a gate electrode. The remaining first conductive material forms the field plate and extends to the first main surface at a location laterally adjacent to the gate electrode.

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. SHORT DESCRIPTION

[0012] The elements of the drawings are not necessarily to scale. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined, provided they are not mutually exclusive. Exemplary embodiments are illustrated in the drawings and are described in detail in the following description. Fig. 1 includes Fig. 1A to Fig. 1E and illustrates transistor devices according to various embodiments. Fig. 2 includes Fig. 2A to Fig. 2L and illustrates methods for forming a gate electrode and a field plate in a columnar trench. Fig. 3 includes Fig. 3A to Fig. 3K and illustrates methods for forming a gate electrode and a field plate in a columnar trench. Fig. 4A to Fig. 4H illustrate top views of metallization structures for transistor devices according to various embodiments. DETAILED DESCRIPTION

[0013] A number of exemplary embodiments are explained below. In this case, identical structural features are identified by identical or similar reference numerals in the figures. In the context of the present description, "lateral" or "lateral direction" should be understood to mean a direction or extent that is generally parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction that is generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.

[0014] As used in this specification, when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "to" another element, it may be directly on or extending directly onto the other element, or there may also be intervening elements. Conversely, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements.

[0015] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0016] As used herein, various device types and / or doped semiconductor regions may be identified as being n-type or p-type, but this is merely for convenience of description and is not intended to be limiting, and such identification may be replaced by the more general description of being of a "first conductivity type" or a "second, opposite conductivity type", where the first type may be either n-type or p-type and the second type may then be either p-type or n-type.

[0017] The figures illustrate relative doping concentrations by indicating “-” or “+” next to the doping type “n” or “p”. For example, “n - ” a doping concentration that is lower than the doping concentration of an “n” doping region, while an “n +"-doping region has a higher doping concentration than an "n"-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doping regions can have the same or different absolute doping concentrations.

[0018] In some embodiments, the transistor device is a vertical transistor device having a vertical drift path extending perpendicular to two opposing major surfaces of the semiconductor substrate. The vertical transistor device may be a metal oxide semiconductor field-effect transistor (MOSFET) device, an insulated gate bipolar transistor (IGBT), or a bipolar transistor (BJT).

[0019] The electrodes or terminals of the transistor device are referred to herein as source, drain, and gate. As used herein, these terms also include the functionally equivalent terminals of other types of transistor devices, such as an insulated-gate bipolar transistor (IGBT). For example, the term "source," as used herein, includes not only a source of a MOSFET device, but also an emitter of an insulated-gate bipolar transistor (IGBT) device and an emitter of a bipolar junction bipolar transistor (BJT) device; the term "drain" includes not only a drain of a MOSFET device, but also a collector of an insulated-gate bipolar transistor (IGBT) device and a collector of a BJT device; and the term "gate" includes not only a gate of a MOSFET device, but also a gate of an insulated-gate bipolar transistor (IGBT) device and a base of a BJT device.

[0020] The present disclosure provides a transistor design concept for columnar (such as columnar) trench power transistors, e.g., power MOSFETs. In this design concept, it is proposed to integrate the gate and the field plate in the same columnar trench. This design may be used in combination with a stepped field dielectric, i.e., a field dielectric having a greater thickness in a lower portion of the columnar trench than in an upper portion of the columnar trench. This may, for example, allow the pitch of the columnar (columnar) trenches to be reduced in some embodiments.

[0021] Reducing the pitch in a conventional columnar trench MOSFET design is challenging because the gate electrode and field plate are arranged in separate trenches, with the gate trench positioned in the mesa formed between the columnar trenches where the field plates are located. Therefore, the minimum pitch between the columnar trenches is influenced by the integration scheme and process variations used to maintain a minimum distance between the gate trench and the source mesa contact.

[0022] According to the present disclosure, a power transistor device, e.g., a MOSFET, is provided with columnar trenches in which the gate electrode and the field plate are located within the same columnar trench. The gate and the field plate are electrically isolated from each other, which may reduce the gate-drain charge in some embodiments. The gate and field plate electrodes within the same trench are separately contacted at the die surface, i.e., at the upper open end of the columnar trench, with gate and source potentials, respectively.

[0023] In one embodiment, the power transistor device with columnar trenches having the gate and field plate electrodes within the same trench also includes a stepped field dielectric in which the field dielectric has a greater thickness in a lower portion of the sidewall of the columnar trench than in an upper portion of the sidewall of the columnar trench. The field plate has a smaller thickness in the lower portion and a greater thickness in the upper portion of the columnar trench.

[0024] A single transistor device may comprise multiple columnar trenches arranged in a regular array. Various arrangements of the columnar trenches are possible, such as an orthogonal layout and a hexagonal layout. The columnar trenches may have any lateral shape, for example, circular. Any polygon with a number of sides n greater than or equal to 3 may be used for the columnar shape. Irregular polygons and elongated shapes are also possible.

[0025] The gate and field plate electrodes are both accessible at the top of the columnar trench and can be reached through their respective contacts. The use of a graded field dielectric, e.g., a field oxide, may enable an increased area at the surface of the substrate available for forming contacts to the gate and field plate electrodes located next to each other. In some embodiments, providing a columnar trench comprising gate and field plate electrodes within the same trench may enable pitch shrinkage and lower RDSonA. In the same or different embodiments, isolating the gate and field plate electrodes with a dielectric material may reduce gate-drain charge. Lower RDSonA may be provided by using a graded field oxide. A trade-off between RDSon and gate charge Qg may be achieved through layout, e.g.,by modifying the gate and contact masks.

[0026] Since the field plate reaches the top of the columnar trench and is located adjacent to the gate, which also reaches the top of the columnar trench, the entire perimeter of the columnar trench is unavailable for channel formation. The channel of the transistor device can only be formed adjacent to the gate. Since the gate is not located adjacent to the entire sidewall, i.e., it does not extend 360° adjacent to the sidewall of the trench, the size of the channel is reduced accordingly due to the field plate contact coming to the surface of the substrate. In other words, the channel is not formed in the regions along the perimeter of the columnar trench where the field plate electrode reaches the substrate surface and is located adjacent to the perimeter of the columnar trench and adjacent to the source and body regions.The percentage of the available channel formed at each columnar trench can be tuned by appropriate layout, for example, by adjusting the gate mask. The percentage of the columnar trench perimeter used to form the channel can range from 15% to 85% of the total columnar trench perimeter. Increasing the channel percentage improves Rdson at the expense of gate charge. Fine-tuning the Rdson-Qg trade-off can be achieved by designing the gate layout. For example, a 50% channel percentage layout (1 / 2 gate) with orthogonal and hexagonal columnar trench arrangement or a 75% channel percentage layout (3 / 4 gate) with orthogonal and hexagonal columnar trench arrangement can be used.

[0027] The integration scheme for the gate and field plate in a single columnar trench is compatible with columnar trench technologies that incorporate a polysilicon or metal gate. The gate / source contact and tungsten line isolation are compatible with columnar trench and BEOL technologies. Potential modulation of the output resistor Ross (to integrate snubber functionality to reduce oscillations during switching) is provided by varying the thickness of the oxide in the upper section of the field plate in combination with the polyresistor. The source contact layout can be optimized for device performance (Ron, Vth, DIBL, parasitic turn-on, etc.). Various contact arrangements and configurations are also possible.

[0028] In some embodiments, the gate charge of the proposed device can exhibit a 50% lower Qgd compared to a columnar trench gate device while maintaining a similar RonA. The device exhibits a better Ron*Qgd figure of merit (FOM) despite a thinner gate oxide, making this concept attractive for fast switching applications where low FOMs are required.

[0029] As a result of the ability to reduce the spacing between the columnar trenches, a low-voltage columnar trench MOSFET can be provided. The transistor device according to the present disclosure can enable low Rdson and low Qg(d) for low-voltage columnar trench MOSFETs, where low voltage refers to breakdown voltage (BV) <= 40 V. The transistor device according to the present disclosure can also be used in higher voltage classes (BV >= 40 V), for example, for FOM (Figure of Merit)-optimized products with low gate charge.

[0030] Fig. 1 includes Fig. 1A to Fig. 1E and illustrates transistor devices 10 according to various embodiments. Fig. 1A illustrates a cross-sectional view and Fig. 1B is a top view of a transistor device 10 according to an embodiment, Fig. Figure 1C illustrates a cross-sectional view and Fig. 1D is a plan view of a transistor device 10 according to another embodiment, and Fig. 1E illustrates a cross-sectional view of a transistor device 10 according to yet another embodiment.

[0031] The transistor device 10, which in Fig. 1A to Fig. 1E and described with reference thereto, comprises a semiconductor substrate 11 having a first main surface 12 and at least one columnar trench 13 disposed in the first main surface 12. The columnar trench 13 includes a bottom surface 14, which may also be referred to as the bottom, and a sidewall 15 extending from the bottom surface 14 to the first main surface 12.

[0032] A columnar trench 13 may also be referred to as a needle-shaped trench and has a small or narrow perimeter or width relative to its height / depth in the substrate 11 perpendicular to the first main surface 12, in contrast to an elongated strip trench, which has a length in a plane parallel to the first main surface 12 that is greater than its depth in the substrate 11. Using the Cartesian coordinate system, the first main surface 12 can be considered to lie in the xy plane and the height / depth in the z direction.

[0033] The columnar (needle) trench 13 can have various shapes in plan view, for example, octagonal, circular, square, hexagonal, and other shapes in plan view. A columnar trench 13 that is circular in plan view has a single continuous sidewall 15. A columnar trench 13 that is square in plan view has a sidewall 15 with four subsections, with adjacent subsections arranged perpendicular to each other; a columnar trench 13 that is hexagonal in plan view has a sidewall with six subsections, and so on.

[0034] The transistor device 10 may include a plurality of columnar trenches 13, which may be arranged in a regular array with substantially the same uniform spacing, e.g., a square grid array of rows and columns. Alternatively, a plurality of columnar trenches 13 may be, for example, an array of staggered rows or a hexagonal array. A mesa 28 is formed by the region of the substrate 11 laterally surrounding the columnar trench 13, e.g., disposed between adjacent ones of the plurality of columnar trenches 13. Each columnar trench 13, with its gate electrode 16 and field plate 18, may form part of a transistor cell 24 of the transistor device. Typically, the transistor device 10 includes a plurality of transistor cells 24 electrically coupled in parallel to switch a load.

[0035] The transistor device 10 further includes a gate electrode 16 positioned in the columnar trench 13 and electrically insulated from the semiconductor substrate 11 by a gate dielectric 17 located on the sidewall 15 of the columnar trench 13. The transistor device 10 further includes a field plate 18, which may also be referred to as a field electrode. The field plate 18 is also positioned in the columnar trench 13. The field plate 18 is located in the columnar trench 13 below the gate electrode 16. The field plate 18 is electrically insulated from the gate electrode 16 and from the semiconductor substrate 11 by a field dielectric 19. The gate electrode 16 is asymmetric about a longitudinal axis 20 of the columnar trench 13.

[0036] The gate electrode 16 can be arranged asymmetrically in the columnar trench 13 with respect to the longitudinal axis 20 of the columnar trench 13. Asymmetrically arranged refers to a non-symmetrical arrangement of the gate electrode 16 in the columnar trench 13 with respect to the longitudinal axis 20 of this columnar trench in at least one plane that is parallel to the first main surface 12 and perpendicular to the longitudinal axis 10. In this at least one plane, the remainder of the columnar trench 13 is not occupied by the gate electrode 16. Since the gate electrode in the columnar trench 13 is arranged asymmetrically with respect to the longitudinal axis 20 of the columnar trench 13, the columnar trench 13 has only a simple rotational symmetry about the longitudinal axis 20 and no other n-fold rotational symmetry, where n is a natural number.For example, the gate electrode 16 may be located only in a single quadrant of a circular (cylindrical) columnar trench 13. In another example, the gate electrode may be located only in two or three adjacent quadrants of a circular columnar trench 13. The gate electrode 16 is provided by a single electrically conductive element disposed in the columnar trench 13. This single electrically conductive element is located in the columnar trench 13 asymmetrically with respect to the longitudinal axis 20.

[0037] The field plate 18 comprises a field plate extension 21 that extends from the field plate 18, which is located below the gate electrode 16, to the first main surface 12. The field plate extension 21 extends laterally adjacent to the gate electrode 16, where laterally denotes the xy plane. Thus, the field plate extension 21 and the gate electrode 16 are positioned within a single columnar trench 13 and are located at or below the plane of the first main surface 12. This makes it possible to establish electrical contact with the gate electrode 16 and the field plate extension 21, which enables electrical connection to the field plate 18, which is located in the bottom of the columnar trench 13, at the first main surface 13. The first contact 22 and the second contact 23 of a columnar trench 13 are arranged laterally adjacent to one another and can be arranged on opposite sides of the columnar trench 13, e.g.on opposite sides of the longitudinal axis 20.

[0038] In some embodiments, a first contact 22 with the gate electrode 16 and a second contact 23 with the field plate extension 21 and consequently with the field plate 18 located below the gate electrode 16 may be positioned within the region of the columnar trench 13, as defined by the circumferential sidewall 15 at the first main surface 12. The first and second contacts 22, 23 of the columnar trench 13 may be aligned in the x-direction.

[0039] The semiconductor substrate 11 may be formed from a Group IV semiconductor, such as silicon, and may be formed from a monocrystalline epitaxial layer or a single crystal, e.g., a monocrystalline silicon epitaxial layer or a silicon single crystal. The gate electrode 16 and the field plate 18, including its field plate extension 21, may comprise electrically conductive material, such as polysilicon. The gate dielectric 17 and the field dielectric 19 may be formed from an oxide, such as silicon oxide.

[0040] The semiconductor substrate 11 may be doped with a first conductivity type, for example, n-type, and provide the drift region 25 of the transistor device. A body region 26 comprising a second conductivity type opposite to the first conductivity type, e.g., p-type if the first conductivity type is n-type, is formed on the drift region 25, and a source region 27 comprising the first conductivity type is arranged on and / or in the body region 26. A drain region 29 formed of the first conductivity type is formed on the opposite second surface 30 of the semiconductor substrate 11, such that a vertical drift path is formed between the opposite first and second surfaces 12, 30. The source region 27 and the drain region 29 are more highly doped than the drift region 25.

[0041] In some embodiments, the field plate 18 is electrically connected to source potential. In some embodiments, the columnar trench 13 has a maximum area at in a plane parallel to the first main surface 12, and the gate electrode 16 is sized and shaped to have a maximum area a g in the plane parallel to the first principal surface and such that 10% ≤ (a g / a t ) *100 ≤ 90 % or 20 % ≤ (a g / a t ) *100 ≤ 80 %, 25 % ≤ (a g / a t ) *100 ≤ 75 %. In some embodiments, the field plate extension is sized and shaped to provide a maximum area a e in the plane parallel to the first principal surface and such that 10% ≤ (a e / a t ) *100 ≤ 90 % or 20 % ≤ (a e / a t ) *100 ≤ 80 %, 25 % ≤ (a e / a t) *100 ≤ 75%. In some embodiments, a ratio of a e / a g within the range of 1 / 9 to 9 / 1.

[0042] In some embodiments, the columnar trench 13 has a circumference (perimeter) At in a plane parallel to the first main surface 12, and the gate electrode 16 is sized and shaped to have a maximum circumferential length (perimeter length) A g in the plane parallel to the first principal surface and such that 10% ≤ (A g / A t ) *100 ≤ 90 % or 20 % ≤ (A g / A t ) *100 ≤ 80 %, 25 % ≤ (A g / A t ) *100 ≤ 75 %. In some embodiments, the field plate extension is sized and shaped to have a maximum circumferential length A e in the plane parallel to the first principal surface and such that 10% ≤ (A e / A t ) *100 ≤ 90 % or 20 % ≤ (A e / At ) *100 ≤ 80 %, 25 % ≤ (A e / A t ) *100 ≤ 75%. In some embodiments, a ratio of A e / A g within the range of 1 / 9 to 9 / 1.

[0043] By arranging the gate electrode 16 in the same trench as the field plate 18, the space within the mesa 28 is not occupied by a separate trench for the gate electrode. This makes it possible to reduce the pitch of the columnar trench array 13, i.e., the center-to-center pitch, and the width of the mesa 28, which can reduce RDS(on).Area.

[0044] The gate electrode 16 and the field plate 18 including its field plate extension 21, which are located in a columnar trench 13, can be electrically isolated from each other using various arrangements of electrically insulating material and / or dielectric material, which together provide the field dielectric.

[0045] Fig. Figure 1A illustrates a cross-sectional view along the Fig. Line AA shown in Figure 1B.

[0046] In some embodiments, the field dielectric 19 on the sidewall 15 of the columnar trench has two or more different thicknesses. With reference to the Fig. 1A and Fig. 1B, the field dielectric 19 has a first thickness t1 at a first distance from the bottom surface 14 that is less than a second thickness t2 of the field dielectric 19 at a second distance from the bottom surface 14, and a third thickness t3 at a third distance from the bottom surface 14, the first distance being greater than the second distance, which in turn is greater than the third distance. A first perimeter of the columnar field plate 18 at the first distance is greater than a second perimeter of the columnar field plate 18 at the second distance, and the second perimeter is greater than a third perimeter of the field plate 18 at the third distance. The first distance may lie in a plane intersecting the field plate extension 21.

[0047] In some embodiments, the side surface of the field plate 18 comprises a step such that an upper portion of the field plate has a width that is greater than a width of a lower portion of the field plate, and such that the field dielectric 19 has the second thickness t2 in a first region of the sidewall 15 of the columnar trench 13 and a third thickness t3 in a second region of the sidewall of the columnar trench, where t2 ≤ 1.15 t3 or t2 ≤ 1.2 t3 or t1 ≤ 1.5 t3. In some embodiments, t1 > t2. In some embodiments, t2 > t3. The difference between t2 and t3 is greater than that resulting from process variations.

[0048] In some embodiments, the side surface of the field plate 18 comprises a step at the transition to the field plate extension 21, such that the field dielectric 19 has a first thickness t1 in a first region of the sidewall 15 of the columnar trench 13 adjacent to the field plate extension 21 and the second thickness t2 in the second region of the sidewall 15 of the columnar trench 13 adjacent to the upper portion of the field plate 18, where t1 ≤ 1.15 t2 or t1 ≤ 1.2 t2 or t1 ≤ 1.5 t2.

[0049] With reference to the Fig. 1A and Fig. 1B, in some embodiments, an electrically insulating interlayer 36 is arranged centrally along the longitudinal axis 20 of the columnar trench 13. For example, the electrically insulating interlayer 36 may be cylindrical if the columnar trench 13 is substantially cylindrical, i.e., circular in plan view. The electrically insulating interlayer 36 extends vertically from the first main surface 12 into the trench 13 along the longitudinal axis 20 and is located centrally within the columnar trench 13 and extends into the columnar trench 13 from the first main surface 12 by a distance that is greater than the height of the gate electrode 16, i.e., greater than the distance of the base (bottom surface) of the gate electrode 16 from the first main surface 12.The electrically insulating intermediate layer 36 has a rod-like shape and is located between an inner side wall of the gate electrode 16 and the field plate extension 21, which is positioned laterally next to the gate electrode 16.

[0050] The gate electrode 16 is located in a gate recess 37, which is located in the columnar trench 13 adjacent to a portion of the sidewall 15 and between the sidewall 15 and the electrically insulating interlayer 36. The electrically insulating interlayer 36 extends from the first main surface 12 beyond the base of the gate electrode 16 and the bottom of the gate recess 37, such that the upper region of the field plate 18, which is arranged below the gate recess 37, has a ring shape. The lower region of the field plate 18 is located below the electrically insulating interlayer 36, and the ring-shaped upper portion fills the remaining area of ​​the columnar trench 13 that is not occupied by the field dielectric 19 at the sidewall 15 and bottom surface 14 of the columnar trench 13.

[0051] The gate recess 37 is located in the columnar trench 37 asymmetrically with respect to the longitudinal axis 20. The gate recess 37 is delimited on its outer sidewall by the gate dielectric 17, which is arranged on the upper portion of the sidewall 15 of the columnar trench 13, on its inner sidewall by the central electrically insulating interlayer 36, on its lower surface by a lateral electrically insulating layer 38, and on its two further sidewalls by a vertical electrically insulating layer 39. The gate recess 37 is therefore electrically separated from the field plate 18, which is located below the gate recess 37, by the lateral electrically insulating layer 38, and from the field plate extension 21, which is located laterally adjacent to the inner sidewall of the gate recess 37, by the central electrically insulating interlayer 36 and the vertical electrically insulating layers 39.The gate electrode 16 is therefore electrically separated from the semiconductor substrate 11 by the gate dielectric 17 and from the field plate 18 and the field plate extension 21 by the electrically insulating intermediate layer 36 and the additional electrically insulating layers 38, 39.

[0052] In some embodiments, the gate recess 37 and consequently the gate electrode 16 have the shape of an arc. An arc can also be described as an open ring shape with a gap located between two distal ends of the open ring shape. The field plate extension 21 is located in the gap of the gate electrode 16. The second contact 23 to the field plate 18 is also located in this gap and is positioned laterally adjacent to and separate from the gate electrode 16 in the columnar trench 13. The field plate extension 21 can also have an arc or open ring shape.

[0053] In some embodiments, the field plate 18 is electrically connected to source potential. This electrical connection can be provided by various arrangements.

[0054] The area of ​​the second contact 23 may be smaller than the area of ​​the gate electrode 16. The first contact 22 may be in direct physical contact with the gate electrode 16 such that the base (bottom surface) of the first contact 22 is positioned below the first main surface 12. The area of ​​the second contact 23 may be smaller than the area of ​​the field plate extension 21 at the first main surface 12. The second contact 23 may also extend into and be in physical contact with the field plate extension 21 and have a base (bottom surface) positioned below the first main surface 12.

[0055] In some embodiments, such as the Fig. 1A and Fig. 1B, the transistor device 10 includes a third contact 31 for each of the columnar trenches 13, extending into the source region 27 and body region 26 located in the mesa 28 formed between adjacent ones of the columnar trenches 13. The third contact 31 may be arranged laterally adjacent to the second contact 23 to the field plate 18, for example, aligned in the x-direction. The third contact 31 may be electrically connected to the second contact 23 to electrically connect the field plate 18 to source potential. In some embodiments, the third contact 31 may be electrically connected to the second contact 23 by a conductive line 32 arranged on the first main surface 12 of the semiconductor substrate 11.

[0056] As in Fig. 1A, the transistor device 10 may comprise a metallization layer 33 on the first main surface, which may comprise one or more dielectric layers 34 positioned directly on the first main surface 12 and through which the contacts 22, 23, 31 extend. The metallization layer 33 may comprise a first electrically conductive redistribution structure 34 extending between and electrically connecting the first contacts 22, one of which is located in each of the columnar trenches 13 of the regular array, and gate electrodes 16, and the second electrically conductive structure 32 electrically connecting the second contacts 23 and the third contacts 31 to each other and consequently the field plates 18 to the source region 27 and source potential.

[0057] The first contact 22 and the second contact 23 associated with a particular columnar trench 13 may be arranged on opposite sides of the columnar trench 13, for example, on opposite sides of the longitudinal axis 20, as shown in the plan view of Fig. 1B. This reflects the asymmetrical arrangement of the gate electrode 16 within the area of ​​the columnar trench 13. In this embodiment, the gate electrode 16 and the field plate extension 21 have an open ring shape having distal ends. The gate electrode 16 and the field plate extension 21 can be considered to have an arc portion of a cylindrical shape. The vertical electrically insulating layer 39 is arranged between the respective distal ends of the open ring shapes of the gate electrode 16 and the field plate 18 to electrically isolate the gate electrode 16 and the field plate 18 from each other. The gate electrode 16 and the field plate 18 each have an outer perimeter having a length slightly less than half the perimeter or inner perimeter of the sidewall 15 of the columnar trench 13.The open ring shape of the gate electrode 16 and the field plate extension 21 together laterally surround the electrically insulating interlayer 36, which has the shape of a substantially cylindrical element. In some embodiments, the second contact 23 to the field plate 18 and / or the first contact 22 to the gate electrode 16 are also in physical contact with the electrically insulating interlayer 36.

[0058] The field plate 18 is located below the gate electrode 16 and is connected to the field plate extension 21. The upper portion of the field plate 18 comprises an annular structure and is located between the central electrically insulating interlayer 36 and the field dielectric 19 positioned on the sidewall 15 of the columnar trench 13. The lower portion of the field plate 18 is located below the electrically insulating interlayer 36 and fills the area of ​​the columnar trench 13 delimited by the field dielectric 19 lining the bottom surface 14 and sidewall 15 of the columnar trench 13. The lower portion of the field plate 18 may have a cylindrical shape, for example, if the columnar trench has a substantially cylindrical shape. The lateral electrically insulating interlayer 38 may also be arranged between the bottom surface of the gate electrode 16 and the field plate 18.

[0059] Because the field plate extension 21 reaches the top of the columnar trench 13 and is located adjacent to the gate electrode 16, which also reaches the top of the columnar trench 13, the channel of the transistor device 10 is not formed in the regions along the perimeter of the columnar trench 12 where the field plate 18 reaches the first main surface 12. The percentage of the trench perimeter used to form the channel can range from 15% to 85% of the total columnar trench perimeter. Increasing the channel percentage improves the Rdson at the expense of gate charge. Fine-tuning the Rdson-Qg tradeoff can be achieved by designing the gate electrode 16. For example, a 50% channel percentage layout (1 / 2 gate) with orthogonal and hexagonal columnar trench arrangement or a 75% channel percentage layout (3 / 4 gate) can be used.

[0060] Fig. 1C and Fig. 1D illustrate a cross-sectional view along the Fig. 1D and a plan view of a transistor device 10 according to another embodiment. The transistor device of Fig. 1C and Fig. 1D differs from the one in Fig. 1A and Fig. 1B, the second contact 23 is sized, shaped, and arranged to be in direct contact with the field plate extension 21 and with the body region 26 and source region 27 formed in the mesa 28. The second contact 23 can be viewed as extending through the sidewall 15 of the columnar trench 13 such that its base (bottom surface) is positioned within the field plate extension 21 on the field dielectric 19 and also in contact with the body region 26. Therefore, the single contact 22 electrically connects the field plate extension 21 and the field plate 18 to the body region 26 and the source region 27, thus electrically coupling the field plate 18 to the source potential.

[0061] In the transistor device 10 of the Fig. 1A and Fig. 1B, the electrical connection of the field plate 18 to the source potential is provided by means of the second metallization structure 32 positioned on the dielectric layer 34 located on the first main surface 12 and extending between the separated second and third contacts 23, 31. The second metallization structure 32 may be formed from the same deposited layer as the contacts 23, 31 by patterning a portion of the deposited layer located on the dielectric layer 34 to form a conductive path. The transistor device 10 of the embodiment shown in Fig. 1C and Fig. 1D differs from the embodiment shown in Fig. 1A and Fig. 1B in that the single second contact 23 electrically connects the field plate 18 to the source region and is in direct contact with both the source region 27 and the field plate 18. The further features of the transistor device 10 of the embodiment illustrated in Fig. 1C and Fig. 1D may be the same as those in Fig. 1A and Fig. 1B illustrated transistor device.

[0062] Fig. 1E illustrates a transistor device 10 according to an embodiment that differs from that shown in Fig. 1A to Fig. 1D in the size, shape and arrangement of the electrically insulating interlayer 36 located between the field plate extension 21 and the gate electrode 16 in the upper portion of the columnar trench 13. The further features of the transistor device 10 of the Fig. 1E illustrated embodiment may be the same as that of the embodiment shown in Fig. 1A and Fig. 1B illustrated transistor device.

[0063] In the transistor device 10 of the Fig. 1E, the electrically insulating interlayer 36 extends into the columnar trench 13 from the first main surface 12 by a distance such that its end is positioned between the lower surface of the gate electrode 16 and the field plate 18 and is aligned with the lateral electrically insulating layer 38 at the lower surface of the gate recess 37. The electrically insulating interlayer 36 forms the inner side surface of the gate recess 37 for the gate electrode 16, but, in contrast to the embodiments shown in Fig. 1A to Fig. 1D, the field plate 18 does not extend further into the conductive material of the field plate 18 and beyond the lateral electrically insulating layer 38 at the bottom of the gate recess 37. The field plate 18, which is arranged below the gate electrode 16, fills the entire area of ​​the columnar trench 13 that is not occupied by the field dielectric 19. The electrically insulating intermediate layer 36 can be arranged asymmetrically with respect to the longitudinal axis 20 of the columnar trench 13, for example, offset laterally from the longitudinal axis 20 in the direction of the gate electrode 16. The electrically insulating intermediate layer 36 can also form the further two side surfaces of the gate recess 37, so that the gate electrode 16 is electrically insulated within the gate recess 37 from the field plate 18 and its field plate extension 21, which is also located in the columnar trench 13.

[0064] In some embodiments, the field plate extension 21 may extend along the longitudinal axis 20, and the gate recess 37 is laterally offset from the longitudinal axis 20. The bottom of the gate recess 37 is formed by the lateral electrically insulating layer 38. The field plate 18 fills the area of ​​the columnar trench 13 below the lateral electrically insulating layer 38 and below the gate electrode 16 that is not occupied by the field dielectric 19.

[0065] In the transistor device 10 of Fig. 1E, the field dielectric 19 has two different thicknesses on the sidewall 15 of the columnar trench 13. A first thickness t1 of the field dielectric 19 at a first distance from the bottom surface 14 is smaller than a second thickness t2 of the field dielectric at a second distance from the bottom surface 14, wherein the first distance is greater than the second distance. The side surface of the field plate 18 includes a step such that the field dielectric 19 has a first thickness t1 in a first region of the sidewall 15 of the columnar trench 13 adjacent to the field plate extension 21 and laterally adjacent to the gate electrode 16, and a second thickness t2 in a second region of the sidewall 15 of the columnar trench 13 adjacent to the field plate 18 below the gate electrode 16, where t1 ≤ 1.15 t2 or t1 ≤ 1.2 t2 or t1 ≤ 1.5 t2. In some embodiments, t1 > t2. In some embodiments, t2 > t3.The difference between t1 and t2 is larger than that resulting from process variations.

[0066] Methods for fabricating a gate electrode and a field plate in a columnar trench will now be described with reference to Fig. 2 described, the Fig. 2A to Fig. 2L. The provisions of Fig. 2 can be used to form the columnar trench 13 and the Fig. 1A to Fig. 1D illustrated transistor device 10.

[0067] With reference to Fig. 2A, a semiconductor substrate 11 is provided having a first main surface 12 and at least one columnar trench 13. The semiconductor substrate 11 may comprise a plurality of columnar trenches 13 arranged in a regular array, for example, a square grid array or staggered rows, each having substantially the same structure. The plurality of columnar trenches 13 may be processed using the same process steps. The columnar trench 13 has a bottom surface 14, which may also be referred to as the bottom of the trench, and a sidewall 15 extending from the bottom surface 14 to the first main surface 12. The sidewall 15 and the lower surface 14 are lined with a field dielectric 19 and the rest of the columnar trench 13, ie the central region bounded by the field dielectric 19, is filled with a first conductive material 40.

[0068] The semiconductor substrate 11 may be formed from silicon, for example, a monocrystalline silicon epitaxial layer or a silicon single crystal. The body region 25 and the source region 27 may already have been formed, for example, by implanting suitable dopants into the first main surface 12. The first conductive material 40 may be selected to be suitable for forming a field plate. For example, the first conductive material 40 may be polysilicon. The field dielectric 19 may be formed from an oxide, for example, silicon oxide. The dielectric material 19 may also extend over the first main surface 12.

[0069] In one embodiment, the method is as described with reference to Fig. 2B. In an alternative embodiment, the method is continued as described with reference to Fig. 2C and Fig. Continued as described in 2D.

[0070] With reference to Fig. 2B, a portion of the first conductive material 40 is removed from the upper portion of the columnar trench 13, exposing the field dielectric 19 at the upper portion of the sidewall 15 of the columnar trench 13. The first conductive material 40 may preferably be removed over the material of the field dielectric 19, for example, by selective etching, e.g., wet etching. The selectivity of the conductive material 40 over the material of the field dielectric 19 to the etch may be about 100 to 1 (it could also be lower, such as about 50 to 1 in some examples). In some embodiments, a portion, e.g., a portion of the first conductive material 40 may also be removed in this process. B. a surface, of the exposed field dielectric 19 is removed (in other embodiments this may be done in a separate process), thereby reducing the thickness of the field dielectric 19 in the upper portion of the columnar trench 13 and also on the first main surface 12.The first main surface 12 and the upper portion of the sidewall 15 of the columnar trench 13 remain covered with a thinner layer of the field dielectric 19. The field dielectric 19 then has two different thicknesses on the sidewall 15: a first, larger thickness in the lower portion in contact with the remainder of the first conductive material 40, and a second, smaller thickness in the upper portion exposed from the conductive material 40. The method can be performed as described with reference to FIG. Fig. 2E to Fig. 2L described.

[0071] With reference to Fig. 2C, in the alternative embodiment, the first conductive material 40 is removed within the columnar trench 13, e.g., preferably removed over the material of the field dielectric 19, for example, by selective etching, e.g., wet etching, from an uppermost portion of the columnar trench 30 to a smaller depth than in the Fig. 2B. The field dielectric 19 is also exposed over a smaller depth in the upper and intermediate portions of the sidewall 15 of the columnar trench 13. The thickness of the exposed region of the field dielectric 19 can also be slightly reduced by this process.

[0072] With reference to Fig. 2D, a further removal process is performed to remove another portion of the first conductive material 40 and a portion of the field oxide 19 positioned on the sidewall 15 in the uppermost portion of the columnar trench 13 and on the sidewall 15 in the intermediate portion of the columnar trench 13. In this embodiment, the field dielectric 19 comprises three different thicknesses on the sidewall 15 of the trench. The thickness is greatest in the lower portion of the trench, where the field dielectric 19 is in contact with the remainder of the first conductive material 40. The field dielectric 19 has a second thickness, slightly less than the first thickness, in the intermediate portion uncovered during the second etch process, and a third thickness, less than the second thickness, in the uppermost portion of the trench 13, which is partially removed in both removal, e.g., etching, processes.This arrangement is in contrast to that in . Fig. 2B, in which the field dielectric has only two different thicknesses on the side wall 15. The alternative method is then carried out as described with reference to Fig. 2E to Fig. 2L described continued.

[0073] With reference to Fig. 2E, a second conductive material 41 is deposited, extending over the exposed field dielectric 19 at the first main surface 12 and on the sidewall 15 of the columnar trench 13. The second conductive material 41 may also cover the exposed upper surface of the first conductive material 40. The second conductive material 41 forms a conductive layer surrounding a gap 42 located centrally in the columnar trench 13 and extending along the longitudinal axis 20 of the columnar trench 13. The first and second electrically conductive materials 40, 41 may have the same or a similar composition, for example, polysilicon. This gap 42 is then filled with an electrically insulating material 43, for example, silicon oxide, forming a central electrically insulating interlayer 36.

[0074] With reference to Fig. 2F, a planarization process may be performed to remove the second conductive material 41 from the first main surface 12 and expose the remainder of the field dielectric layer 19 disposed on the first main surface 12. The process continues by forming the gate recess 37 and the gate electrode 16 in the upper portion of the columnar trench 13.

[0075] With reference to Fig. 2G, a mask 44 is formed on the first main surface 12, comprising openings 45 sized, shaped, and arranged to form a gate recess 37. The openings 45 are sized, shaped, and arranged to expose a portion of the central electrically insulating material 43 and a portion of the second conductive material 25 that is laterally asymmetric with respect to the longitudinal axis 20 of the columnar trench 13 and located within the columnar trench 13. For example, the opening 45 in the mask 44 may have an arcuate shape, which may also be described as an open ring shape with a gap between two distal ends of the open ring shape. The remainder of the second conductive material 41 within the columnar trench 13 and optionally also a portion of the electrically insulating layer material 43 is covered by the mask 44.The exposed portion of the second conductive layer 41 is removed to form a single gate recess 37 located in a portion of the surface of the columnar trench 13. The electrically insulating interlayer 36, in combination with the mask 44, acts as an etch stop and assists in at least partially self-aligning the position of the gate recess 37 within the columnar trench 13. The gate recess 37 is lined on its outer side surface by the field dielectric 19 located on the sidewall 15 of the trench 13 and on its inner side surface by the exposed portion of the electrically insulating interlayer 36. In this stage of the process, the lower surface of the gate recess 37 and the two further sidewall portions are formed by the exposed second conductive material 41.

[0076] With reference to Fig. 2H, the mask 44 is removed. The exposed area of ​​the field dielectric 19 is removed, and the upper portion of the sidewall 15 of the columnar trench 13 and the first main surface 12 are exposed. Referring to Fig. 2l, a further electrically insulating layer 17 is deposited or grown, for example, by thermal oxidation, covering the lower surface and sidewall portions of the gate recess 37, such that the gate recess 37 is lined with electrically insulating and / or dielectric material. The thickness of the electrically insulating layer 17 on the sidewall 15 of the columnar trench 13 is suitable for providing the gate dielectric 17 of the transistor device 10. The thickness of the electrically insulating layer 17 may be higher at the lower surface and other sidewall portions of the gate recess 37. If the gate dielectric is deposited, then the thickness of the gate dielectric may be the same at the lower surface and the sidewalls, i.e., portions 17, 38, and 39.If the gate dielectric is thermally grown, the regions on the bottom surface and the sidewall formed by polysilicon, i.e., sections 38, 39, may have a thickness greater than section 17 formed on the sidewall formed of silicon. For example, for thermally grown silicon oxide, the thickness of the thermally grown gate dielectric in sections 38, 39 may be 2 to 3 times greater than in section 17, since silicon oxide grows faster on polysilicon than silicon. Electrically conductive material 47, e.g., B. polysilicon, is then inserted into the gate recess 37 to form the gate electrode 16, which is electrically insulated by the electrically insulating material 17 from the second conductive material 41 in the columnar trench 13, which forms the field plate 18 and the field plate extension 21, and from the semiconductor substrate 11.

[0077] With reference to Fig. 2J, the process may be continued by depositing one or more dielectric layers 48 on the first main surface 12, covering the columnar trenches 13 and the gate electrode 16 and the field plate extension 21. Referring to Fig. 2K, for at least one of the columnar trenches 13, a first opening 49 may be formed in the dielectric layers 48, exposing the gate electrode 16, and a second opening 50 may be formed, exposing the second conductive material 41 in a position laterally adjacent to the gate electrode 16. In some embodiments, the second opening 50 also exposes a region of the mesa 28 formed adjacent to the sidewall 15 of the columnar trench 13. An etch process may then be performed to remove a portion of the material of the gate electrode 16 and the second conductive material 41 and, if exposed, an adjacent portion of the mesa 28, to form first and second contact openings 51, 52. This etch process may also be used to form third openings for the contacts 31 to the mesas 31.

[0078] With reference to Fig. 2L, electrically conductive material 53 can then be inserted into the first and second openings 51, 52 to form a first contact 22 to the gate electrode and a second contact 23 to the second conductive material 41. The second electrically conductive material 41 forms the field plate extension 21 and is electrically connected to the first conductive material 40 in the lower portion of the columnar trench 13, which forms the field plate 18 within the lower portion of the columnar trench 13. In a plane shown in Fig. 2, the electrically conductive material 53 is also inserted into third openings to form the contacts 31 to the mesas 28. The electrically conductive material 53 may be polysilicon or a metal and may comprise two or more sublayers of different compositions, e.g., different metals or alloys.

[0079] In some embodiments, a first lateral redistribution structure 56 may be formed extending between the first contacts 22 and electrically interconnecting the gate electrodes 16 within different columnar trenches 13. A second lateral redistribution structure 32 may be formed extending between the second contacts 23 and electrically interconnecting the field plates 18 and the body and source regions 26, 27.

[0080] The first and second lateral redistribution structures 56, 32 may be formed simultaneously with the insertion of the electrically conductive material 53 into the first and second openings 51, 52 and into the third openings for the mesa contacts 31. The electrically conductive material is further formed on the first main surface and is then patterned to form separate lateral redistribution structures 56, 32. The lateral redistribution structure 56 is used to electrically connect the first contacts 22 and gate electrodes 16. The second lateral redistribution structure 32 is used to electrically connect the second contacts 23 and the field plates 18 and the contacts 31 to the mesas 28.

[0081] A method of forming a gate electrode and a field plate in a columnar trench according to another embodiment will now be described with reference to Fig. 3 described, the Fig. 3A to Fig. 3K. The with reference to Fig. 3 can be used to form the columnar trench 13 and the Fig. 1E illustrated transistor device 10.

[0082] With reference to Fig. 3A, a semiconductor substrate 11 is provided having a first main surface 12 and at least one columnar trench 13, as described with reference to Fig. 2A. Each of the columnar trenches 13 has a bottom surface 14 and a sidewall 15 extending from the bottom surface 14 to the first main surface 12. The first main surface 12, the sidewall 15, and the bottom surface 14 of the columnar trenches 13 are covered with an electrically dielectric layer 19 surrounding a gap in the center of each of the columnar trenches 13. This gap is filled with a first conductive material 40 to form a field plate.

[0083] With reference to Fig. 3B, the first electrically conductive material 40 is removed from an upper portion of the columnar trench 13, exposing a portion of the field dielectric 19 located at the sidewall 15 of the columnar trench 13. The first electrically conductive material 40, e.g., polysilicon, is preferably removed over the material of the field dielectric 19, e.g., SiO2, for example, by selective etching.

[0084] With reference to Fig. 3C, a portion of the exposed field dielectric 19 is removed, reducing the thickness of the field dielectric 19 at the sidewall 14 of the upper portion of the columnar trench 13 and at the first main surface 12, such that the field dielectric 19 has a smaller thickness at the sidewall 15 in the upper portion of the columnar trench 13 and a larger thickness in the lower portion of the columnar trench 13. In this embodiment, the field dielectric 19 has two different thicknesses at the sidewall 15, a first larger thickness in the lower portion in contact with the remainder of the first conductive material 40, and a second smaller thickness in the upper portion exposed from the conductive material 40.

[0085] With reference to Fig. 3D, a second conductive material 41, e.g., polysilicon, is then inserted into the columnar trenches 13 to fill the trenches, thereby forming a structure for a field plate 18 having a larger width in the upper part of the columnar trench 13 and a smaller width in the lower part of the columnar trenches 13 and 13. One or more further dielectric materials 48 are then deposited on the first main surface 12, covering the columnar trench 13 and the second conductive material 41 within the columnar trench 13.

[0086] With reference to Fig. 3E, a gate recess 37 is formed in the upper portion of the columnar trench 13 by removing a portion of the second conductive material 41 to expose the field dielectric 19 of the sidewall 15 of the columnar trench 13 and to form the gate recess 37, which is bounded on its outer surface by the field dielectric 19 and on its inner sidewall and remaining sidewalls by the second conductive material 41. The gate recess 37 is laterally asymmetric with respect to the longitudinal axis 20 of the columnar trench.

[0087] The thickness of the exposed region of the field dielectric 19 on the uppermost portion 15 of the sidewall 15 of the columnar trench 30 can be further reduced, as shown in Fig. 3F, and can be completely removed. With reference to Fig. 3G, an electrically insulating layer 17 is then deposited into the gate recess 37, lining the bottom surface and sidewalls of the gate recess 37 including the sidewall 15 of the columnar trench 13, where it forms the gate dielectric 17 and the isolation regions 38 and 39 between the gate electrode 16 and the field plate electrode 18 of the transistor device 10 and the sidewalls of the gate recess 37 formed by the second conductive material 41.Alternatively, the electrically insulating layer 17 is grown, for example by thermal oxidation, on the lower surface and sidewalls of the gate recess 37 including the sidewall 15 of the columnar trench 13 to form the gate dielectric 17 and the isolation regions 38 and 39 located between the gate electrode 16 and the field plate electrode 18 of the transistor device 10 and between the gate electrode 16 and the sidewalls of the gate recess 37 formed by the second conductive material 41.

[0088] With reference to Fig. 3H, electrically conductive material 47 is then inserted into the dielectric-lined gate recess 37 to form the gate electrode 16. The gate electrode 16 is electrically insulated from the second conductive material 41 by the dielectric layer 17 that lines the sidewalls and bottom surface of the gate recess 37 and that also forms the gate dielectric 17 on the sidewall 15 of the columnar trench 13. The second conductive material 41 forms the field plate extension 21, which is located in the upper portion of the trench 13 and laterally adjacent to the level of the gate electrode 16 and substantially parallel to the gate dielectric 17. The second conductive material 41 also forms the upper portion of the field plate 18, which is partially located beneath the gate electrode 16.

[0089] With reference to Fig. 3l, a planarization process may be performed which exposes the first main surface 12, and then one or more dielectric layers 48 may be deposited on the planarized surface, which also cover the columnar trenches 13. Contacts to the gate electrode 16 and the field plate 18 may be made in a similar manner as described with reference to Fig. 2K and Fig. 2L illustrates how to form.

[0090] With reference to Fig. 3J, a first opening 51 is formed through the dielectric layer 48, exposing the gate electrode 16 and may extend into the gate electrode 16. A second opening 52 is formed, exposing the second conductive material 41 and may be sized and shaped to extend into the mesa 28 in the region adjacent to the sidewall 15 of the columnar trench 13. Referring to Fig. 3K, a conductive material 53 is inserted into the openings 51, 52 to form a first contact 22 to the gate electrode 16 and a second contact 23 to the field plate extension 21 and the mesa 28. A first contact 22 and a second contact 23 are formed in each of the columnar trenches 13. The first contacts 22 may be laterally connected to each other by a lateral redistribution structure 56 positioned on or in the dielectric layers 48, and the second contacts 23 may be electrically connected to each other by a second lateral redistribution structure 32 extending above the top surface of the dielectric layers 48. The first and second lateral redistribution structures 32, 56 may extend substantially parallel to each other and may be positioned on opposite sides of the columnar trenches 13.

[0091] Fig. 4, the Fig. 4A to Fig. 4H illustrates views of a metallization layer 60 according to various embodiments, which may be located on the first main surface 12 of the semiconductor substrate 11 of the transistor device 10.

[0092] Fig. 4A illustrates a top view and Fig. 4B is a cross-sectional view of a transistor device 10 including the metallization layer 60 according to one embodiment. The top view of Fig. Figure 4A shows a transistor device 10 which corresponds to the top view of Fig. 1C, and the cross-sectional view of Fig. Figure 4B shows the transistor device 10 corresponding to the cross-sectional view of Fig. 1D corresponds.

[0093] In this embodiment, the gate electrode 16 has an open ring shape with an outer circumference that corresponds to slightly less than 50% of the circumference of the sidewall 15 of the columnar trench 13. The field plate extension 21 also has an open ring structure and has an outer circumference that is slightly less than 50% of the inner circumference of the sidewall 15 of the columnar trench 13 due to the electrically insulating layer 39 arranged between the distal ends of the gate electrode 16 and the field plate extension 21. For each columnar trench 13, a first contact 22 to the gate electrode and a second contact 23 to the field plate 18 are provided.

[0094] The columnar trenches 13 are arranged in a square grid array, or rows and columns, such that the spacing between the columnar trenches 13 is substantially equal in two perpendicular directions, the x-direction and the y-direction using the Cartesian coordinate system. The columnar trenches 13 can be considered to be arranged in multiple columns, with each column extending in the y-direction. The first contacts 22, which are electrically connected to the respective gate electrodes 16 in the columnar trenches 13 of a column, are electrically connected to each other by a strip-like electrically conductive trace 61 of the metallization layer 60 extending in the y-direction. The conductive trace 61 is positioned on and electrically in contact with each of the first contacts 22 and is electrically insulated from the mesa 28 located between the columnar trenches 13.

[0095] In this embodiment, the second contact 23 is sized, shaped, and positioned to be in contact with the field plate 18 and with the mesa 28, and in particular with the body region 26 and source region 27 located in the mesa 28 adjacent to this columnar trench. Fourth contacts 62 are provided, with a fourth contact 61 positioned in the mesa 28 formed between adjacent ones of the columnar trenches 13. The fourth contacts 62 are electrically connected to the source region 27 and optionally also to the body region 26. The fourth contact 62 may have a depth into the semiconductor substrate 11 from the first main surface 12 to extend into the source region 27 and the body region 26. The fourth contacts 62 may be arranged in a column with the second contacts 23, wherein the column extends in the y-direction and substantially to the column of the first contacts 22 to the gate electrodes.The second and fourth contacts 23, 62 are electrically connected to each other by an electrically conductive metallization structure 63 in the first main surface 12. The electrically conductive metallization structure 63 may be strip-like and extend in the y-direction and parallel to and spaced from the conductive trace 61 connecting the gate electrodes 16. The conductive trace 63 is electrically connected to the field plates 18 of this column and the source and body regions 26, 27 in the mesa 28.

[0096] The metallization structure 60 comprises a further conductive trace 64 located on the dielectric layer on the first main surface 12 and electrically connected to the metallization structure 63 and the contacts 23, 62 located in the semiconductor substrate 11. A conductive trace 61 is located on the dielectric layer 34 on the first main surface 12 and electrically connects the first contacts 22 to the gate electrodes 16. The conductive trace 64 extends substantially parallel to the conductive trace 61. The conductive trace 64 may be wider than the conductive trace 61. Since the columnar trenches 13 are arranged in a plurality of columns extending substantially parallel to each other in the y-direction, two conductive traces 61, 64 are provided for each column of the columnar trenches 13, so that the traces 61, 64 are alternately connected to the gate and source potential.The tracks 61, 64 may be arranged in a layer of the metallization layer 60 that is integral and formed simultaneously with the conductive material forming the contacts 22, 23, 62 and the conductive connection 63.

[0097] Fig. 4C illustrates a top view and Fig. 4D shows a cross-sectional view of a transistor device 10 including a metallization layer, according to another embodiment. Fig. 4C and Fig. 4D is different from the transistor device 10 shown in the Fig. 4A and Fig. 4B, in the ratio between the area of ​​the gate electrode 16 and the area of ​​the field plate extension 21 at the first main surface 12 within a columnar trench 13 and in the ratio between the length of the perimeter of the gate electrode 16 and the length of the perimeter of the field plate 18 at the first main surface 12 within a columnar trench 13. In this embodiment, the gate electrode 16 has an open ring shape with an outer circumference that corresponds to slightly less than 75% of the circumference of the sidewall 15 of the columnar trench 13. The field plate extension 21 also has an open ring structure and has an outer circumference that is slightly less than 25% of the inner circumference of the sidewall 15 of the columnar trench 13 due to the electrically insulating layer 39 arranged between the respective distal ends of the gate electrode 16 and the field plate extension 21.The open ring shape of the gate electrode 16 and the open ring shape of the field plate extension 21, together with the electrically insulating layer 39, laterally surround the central rod-shaped electrically insulating intermediate layer 36 within the columnar trench 13.

[0098] The position of the second contact 23 to the field plate 18 differs from that in Fig. 4A in that it is no longer aligned in the x-direction with the first contact 22 to the gate electrode 16 of this columnar trench 13, but is offset in the y-direction. A fourth contact 62 is also provided, which is located in the mesa 28 between two adjacent columnar trenches 13 of a column of columnar trenches 13 extending in the y-direction. The second and fourth contacts 23, 62 are connected by the conductive connection 63 as in the Fig. 4A. The metallization layer 60 also includes a stripe-like conductive trace 64 located on the dielectric layer 34 on the first main surface 12. The conductive trace 64 is located on and electrically connected to the conductive connection 63 formed in the dielectric layer 34 and is electrically connected to the mesa 28 and the field plates 18. The conductive trace 64 extends in the y-direction substantially parallel to the conductive trace 61 located on the dielectric layer 34 and electrically connected to the gate contacts 22 of the columnar trenches 13 of a particular column. The conductive trace 64 may be integral with the conductive connection 63 and the contacts 23, 61, and the conductive trace 61 may be integral with the contacts 22. The conductive traces 61, 64 are essentially coplanar.

[0099] Fig. 4E illustrates a top view and Fig. 4F is a cross-sectional view of a metallization layer 60 and a transistor device 10 according to another embodiment different from that shown in Fig. 4A and Fig. 4B in that the columnar trenches 13 are arranged in columns that are offset from each other, ie, offset in the Y direction, so that the columnar trenches 13 have a hexagonal arrangement.

[0100] Each of the columnar trenches 16 has an open annular gate electrode 16 and an open annular field plate 18 which are substantially semicircular, as shown in Fig. 4A. Similar to Fig. 4A, each of the columnar trenches 13 is associated with a first contact 22 to the gate electrode 16 and a second contact 23 to the field plate 18 in the columnar trench 13. The second contact 23 extends into the adjacent region of the mesa 28 to electrically connect the field plate to the body region 26 and the source region 27. In this embodiment, the shape of the conductive trace 63 extending between the second contacts 23 differs from that in Fig. 4A. In this embodiment, the conductive trace 63 has a zigzag structure such that it is positioned substantially equidistant between the columnar trenches 13 within a column (in the y-direction) and between the columnar trenches 13 of that column and the adjacent column. The first contact 22 and the second contact 23 of a columnar trench 13 of one column are aligned in the x-direction, but offset in the y-direction from the first contact 22 and the second contact 23 of a columnar trench 13 of the adjacent column.

[0101] The metallization layer 60 further comprises a strip-shaped conductive trace 61 electrically connected to the plurality of first contacts ss and the gate electrodes 16 of the columnar trenches 13, and a conductive trace 64 extending substantially parallel to the conductive trace 61 and electrically connected to the second contacts 23 and therefore to the source region 26 and the field plate 18.

[0102] Fig. 4G illustrates a top view and Fig. 4H shows a cross-sectional view of a metallization layer 60 and a transistor device 10 according to another embodiment. In this embodiment, the columnar trenches 13 are formed as shown in the top view of Fig. 4E in staggered columns. Each columnar trench 13 comprises a gate electrode 16 and a field plate 18 with the ratio of the areas and the arrangement shown in Fig.4C. The gate electrode 16 has an open ring shape with an outer circumference slightly less than 75% of the circumference of the sidewall 15 of the columnar trench 13, and the field plate extension 21 also has an open ring structure and has an outer circumference slightly less than 25% of the inner circumference of the sidewall 15 of the columnar trench 13 due to the electrically insulating layer 39 disposed between the respective distal ends of the gate electrode 16 and the field plate extension 21.

[0103] In this embodiment, the second contact 23 to the field plate extension 21 is offset from the first contact 22 to the gate electrode 16 of a particular columnar trench 13. The conductive trace 63 extending between the second contacts 23 also has a zigzag or meander structure, such that it is substantially equidistant between adjacent columnar trenches 30 of one column and the columnar trenches 13 of the adjacent column of the array.

[0104] In summary, a power MOSFET with columnar trenches is provided, in which the gate electrode and the columnar field plate are located within the same columnar trench. The gate electrode and the columnar field plate are electrically isolated from each other to reduce the gate-drain charge. The gate electrode and the field plate within the same trench can be separately contacted with gate and source potentials, respectively, at the die surface, i.e., at the top of the columnar trench.

[0105] Pitch shrinkage and lower RDSonA can be achieved by locating the gate and field plate electrodes within the same trench. Low gate-drain charge is achieved by insulating the gate and field plate electrodes with a dielectric material. Lower RDSonA can be achieved by using a graded field oxide.

[0106] Due to the ability to reduce the spacing between the columnar trenches, a low-voltage columnar trench MOSFET can be provided. The transistor device according to the present disclosure can enable low Rdson and low Qg(d) for low-voltage columnar trench MOSFETs, where low voltage denotes BV ≤ 40 V. The transistor device according to the present disclosure can also be used in higher voltage classes (BV ≥ 40 V), for example, for FOM (figure of merit)-optimized products with very low gate charge.

[0107] Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the disclosure. Examples

[0108] Example 1. Transistor device comprising: a semiconductor substrate comprising a first main surface; a columnar trench disposed in the first major surface and comprising a bottom surface, a lower surface, and a sidewall, the sidewall extending from the bottom surface to the first major surface; a gate electrode positioned in the columnar trench and electrically insulated from the semiconductor substrate by a gate dielectric, a field plate positioned in the columnar trench below the gate electrode and electrically insulated from the gate electrode and the semiconductor substrate by a field dielectric, wherein the gate electrode is asymmetric about a longitudinal axis of the columnar trench, and wherein the field plate comprises a field plate extension extending from the field plate to the first main surface and laterally adjacent to the gate electrode.

[0109] Example 2. The transistor device of Example 1, further comprising: a first contact extending from the first main surface into the columnar trench, the first contact being electrically connected to the gate electrode, and a second contact extending from the first main surface into the columnar trench, the second contact being electrically connected to the field plate, wherein the first contact and the second contact are arranged laterally next to each other.

[0110] Example 3. The transistor device of Example 2, wherein the first contact and the second contact are located on opposite sides of the columnar trench.

[0111] Example 4. The transistor device of any one of Examples 1 to 3, wherein the field plate extension is electrically insulated laterally from the gate electrode by an intermediate dielectric.

[0112] Example 5. The transistor device of Example 4, wherein the intermediate dielectric is located centrally in the columnar trench and extends from the first main surface to the field plate.

[0113] Example 6. The transistor device of any one of Examples 1 to 5, wherein the field plate extension and the gate electrode each comprise an arc.

[0114] Example 7. The transistor device according to any one of examples 1 to 7, wherein the gate electrode is provided by a single electrically conductive portion having an open ring shape with a gap located between two distal ends of the open ring shape.

[0115] Example 8. The transistor device of Example 6, wherein the field plate extension is located in the gap of the gate electrode.

[0116] Example 9. The transistor device of any one of examples 1 to 8, wherein a first thickness of the field dielectric at a first distance from the bottom surface is less than a second thickness of the field dielectric at a second distance from the bottom surface, the first distance being greater than the second distance, and a first perimeter of the columnar field plate at the first distance being greater than a second perimeter of the columnar field plate at the second distance.

[0117] Example 10. The transistor device of example 9, wherein the side surface of the field plate comprises a step such that an upper portion of the field plate has a width that is greater than a width of a lower portion of the field plate, and such that the field dielectric has a first thickness t1 in a first region of the sidewall of the columnar trench and a second thickness t2 in a second region of the sidewall of the columnar trench, where t1 ≤ 1.15 t2 or t1 ≤ 1.2 t2 or t1 ≤ 1.5 t2.

[0118] Example 11. The transistor device of any one of examples 7 to 10, wherein the second contact is at least partially positioned in the gap.

[0119] Example 12. The transistor device of any one of examples 1 to 11, wherein the field plate extension extends to the first main surface.

[0120] Example 13. The transistor device according to any one of Examples 1 to 12, wherein the columnar trench has a maximum area at in a plane parallel to the first main surface, and the gate electrode is dimensioned and shaped to have a maximum area a g in the plane parallel to the first principal surface and such that 10% ≤ (a g / a t ) *100 ≤ 90 % or 20 % ≤ (a g / a t ) *100 ≤ 80 %, 25 % ≤ (a g / a t ) *100 ≤ 75 % and / or the field plate extension is dimensioned and shaped so that it has a maximum area a e in the plane parallel to the first principal surface and such that 10% ≤ (a e / a t ) *100 ≤ 90 % or 20 % ≤ (a e / a t ) *100 ≤ 80 %, 25 % ≤ (a e / a t ) *100 ≤ 75 % and / or a ratio of a e / a g is within the range of 1 / 9 to 9 / 1, and / or where the columnar trench has a circumferential length At in a plane parallel to the first main surface, and the gate electrode is dimensioned and shaped to have a maximum circumferential length A g in the plane parallel to the first principal surface and such that 10% ≤ (A g / A t ) *100 ≤ 90 % or 20 % ≤ (A g / A t ) *100 ≤ 80 %, 25 % ≤ (A g / A t ) *100 ≤ 75 % and / or the field plate extension is dimensioned and shaped so that it has a maximum circumferential length A e in the plane parallel to the first principal surface and such that 10% ≤ (A e / A t ) *100 ≤ 90 % or 20 % ≤ (A e / A t ) *100 ≤ 80 %, 25 % ≤ (A e / A t ) *100 ≤ 75 % and / or a ratio of A e / A g within the range of 1 / 9 to 9 / 1.

[0121] Example 14. The transistor device of any one of examples 1 to 13, wherein the field plate comprises a lower portion and an upper portion located below the gate electrode, the lower portion having a smaller area than the upper portion.

[0122] Example 15. The transistor device of any one of examples 1 to 14, wherein the semiconductor substrate comprises a drain region of a first conductivity type formed on the second surface, a drift region of the first conductivity type formed on the drain region, a body region of a second conductivity type opposite to the first conductivity type formed on the drift region, and a source region of a first conductivity type formed on and / or in the body region.

[0123] Example 16. The transistor device of any one of Examples 1 to 15, wherein the transistor device comprises a plurality of columnar trenches arranged in an array and further comprising a metallization layer located on the first main surface, the metallization structure comprising: a first metallization structure extending between the first contacts of the columnar trenches, and a second metallization structure extending between the second contacts of the columnar trenches, wherein the first metallization structure and the second metallization structure extend substantially parallel to each other.

[0124] Example 17. The transistor device of example 16, wherein the second metallization structure electrically connects the field plates to the source region.

[0125] Example 18. The transistor device of Example 16 or Example 17, wherein the second contact extends between and is in contact with the field plate and the source region.

[0126] Example 19. A method of forming a gate electrode and a field plate in a columnar trench, the method comprising: Providing a semiconductor substrate having a first main surface and a columnar trench comprising a bottom surface and a sidewall extending from the bottom surface to the first main surface, wherein the sidewall and the bottom surface are lined with a field dielectric and the columnar trench is filled with a first conductive material; partially removing the field dielectric and the conductive material from the columnar trench and forming a gate recess arranged in the columnar trench asymmetrically with respect to a longitudinal axis of the columnar trench; Forming a dielectric on walls of the recess; Inserting a second conductive material into the gate recess to form a gate electrode, wherein the first conductive material extends to the first main surface laterally adjacent to the gate electrode and forms the field plate.

[0127] Example 20. The method of Example 19, wherein partially removing the dielectric and the conductive material from the columnar trench comprises: Exposing the field dielectric at the top of the columnar trench, forming a conductive layer on the exposed field dielectric and on the conductive material in the bottom surface of the trench, the conductive layer extending to the first main surface and surrounding a central gap; Forming an electrically insulating intermediate layer in the central gap; Partially removing the conductive layer and exposing the electrically insulating interlayer and the field dielectric on the sidewall to form the gate recess.

[0128] Example 21. The method of Example 20, wherein the method further comprises: Applying a mask to the first main surface, covering a first portion of the conductive layer and exposing a second portion of the conductive layer and partially covering the electrically insulating intermediate layer within the columnar trench, Removing the exposed second portion of the conductive layer and forming the gate recess, Removing the mask.

[0129] Example 22. The method of any one of Examples 19 to 21, wherein the method further comprises: Applying an electrically insulating layer to the first main surface covering the trenches, Forming a first opening exposing the gate electrode, forming a second opening exposing the field plate electrode; Inserting a conductive material into the first and second openings to form a first contact to the gate electrode and a second contact to the field plate.

[0130] Example 23. The method of example 22, wherein the second opening further exposes the source region and the body region, and the second contact is further connected to the source region and the body region.

[0131] Example 24. The method of Example 22, further comprising forming a third opening exposing the body region and the source region, and inserting the conductive material into the third opening to form a third contact to the source region and the body region separate from the second contact to the field plate.

[0132] Spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like are used for ease of description to indicate the positioning of an element relative to another. These terms are intended to encompass various orientations of the device in addition to the various orientations illustrated in the figures. Further, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0133] As used herein, the terms “having,” “containing,” “including,” “comprising,” and the like are open-ended terms that indicate the presence of stated elements or features but do not preclude additional elements or features.

Claims

[1] Transistor device (10) comprising: a semiconductor substrate (11) comprising a first main surface (12); a columnar trench (13) disposed in the first main surface and comprising a bottom surface (14) and a sidewall (15), the sidewall extending from the bottom surface to the first main surface; a gate electrode (16) positioned in the columnar trench and electrically insulated from the semiconductor substrate by a gate dielectric (17), a field plate (18) positioned in the columnar trench below the gate electrode and electrically insulated from the gate electrode and from the semiconductor substrate by a field dielectric (19), wherein the gate electrode is asymmetric about a longitudinal axis (20) of the columnar trench, and wherein the field plate comprises a field plate extension (21) extending from the field plate to the first main surface and laterally adjacent to the gate electrode. [2] The transistor device (10) of claim 1, further comprising: a first contact (22) extending from the first main surface into the columnar trench, the first contact being electrically connected to the gate electrode, and a second contact (23) extending from the first main surface into the columnar trench, the second contact being electrically connected to the field plate, wherein the first contact and the second contact are arranged laterally next to each other. [3] The transistor device (10) of claim 2, wherein the first contact and the second contact are located on opposite sides of the columnar trench. [4] A transistor device (10) according to any one of claims 1 to 3, wherein the field plate extension is electrically insulated laterally from the gate electrode by an intermediate dielectric. [5] The transistor device (10) of claim 4, wherein the intermediate dielectric is located centrally in the columnar trench and extends from the first major surface to the field plate. [6] The transistor device (10) according to any one of claims 1 to 5, wherein the gate electrode is provided by a single electrically conductive portion having an open ring shape with a gap located between two distal ends of the open ring shape. [7] The transistor device (10) of any one of claims 1 to 6, wherein a first thickness (t1) of the field dielectric at a first distance from the bottom surface is less than a second thickness (t2) of the field dielectric at a second distance from the bottom surface, the first distance being greater than the second distance, and a first circumference of the columnar field plate at the first distance being greater than a second circumference of the columnar field plate at the second distance. [8] Transistor device (10) according to one of claims 1 to 7, wherein the columnar trench has a maximum circumference A t in a plane parallel to the first main surface, and the gate electrode is dimensioned and shaped to have a maximum circumferential length A g in the plane parallel to the first principal surface and such that 10% ≤ (A g / A t ) *100 ≤ 90 % or 20 % ≤ (Ag / A t ) *100 ≤ 80 %, 25 % ≤ (A g / A t ) *100 ≤ 75 % and / or the field plate extension is dimensioned and shaped so that it has a maximum circumferential length A e in the plane parallel to the first principal surface and such that 10% ≤ (A e / A t ) *100 ≤ 90 % or 20 % ≤ (A e / A t ) *100 ≤ 80 %, 25 % ≤ (A e / A t ) *100 :5 75% and / or a ratio of A e / A g within the range of 1 / 9 to 9 / 1. [9] The transistor device (10) of any one of claims 1 to 8, wherein the transistor device comprises a plurality of columnar trenches arranged in an array, and further comprising a metallization layer located on the first main surface, the metallization layer (33; 60) comprising: a first metallization structure (34) extending between the first contacts of the columnar trenches, and a second metallization structure (32) extending between the second contacts of the columnar trenches, wherein the first metallization structure and the second metallization structure extend substantially parallel to each other. [10] A method of forming a gate electrode (16) and a field plate (18) in a columnar trench (13), the method comprising: Providing a semiconductor substrate (11) having a first main surface (12) and a columnar trench (13) comprising a bottom surface (14) and a sidewall (15) extending from the bottom surface to the first main surface, wherein the sidewall and the bottom surface are lined with a field dielectric (19) and the columnar trench is filled with a first conductive material (40); partially removing the field dielectric and partially removing the first conductive material from the columnar trench and forming a gate recess (37) arranged in the columnar trench asymmetrically with respect to a longitudinal axis (20) of the columnar trench; forming a dielectric (17) on walls of the recess; Inserting a second conductive material (47) into the gate recess to form a gate electrode (16), wherein the first conductive material extends to the first main surface laterally adjacent to the gate electrode and forms the field plate. [11] The method of claim 10, wherein partially removing the field dielectric and the conductive material from the columnar trench comprises: Removing the first conductive material at the top of the columnar trench, Exposing the field dielectric at the top of the columnar trench, forming a conductive layer (41) on the exposed field dielectric and on the conductive material in the bottom surface of the trench, the conductive layer extending to the first main surface and surrounding a central gap; forming an electrically insulating intermediate layer (43) in the central gap; Partially removing the conductive layer and exposing the electrically insulating interlayer and the field dielectric on the sidewall to form the gate recess. [12] The method of claim 11, wherein the method further comprises: Applying a mask (44) to the first main surface, covering a first portion of the conductive layer and exposing a second portion of the conductive layer and partially covering the electrically insulating intermediate layer within the columnar trench, Removing the exposed second portion of the conductive layer and forming the gate recess, Removing the mask. [13] A method according to any one of claims 10 to 12, wherein the method further comprises: Applying an electrically insulating layer (48) to the first main surface covering the trenches, forming a first opening (49) exposing the gate electrode, forming a second opening (50) exposing the field plate; Inserting a conductive material (53) into the first and second openings to form a first contact to the gate electrode and a second contact to the field plate. [14] The method of claim 13, wherein the second opening further exposes the source region (27) and the body region (26) and the second contact is further connected to the source region and the body region. [15] The method of claim 13, further comprising forming a third opening exposing the body region and the source region, and inserting the conductive material into the third opening to form a third contact to the source region and the body region separate from the second contact to the field plate.

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