METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT

Abstract

Method for fabricating a semiconductor device (100), comprising the following steps: (a) fabricating a semiconductor substrate (SUB) of a first conductive type, the semiconductor substrate (SUB) having a top surface (TS) and a bottom surface (BS); (b) after step (a), forming a trench (TR) in the semiconductor substrate (SUB) on the top surface (TS) of the semiconductor substrate (SUB); (c) after step (b), forming a first insulating film (IF1) within the trench (TR) and on the top surface (TS) of the semiconductor substrate (SUB); (d) after step (c), forming a field plate electrode (FP) on the first insulating film (IF1) located within the trench (TR); (e) after step (d), thinning the first insulating film (IF1) and exposing an upper portion of the field plate electrode (FP) from the first insulating film (IF1);(f) after step (e), performing an isotropic etching process on the upper section of the field plate electrode (FP) exposed by the first insulating film (IF1); (g) after step (f), removing the first insulating film (IF1) located on the upper surface (TS) of the semiconductor substrate (SUB) and leaving the first insulating film (IF1) located within the trench (TR) free such that an upper surface of the first insulating film (IF1) located within the trench (TR) is lower in cross-sectional view than the upper section of the field plate electrode (FP);and (h) after step (g), in cross-sectional view, forming a gate insulating film (GI) within the trench (TR) that lies above the top surface of the first insulating film (IF1), and forming a second insulating film (IF2) on a top surface of the upper section of the field plate electrode (FP) and on a side surface of the field plate electrode (FP) exposed by the first insulating film (IF1) in step (g), wherein the field plate electrode (FP) is made of a polycrystalline silicon film, wherein the isotropic etching process in step (f) is a chemical dry etching process using CF4 gas, and wherein a corner of the upper section of the field plate electrode (FP) is chamfered or rounded by the chemical dry etching process.

Description

CROSS-REFERENCE TO THE RELATED APPLICATION

[0001] The disclosure of Japanese Patent Application No. 2023-018587, filed on February 9, 2023, including specification, drawings and abstract, is incorporated herein by reference in its entirety. BACKGROUND

[0002] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including an insulating film formed inside a trench.

[0003] A trench-gate structure, in which a gate electrode is embedded in a trench, is applied to a semiconductor device including a semiconductor element such as a power metal-oxide-semiconductor field-effect transistor (MOSFET). One type of trench-gate structure is a split-gate structure, in which a field-plate electrode is formed under the trench, while a gate electrode is formed on top of the trench. A source potential is supplied to the field-plate electrode from a source electrode. The field-plate electrode spreads a depletion layer in a drift region, allowing the drift region to have a higher concentration and reducing the resistance of the drift region.

[0004] The disclosed technology is listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2011-199109

[0006] For example, Patent Document 1 discloses a MOSFET with a split-gate structure. In Patent Document 1, a polysilicon film is formed within the trench and on a semiconductor substrate, and the polysilicon film is etched back using an anisotropic etching process to form the field plate electrode within the trench. Furthermore, an insulating film is formed between a gate electrode and the field plate electrode using a thermal oxidation process. SUMMARY

[0007] When the field plate electrode is formed by etching back, a corner of an upper portion of the field plate electrode is slightly protruded. Thus, the electric field is easily concentrated at the protruded corner, and leakage current is easily caused between the gate electrode and the field plate electrode. Furthermore, there is a risk of dielectric breakdown of the insulating film formed between the gate electrode and the field plate electrode. This poses the problem of reduced reliability of the semiconductor device.

[0008] Further items and new features are set out in the description of this specification and the attached drawings.

[0009] The following briefly outlines the typical aspects of the embodiments disclosed in the present application.

[0010] A method of manufacturing a semiconductor device according to one embodiment includes the following steps: (a) manufacturing a semiconductor substrate of a first conductive type, the semiconductor substrate having an upper surface and a lower surface; (b) after step (a), forming a trench in the semiconductor substrate on the upper surface of the semiconductor substrate; (c) after step (b), forming a first insulating film within the trench and on the upper surface of the semiconductor substrate; (d) after step (c), forming a field plate electrode on the first insulating film located within the trench; (e) after step (d), thinning the first insulating film and exposing an upper portion of the field plate electrode from the first insulating film; (f) after step (e), performing an isotropic etching process on the upper portion of the field plate electrode exposed from the first insulating film;(g) after step (f), removing the first insulating film located on the upper surface of the semiconductor substrate and recessing the first insulating film located within the trench such that an upper surface of the first insulating film located within the trench is positioned lower than the upper portion of the field plate electrode in cross-sectional view; and (h) after step (g), in cross-sectional view, forming a gate insulating film within the trench positioned above the upper surface of the first insulating film, and forming a second insulating film on an upper surface of the upper portion of the field plate electrode and on a side surface of the field plate electrode exposed from the first insulating film in step (g);

[0011] According to one embodiment, the reliability of the semiconductor device can be improved. SHORT DESCRIPTIONS OF THE DRAWINGS Fig. 1 is a plan view illustrating a complete semiconductor device according to a first embodiment. Fig. 2 is a plan view of a main part of the semiconductor device according to the first embodiment. Fig. 3 is a plan view of a main part of the semiconductor device according to the first embodiment. Fig. 4 is a cross-sectional view illustrating the semiconductor device according to the first embodiment. Fig. 5 is a cross-sectional view illustrating a step of manufacturing the semiconductor device according to the first embodiment. Fig. 6 is a cross-sectional view illustrating a step of manufacturing the semiconductor device (continued from Fig. 5). Fig. Fig. 7 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 6. Fig. Fig. 8 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 7. Fig. 9 is a cross-sectional view illustrating a step of manufacturing the semiconductor device (continued from Fig. 8). Fig. 10 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 9. Fig. 11 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 10. Fig. 12 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 11. Fig. 13 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 12. Fig. 14 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 13. Fig. 15 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 14. Fig. 16 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 15. Fig. 17 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 16. Fig. 18 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 17. Fig. 19 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 18. Fig. Fig. 20 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 19. Fig. 21 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 20. Fig. 22 is a cross-sectional view illustrating a step of manufacturing a semiconductor device according to a second embodiment. Fig. 23 is a cross-sectional view illustrating a step of manufacturing a semiconductor device according to a first test example. Fig. 24 is a cross-sectional view illustrating a step of manufacturing the semiconductor device, continued from Fig. 23. Fig. 25 is a cross-sectional view illustrating a step of manufacturing a semiconductor device according to a second test example. DETAILED DESCRIPTION

[0012] The embodiments will be described in detail below with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference numerals throughout the drawings to explain the embodiments, so a repeated description is omitted. Furthermore, the description of the same or similar sections will generally not be repeated unless particularly necessary in the following embodiments.

[0013] An X-direction, a Y-direction, and a Z-direction described in the present application intersect and are perpendicular to each other. In this application, the Z-direction is described as the vertical direction, the height direction, or the depth direction of a structure. Terms such as "top view" or "planar view" used in this application mean that a "plane" formed by the X-direction and the Y-direction is viewed in the Z-direction. (First embodiment)<Struktur des Halbleiterbauelements>

[0014] A semiconductor device 100 according to a first embodiment is described below with reference to the Fig. 1 to 4. 1 to 4. Main features of the present application are structures of a field plate electrode FP and an insulating film IF2, as well as steps for manufacturing these components, and these features will be described in detail later.

[0015] Fig. 1 is a plan view of a semiconductor chip as a semiconductor device 100. Each of the Fig. 2 and Fig. 3 is a plan view of a main part of an enlarged region 1A of Fig. 1. Fig. 3 illustrates a structure below Fig. 2 and mainly illustrates a trench gate structure formed in a semiconductor substrate SUB. The positions of the holes CH1 to CH3 in Fig. 2 correspond to the positions of holes CH1 to CH3 in Fig. 3 agree. Fig. 4 is a cross-sectional view along line AA and line BB of the Fig. 2 and Fig. 3.

[0016] Fig. Figure 1 mainly illustrates wiring formed on the semiconductor substrate SUB. The semiconductor device 100 includes a cell region CR and an outer region OR surrounding the cell region CR in plan view. Main semiconductor elements such as a plurality of MOSFETs are formed in the cell region CR. The outer region OR is used to connect a gate wiring GW to a gate electrode GE and to form a structure serving as a termination region.

[0017] As in Fig. 1 and Fig. 2, the region CR of the cell is covered with a source electrode SE. The gate wiring GW surrounds the source electrode SE in plan view. Although not illustrated here, the source electrode SE and the gate wiring GW are covered with a protective film such as a polyimide film. Openings are provided in a part of the protective film, and the source electrode SE and the gate wiring GW exposed at the openings serve as a source pad SP and a gate pad GP, respectively. When external interconnections are connected to the source pad SP and the gate pad GP, the semiconductor device 100 is electrically connected to another semiconductor chip, a lead frame, a wiring substrate, or the like. Note that the external interconnection element is, for example, a wire made of gold or copper, or a clip made of copper sheet, or the like.

[0018] As in Fig. As illustrated in Figure 3, a plurality of trenches TR are formed in the semiconductor substrate SUB. A plurality of trenches TR are formed in a stripe shape in the cell region CR and extend in the Y direction and are adjacent to each other in the X direction.

[0019] In the CR region, a field plate electrode FP is formed in the lower portion of the trench TR within the trench TR, and a gate electrode GE is formed in the upper portion of the trench TR. A portion of the field plate electrode FP forms a contact portion FPa. The contact portion FPa is formed in a portion of the CR cell region. The field plate electrode FP, which forms the contact portion FPa, is formed not only at the lower portion of the trench TR but also at the upper portion of the trench TR within the trench TR.

[0020] A cross-sectional structure of the semiconductor device 100 is described below with reference to Fig. 4 described.

[0021] As in Fig. As illustrated in Figure 4, the semiconductor device 100 includes the n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB includes a low-concentration n-type drift region NV. The n-type semiconductor substrate SUB itself configures the drift region NV. Note that the semiconductor substrate SUB may have a stacked structure consisting of an n-type silicon substrate and an n-type semiconductor layer grown on the n-type silicon substrate while doped with phosphorus (P) by an epitaxial process. In this case, the low-concentration n-type semiconductor layer forms the drift region NV, while the high-concentration n-type silicon substrate forms a drain region ND.

[0022] The n-type drain region ND is formed in the semiconductor substrate SUB on the lower surface BS of the semiconductor substrate SUB. The ND region has a higher impurity concentration than that of the drift region NV. The drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is made of, for example, a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a stacked film in which these metal films are stacked accordingly. The drain region ND and the drain electrode DE are formed over the cell region CR and the outer region OR. A drain potential is applied to the semiconductor substrate SUB (the drain region ND and the drift region NV) from the drain electrode DE.

[0023] Trenches TR with a predetermined depth from the upper surface TS of the semiconductor substrate SUB are formed in the semiconductor substrate SUB on the upper surface TS of the semiconductor substrate SUB. The depth of the trench TR is, for example, equal to or greater than 5 µm and equal to or less than 7 µm. Within the trench TR, the field plate electrode FP is formed in the lower portion of the trench TR via an insulating film IF1, while the gate electrode GE is formed in the upper portion of the trench TR via a gate insulating film GI.

[0024] The upper surface of the insulating film IF1 is lower than the upper surface of the field plate electrode FP. The gate insulating film GI is formed on the insulating film IF1 within the trench TR. An insulating film IF2 is formed on the upper surface of the field plate electrode FP and also on the side surfaces of the field plate electrode FP exposed by the insulating film IF1. The gate electrode GE is also formed between the field plate electrode FP exposed by the insulating film IF1 and the semiconductor substrate SUB via the gate insulating film GI and the insulating film IF2.

[0025] The insulating film IF1 is formed between the semiconductor substrate SUB and the field plate electrode FP. The insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. The insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. The semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP are electrically insulated from each other by the insulating films.

[0026] The field plate electrodes FP and the gate electrodes GE each consist of a polycrystalline silicon film doped with n-type impurities. The impurity concentration of each of the polycrystalline silicon films is higher than the impurity concentration of the drift region NV and is, for example, 4.0 × 10 20 / cm 3 .

[0027] The insulating film IF1, the insulating film IF2, and the gate insulating film GI are each made of, for example, a silicon oxide film. The thickness of the insulating film IF1 is greater than the respective thicknesses of the insulating film IF2 and the gate insulating film GI. The thickness of the insulating film IF1 is, for example, equal to or greater than 400 nm and equal to or less than 600 nm. The thickness of the insulating film IF2 and the gate insulating film GI is, for example, equal to or greater than 50 nm and equal to or less than 70 nm. An insulating film IF3 is formed on the gate electrode GE. The insulating film IF3 is made of, for example, a silicon oxide film.

[0028] A p-type body region PB is formed to be shallower than the trench TR in the semiconductor substrate SUB on the upper surface TS of the semiconductor substrate SUB. An n-type source region NS is formed in the body region PB. The region NS has a higher impurity concentration than that of the drift region NV.

[0029] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB to cover the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, equal to or greater than 700 nm and equal to or less than 900 nm.

[0030] A hole CH1 is formed in the interlayer insulating film IL, which penetrates the interlayer insulating film IL and the source region NS and reaches the body region PB. A highly concentrated diffusion region PR is formed at the bottom of the hole CH1 in the body region PB. The highly concentrated diffusion region PR has a higher impurity concentration than that of the body region PB.

[0031] The source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is electrically connected to the source region NS, the body region PB, and the highly concentrated diffusion region PR via the hole CH1, and supplies these impurity regions with a source potential.

[0032] As in cross section BB in Fig. As illustrated in Figure 4, a part of the field plate electrode FP forms the contact portion FPa of the field plate electrode FP. The upper surface of the insulating film IF1 in contact with the field plate electrode FP is lower than the upper surface of the insulating film IF1 in contact with the contact portion FPa. That is, the upper surface of the insulating film IF1 in cross section AA is located at a depth equal to or greater than 300 nm and equal to or less than 400 nm from the upper surface TS of the semiconductor substrate SUB. The upper surface of the insulating film IF1 in cross section BB is located at a depth equal to or greater than 50 nm and equal to or less than 100 nm from the upper surface TS of the semiconductor substrate SUB.

[0033] The insulating film IF2 is formed on the upper surface of the contact portion FPa and also on the side surfaces of the contact portion FPa exposed by the insulating film IF1. The insulating film IF3 is formed on the insulating film IF2. Note that the insulating film IF3 does not need to be formed as described later.

[0034] A hole CH3 is formed in the interlayer insulating film IL, which penetrates the interlayer insulating film IL, the insulating film IF3, and the insulating film IF2 and reaches the contact portion FPa. The source electrode SE is electrically connected to the field plate electrode FP via the hole CH3 and supplies a source potential to the field plate electrode FP.

[0035] Although not illustrated here, a hole CH2 is formed in the interlayer insulating film IL and the insulating film IF3, which reaches and penetrates the gate electrode GE. The gate wiring GW is electrically connected to the gate electrode GE via the hole CH2 and supplies a gate potential to the gate electrode GE.

[0036] A plug PG is embedded in each of the holes CH1 to CH3. A plug PG is made of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film consists of a stacked film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0037] The source electrode SE and the gate wiring GW consist of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium-tungsten film, and the conductive film is, for example, an aluminum alloy film with copper or silicon added.

[0038] In the first embodiment, the corner of the upper portion of the field plate electrode FP is chamfered or rounded. Thus, the regions where the electric field is concentrated are uniform between the gate electrode GE and the field plate electrode FP. That is, since the electric field concentration is reduced, the risk of leakage current occurring between the gate electrode GE and the field plate electrode FP is suppressed. Therefore, the reliability of the semiconductor device 100 can be improved.

[0039] A method for manufacturing a semiconductor device to form the structure of such a field plate electrode FP will be described below. <Verfahren zur Herstellung eines Halbleiterbauelements>

[0040] Each manufacturing step in the method for manufacturing the semiconductor device 100 will be described below with reference to the Fig. 5 to 21 described.

[0041] As in Fig. As illustrated in Figure 5, the n-type semiconductor substrate SUB having the upper surface TS and the lower surface BS is first fabricated. As described above, the semiconductor substrate SUB may have a stacked structure composed of an n-type silicon substrate and an n-type semiconductor layer formed on the silicon substrate by an epitaxial growth method.

[0042] Next, as in Fig. 6, the trench TR is formed in the semiconductor substrate SUB on the upper surface TS of the semiconductor substrate SUB.

[0043] First, a silicon oxide film is formed on the semiconductor substrate SUB, e.g., by a CVD process. Next, the silicon oxide film is patterned using a photolithographic process and anisotropic etching to form a hard mask HM. Subsequently, an anisotropic etching process is performed, using the hard mask HM as a mask, to form the trench TR in the semiconductor substrate SUB. The trench TR is formed in the semiconductor substrate SUB such that it extends from the upper surface TS toward the lower surface BS. The hard mask HM is then removed, e.g., by a wet etching process using a hydrofluoric acid solution.

[0044] Next, as in Fig. As illustrated in Figure 7, the insulating film IF1 is formed within the trench TR and on the semiconductor substrate SUB. The insulating film IF1 is, for example, a silicon oxide film formed by a thermal oxidation process. Note that the insulating film IF1 may be a stacked film made of a first silicon oxide film formed by a thermal oxidation process and a second silicon oxide film formed on the first silicon oxide film by a CVD method.

[0045] As in Fig. As illustrated in Figure 8, the conductive film CF1 is next formed on the insulating film IF1, e.g., by a CVD method, to fill the interior of the trench TR. The conductive film CF1 is, for example, an n-type polycrystalline silicon film. To advantageously embed the conductive film CF1 in the trench TR, the conductive film CF1 can be formed by two separate processes for forming a first polycrystalline silicon film and forming a second polycrystalline silicon film.

[0046] Then, as in Fig. 9, the conductive film CF1 formed (lying) outside the trench TR is removed to form the conductive film CF1 remaining inside the trench TR as the field plate electrode FP.

[0047] First, the conductive film CF1 formed (lying) outside the trench TR is removed, e.g., by a polishing process using a chemical mechanical polishing (CMP) method. Subsequently, the upper surface of the conductive film CF1 located inside the trench TR is recessed, e.g., by an anisotropic etching process using SF6 gas. In this way, the field plate electrode FP is formed within the trench TR.

[0048] Next, as in Fig. 10 illustrates that in order to leave a part of the field plate electrode FP as a contact portion FPa, another part of the field plate electrode FP is selectively etched (ie, the field plate electrode FP is selectively recessed).

[0049] First, as illustrated in cross section BB, a resist pattern RP1 is formed that selectively covers a portion of the field plate electrode FP that is to be the contact portion FPa. Subsequently, the field plate electrode FP is patterned, for example, by an anisotropic etching process using SF6 gas, with the resist pattern RP1 as a mask. That is, as illustrated in cross section AA, another portion of the field plate electrode FP is selectively etched (i.e., the field plate electrode FP is selectively recessed). A non-recessed portion of the field plate electrode FP is the contact portion FPa. Subsequently, the resist pattern RP1 is removed by an ashing process.

[0050] Next, as in Fig. As illustrated in Figure 11, the insulating film IF1 is thinned through an isotropic etching process, and the upper portion of the field plate electrode FP is exposed from the insulating film IF1. At this time, the upper portion of the contact part FPa is also exposed from the insulating film IF1. At this time, it should be noted that the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB and within the trench TR is not completely removed. Isotropic etching is, for example, a wet etching process using a hydrofluoric acid solution.

[0051] Due to the anisotropic etching process of the Fig. 9 and Fig. 10, the exposed corner of the upper section of the field plate electrode FP and the contact section FPa is highlighted.

[0052] Next, as in Fig. As illustrated in Figure 12, the upper portion of the field plate electrode FP exposed from the insulating film IF1 is isotropically etched. Similarly, the upper portion of the contact portion FPa exposed from the insulating film IF1 is isotropically etched. Isotropic etching is a dry chemical etching process using CF4 gas. In this way, the corner of the upper portion of the field plate electrode FP and the contact portion FPa is chamfered or rounded.

[0053] At the time of isotropic etching processing, the thinned insulating film IF1 on the upper surface TS of the semiconductor substrate SUB and within the trench TR acts as an etch stopper.

[0054] Next, as in Fig. 13 illustrates, by isotropic etching on the insulating film IF1, the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB is removed. At the same time, the insulating film IF1 located within the trench TR is removed in the direction of the arrow from Fig. 13 so that the upper surface of the insulating film IF1 located within the trench TR is lower than the upper portion of the field plate electrode FP in cross-sectional view.

[0055] Next, as in Fig. As illustrated in Figure 14, the insulating film GI is formed within the trench TR located on the upper surface of the insulating film IF1 recessed by the isotropic etching process. At the same time, the insulating film IF2 is formed on the (upper) surface of the upper portion of the field plate electrode FP and the side surface of the field plate electrode FP, which has been newly exposed from the insulating film IF1 by the isotropic etching process.

[0056] The insulating film GI and the insulating film IF2 each consist of a silicon oxide film OX1. The silicon oxide film OX1 is formed by a dry oxidation process. The dry oxidation process is, for example, a thermal oxidation process using oxygen gas under a temperature condition equal to or higher than 1000°C and equal to or lower than 1200°C. The thickness of the silicon oxide film OX1 is, for example, equal to or greater than 50 nm and equal to or less than 70 nm. <Vergleich zwischen den Prüfbeispielen und der ersten Ausführungsform>

[0057] With reference to the Fig. 23 to 25, semiconductor devices according to the first and second test examples tested by the present inventors are described herein.

[0058] In the first test example, as in Fig. 23 illustrates that, by a single isotropic etching process, after the field plate electrode FP including the contact portion FPa has been formed, the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB is removed, while the insulating film IF1 located within the trench TR is left out. The chemical dry etching process of Fig. 12 is not carried out in the first test example.

[0059] Then, as in Fig. 24, a dry oxidation process is performed to form the silicon oxide film OX1 (the gate insulating film GI and the insulating film IF2).

[0060] The first test example differs from the first embodiment in that the corner of the upper portion of the field plate electrode FP remains protruding. This tends to concentrate the electric field on the protruding portions, causing leakage current between the field plate electrode FP and the gate electrode GE described later. Furthermore, there is a risk of deteriorating the dielectric breakdown of the insulating film IF2.

[0061] On the other hand, in the first embodiment, the chemical dry etching process of Fig. 12 is applied, and thus the corner of the upper portion of the field plate electrode FP is chamfered or rounded. This alleviates the concentration of the electric field, thus suppressing the leakage current and also preventing the deterioration of the dielectric breakdown of the insulating film IF2. Therefore, the reliability of the semiconductor device 100 can be improved.

[0062] Fig. 25 illustrates a step for forming the gate insulating film GI and the insulating film IF2 according to a second test example. While the first embodiment uses the dry oxidation method, the second test example uses a wet oxidation method. The wet oxidation method is, for example, a thermal oxidation method using moisture under conditions equal to or higher than 850°C and equal to or lower than 950°C.

[0063] The impurity concentration of the polycrystalline silicon film forming the field plate electrode FP is higher than the impurity concentration of the drift region NV. Therefore, the insulating film IF2 can be slightly thickened than the gate insulating film GI in the wet oxidation process due to the influence of enhanced oxidation.

[0064] However, in the wet oxidation process, the roughness of the oxidized surface of the field plate electrode FP is slightly increased. As a result, the insulating film IF2 is locally and slightly thinner, and the electric field tends to concentrate on the thinner section. Furthermore, it is difficult to moderate the electric field concentration at the protruding corner of the field plate electrode FP.

[0065] On the other hand, the influence of enhanced oxidation in the dry oxidation process in the first embodiment is less than in the wet oxidation process. However, the roughness of the oxidized surface of the field plate electrode FP is improved. Therefore, the electric field concentration can be easily moderated.

[0066] As described above, in the first embodiment, the electric field concentration can be suppressed only by the chemical dry etching process at the field plate electrode FP. However, if the insulating film IF2 is also formed by the dry oxidation process, the electric field concentration can be further suppressed.

[0067] Fig. 15 illustrates a manufacturing step in continuation of Fig. 14. As in Fig. As illustrated in Figure 15, the conductive film CF2 is formed on the upper surface TS of the semiconductor substrate SUB to fill the trench TR, for example, by a CVD method. The conductive film CF2 is, for example, an n-type polycrystalline silicon film.

[0068] As in Fig. As illustrated in Figure 16, the conductive film CF2 formed outside the trench TR is removed when an anisotropic dry etching process is performed for the conductive film CF2. Thus, as illustrated in cross section AA, the gate electrode GE is formed on the field plate electrode FP within the trench TR via the insulating film IF2.

[0069] As illustrated in the cross-section in BB, the conductive film CF2 within the trench TR, where the contact portion FPa is formed, is removed. The anisotropic etching process is performed as an overetch to remove the excess conductive film CF2 on the contact portion FPa, so that the upper surface of the gate electrode GE is slightly lower than the upper surface TS of the semiconductor substrate SUB. Thus, the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP (contact portion FPa), which are located within the trench TR, are electrically isolated from each other.

[0070] As in Fig. As illustrated in Figure 17, an insulating film IF3 is formed on the upper surface TS of the semiconductor substrate SUB, covering the trench TR, for example, by a CVD process. The insulating film IF3 is, for example, a silicon oxide film.

[0071] As in Fig. As illustrated in Figure 18, the insulating film IF3 and the gate insulating film GI on the upper surface TS of the semiconductor substrate SUB are removed by an anisotropic etching process. A portion of the insulating film IF3 remains inside the trench TR.

[0072] It should be noted that the formation of the insulating film IF3 is not absolutely necessary. However, other semiconductor elements can be formed in other regions of the semiconductor substrate SUB by using the insulating film IF3 as a protective film covering the trench TR. Another semiconductor element can be, for example, a resistance element connecting the gate pad GP and the gate wiring GW. Between the manufacturing step of Fig. 17 and the manufacturing step of Fig. 18, the resistance element can be formed by forming and patterning a conductive film on the insulating film IF3.

[0073] As in Fig. As illustrated in Figure 19, the upper surface TS of the semiconductor substrate SUB is doped with boron (B), for example, using a photolithographic process and an ion implantation process, so that a p-type body region PB is selectively formed in the semiconductor substrate SUB. The body region PB is shallower than the trench TR.

[0074] Subsequently, the semiconductor substrate is doped with, for example, arsenic (As) through a photolithographic process and an ion implantation process, so that an n-type source region NS is selectively formed in the body region PB in the cell region CR. Note that the n-type source region is not formed in the body region PB near the contact portion FPa. Subsequently, an annealing process is performed on the semiconductor substrate SUB to diffuse the impurities contained in the source region NS and the body region PB.

[0075] As in Fig. As illustrated in Figure 20, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB to cover the trench TR, for example, by a CVD method. The interlayer insulating film IL is made of, for example, a silicon oxide film. Note that the interlayer insulating film IL may be a stacked film formed from a thin silicon oxide film formed by a CVD method and a phosphorus silicate glass (PSG) or borophosphosilicate glass (BPSG) film formed by a coating method.

[0076] Next, holes CH1 to CH3 are formed in the interlayer insulating film IL. First, a resist pattern is formed on the interlayer insulating film IL, which has a pattern for opening the semiconductor substrate SUB, in which the source region NS is formed. Next, by an anisotropic etching process using the resist pattern as a mask, the hole CH1 is formed, which penetrates both the interlayer insulating film IL and the source region NS and reaches the body region PB. Next, the body region PB is doped with boron (B), for example, at the bottom of the hole CH1 by an ion implantation method, so that the highly concentrated p-type diffusion region PR is formed. The resist pattern is then removed by an ashing process.

[0077] Next, a resist pattern patterned to open the tops of the contact portion FPa and the gate electrode GE is formed on the interlayer insulating film IL. Next, through an anisotropic etching process using the resist pattern as a mask, the hole CH3, which penetrates the interlayer insulating film IL, the insulating film IF3, and the insulating film IF2 and reaches the contact portion FPa, and the hole CH2, which penetrates each of the interlayer insulating films IL and the insulating film IF3 and reaches the gate electrode GE, are formed. The resist pattern is then removed by an ashing process.

[0078] Regarding the order of formation of holes CH1 to CH3, it should be noted that any hole can be formed first.

[0079] As in Fig. 20, the plugs PG are formed in the holes CH1 to CH3, and the source electrode SE and the gate wiring GW are formed on the interlayer insulating film IL.

[0080] First, a first barrier metal film is formed inside the holes CH1 to CH3 and on the interlayer insulating film IL by a sputtering method or a CVD method. The first barrier metal film is, for example, a stacked film of a titanium nitride film and a titanium film. Then, a first conductive film is formed on the first barrier metal film by a CVD method. The first conductive film is, for example, made of a tungsten film. Next, the first barrier metal film and the first conductive film formed outside the holes CH1 to CH3 are removed by a CMP method or an anisotropic etching process. In this way, plugs PG are formed from the first barrier metal film and the first conductive film to fill the insides of the holes CH1 to CH3.

[0081] Subsequently, a second barrier metal film is formed on the interlayer insulating film IL by a sputtering process. The second barrier metal film consists, for example, of a titanium-tungsten film. Subsequently, a second conductive film is formed on the second barrier metal film by a sputtering process. The second conductive film is, for example, an aluminum alloy film with added copper or silicon. Subsequently, the second barrier metal film and the second conductive film are patterned to form the source electrode SE and the gate wiring GW.

[0082] Next, although not illustrated here, a protective film, such as a polyimide film, is formed on the source electrode SE and the gate wiring GW, e.g., by a coating process. A portion of the protective film is opened to expose regions that will be the source pad SP and the gate pad GP in the source electrode SE and the gate wiring GW.

[0083] Then the Fig. The structure illustrated in Figure 5 is provided by the following manufacturing steps. First, the bottom surface BS of the semiconductor substrate SUB is polished as required. Next, the bottom surface BS of the semiconductor substrate SUB is doped with, for example, arsenic (As) or the like by an ion implantation method, so that the n-type drain region ND is formed. When the semiconductor substrate SUB is made of a stacked structure of an n-type silicon substrate and an n-type semiconductor layer, the drain region ND is formed from the high-concentration n-type silicon substrate, and thus the formation of the drain region ND by the ion implantation method can be omitted. Subsequently, the drain electrode DE is formed on the bottom surface BS of the semiconductor substrate SUB by a sputtering method. (Second embodiment)

[0084] A semiconductor device according to a second embodiment is described below with reference to Fig. 22. In the following explanation, it should be noted that the differences from the first embodiment are mainly described, and the description of overlaps with the first embodiment is omitted.

[0085] In the first embodiment, both the gate insulating film GI and the insulating film IF2 are made of the silicon oxide film OX1. As shown in Fig. 22, in the second embodiment, each of the gate insulating films GI and the insulating film IF2 is a stacked film including the silicon oxide film OX1 and a silicon oxide film OX3. Note that Fig. 22 a manufacturing step instead of the manufacturing step of Fig. 14 of the first embodiment.

[0086] As in Fig.As illustrated in Fig. 22, first, the silicon oxide film OX1 is formed on the insulating film IF1 located within the trench TR, and the silicon oxide film OX1 is formed on the upper surface of the field plate electrode FP and also on the side surface of the field plate electrode FP exposed from the insulating film IF1. The silicon oxide film OX1 is formed by a dry oxidation process. The dry oxidation process is a thermal oxidation process using, for example, oxygen gas under a condition equal to or higher than 1000°C and equal to or lower than 1200°C, similar to the first embodiment. The thickness of the silicon oxide film OX1 according to the second embodiment is, for example, equal to or greater than 25 nm and equal to or less than 35 nm.

[0087] Subsequently, a silicon oxide film OX2 is formed on the silicon oxide film OX1 using a CVD process. The silicon oxide film OX2 is a tetraethoxysilane (TEOS) film and has a thickness that is, for example, equal to or greater than 25 nm and equal to or less than 35 nm. Subsequently, a heating process can be performed to densify the film texture of the silicon oxide film OX2. Such a heating process is performed, for example, in a nitrogen gas atmosphere or an oxygen gas atmosphere at a temperature equal to or higher than 900°C and equal to or lower than 1000°C.

[0088] The silicon oxide film OX2 formed by a CVD process is easier to form with a uniform thickness than the silicon oxide film OX3 formed by a wet oxidation process as in the second test example. Therefore, it is difficult to locally thin the insulating film IF2, and the occurrence of electric field concentration can be easily suppressed.

[0089] The total thickness of the insulating film IF2 can also be easily adjusted by the silicon oxide film OX2. For example, the dielectric breakdown between the gate electrode GE and the field plate electrode FP can be slightly improved by increasing the thickness of the silicon oxide film OX2.

[0090] The number of layers of silicon oxide films stacked on the silicon oxide film OX1 by the CVD method is not limited to one, namely the silicon oxide film OX2, and a plurality of films can be stacked.

[0091] The silicon oxide film OX1, rather than the silicon oxide film OX2, is preferred as the insulating film in contact with the field plate electrode FP and the semiconductor substrate SUB. The silicon oxide film OX1 formed by the dry oxidation process can improve the interface state between the insulating film IF2 and the field plate electrode FP, as well as the interface state between the gate insulating film GI and the semiconductor substrate SUB, more than the silicon oxide film OX2 formed by the CVD process.

[0092] The present invention has been specifically described in the foregoing with reference to the embodiments. However, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of the present invention. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023018587

[0001] JP 2011199109

[0005]

Claims

A method of manufacturing a semiconductor device, comprising the following steps: (a) preparing a semiconductor substrate of a first conductive type, the semiconductor substrate having an upper surface and a lower surface; (b) after step (a), forming a trench in the semiconductor substrate on the upper surface of the semiconductor substrate; (c) after step (b), forming a first insulating film within the trench and on the upper surface of the semiconductor substrate; (d) after step (c), forming a field plate electrode on the first insulating film located within the trench; (e) after step (d), thinning the first insulating film and exposing an upper portion of the field plate electrode from the first insulating film; (f) after step (e), performing an isotropic etching process on the upper portion of the field plate electrode exposed from the first insulating film;(g) after step (f), removing the first insulating film located on the upper surface of the semiconductor substrate and recessing the first insulating film located within the trench such that an upper surface of the first insulating film located within the trench is lower than the upper portion of the field plate electrode in cross-sectional view; and (h) after step (g), in cross-sectional view, forming a gate insulating film within the trench, which is located above the upper surface of the first insulating film, and forming a second insulating film on an upper surface of the upper portion of the field plate electrode and on a side surface of the field plate electrode exposed from the first insulating film in step (g). A method of manufacturing the semiconductor device according to claim 1, wherein the field plate electrode is made of a polycrystalline silicon film, and wherein the isotropic etching process in step (f) is a chemical dry etching process using CF4 gas. A method of manufacturing the semiconductor device according to claim 2, wherein a corner of the upper portion of the field plate electrode is chamfered or rounded by the chemical dry etching process. A method of manufacturing the semiconductor device according to claim 1, wherein the first insulating film is made of a silicon oxide film, and wherein each of step (e) and step (g) is performed by a wet etching process using a hydrofluoric acid solution. A method of manufacturing the semiconductor device according to claim 1, wherein in step (h), the gate insulating film and the second insulating film are formed by a thermal oxidation process using oxygen gas under a condition equal to or higher than 1000 °C and equal to or lower than 1200 °C. A method for manufacturing the semiconductor device according to claim 1, wherein the step of (h) includes the steps of: (h1) forming a first silicon oxide film within the trench positioned above the first insulating film and on the upper surface of the field plate electrode and also the side surface of the field plate electrode exposed from the first insulating film by a thermal oxidation process using oxygen gas under a condition equal to or higher than 1000°C and equal to or lower than 1200°C; and (h2) forming a second silicon oxide film on the first silicon oxide film by a CVD method, and wherein the gate insulating film and the second insulating film each include the first silicon oxide film and the second silicon oxide film. A method of manufacturing the semiconductor device according to claim 1, wherein step (d) includes the following steps: (d1) forming a first conductive film on the first insulating film to fill the interior of the trench; (d2) after step (d1), forming the first conductive film remaining inside the trench as a field plate electrode by removing the first conductive film located outside the trench; and (d3) after step (d2), selectively recessing the field plate electrode such that a part of the field plate electrode remains as a contact portion. A method for manufacturing the semiconductor device according to claim 7, further comprising the steps of: (i) after step (h), within the trench, forming a gate electrode on the field plate electrode recessed by step (d3) via the second insulating film; (j) after step (i), on the upper surface of the semiconductor substrate, forming a body region within the semiconductor substrate so as to be shallower than the trench, wherein a conductive type of the body region is a second conductive type opposite to the first conductive type; (k) after step (j), forming a source region within the body region, wherein a conductive type of the source region is the first conductive type; (l) after step (k), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the trench;(m) after step (1), forming a first hole penetrating both the interlayer insulating film and the source region and reaching the interior of the body region; (n) after step (1), forming a second hole penetrating the interlayer insulating film and reaching the gate electrode; (o) after step (1), forming a third hole penetrating the interlayer insulating film and reaching the contact portion; (p) after step (m), step (n) and step (o), forming a source electrode and a gate wiring on the interlayer insulating film;and (q) after step (p), forming a drain electrode on the lower surface of the semiconductor substrate, wherein the gate wiring is electrically connected to the gate electrode via the second hole, wherein the source electrode is electrically connected to both the source region and the body region via the first hole and is electrically connected to the field plate electrode via the third hole, and wherein the drain electrode is electrically connected to the semiconductor substrate.;