FORMING LOW PARASITIC CAPACITY ISOLATION AREAS

Abstract

One method involves forming a gate stack and etching the gate stack to create a trench penetrating the gate stack. A dielectric insulating region located beneath the gate stack is exposed to the trench, and a first and second section of the gate stack are separated by the trench. The method includes performing a first deposition process to form a first dielectric layer extending into the trench and lining the sidewalls of the first and second sections of the gate stack, and performing a second deposition process to form a second dielectric layer on top of the first dielectric layer. The second dielectric layer fills the trench.The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the following preliminary US patent application: Application No. 63 / 582,356, filed on September 13, 2023, entitled “Method of Forming Cut Metal Gate Liner by Using Low Dielectric Constant Material for Ceff Reduction”; this application is hereby incorporated into the present application by reference. BACKGROUND

[0002] Technical advances in materials and integrated circuit (IC) design have produced generations of ICs, each featuring progressively smaller and more complex circuits than the previous generations. As ICs have evolved, functional density (e.g., the number of interconnected components per chip area) has generally increased while geometry sizes have decreased. This downscaling process generally provides benefits by improving production efficiency and reducing associated costs.

[0003] This downscaling has also increased the complexity of IC processing and manufacturing, and similar advancements in IC processing and manufacturing are needed to implement these improvements. For example, gate-all-around transistors (GAA transistors) have been introduced to replace planar transistors. The structures of GAA transistors and the processes for manufacturing them are currently under development.

[0004] The fabrication of GAA transistors typically involves forming long strips (containing alternating semiconductor materials) and long gate stacks, followed by the formation of isolation regions to separate the long strips and gate stacks into shorter sections. These shorter sections can then be used to form the channel layers and gate stacks of the GAA transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. Figures 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 114, 11B, 12A, 12B, 13A, 13B, 14A, 14B and 15-20 show views of intermediate stages in the formation of gate all-around transistors (GAA transistors) according to some embodiments. Fig. Figure 21 is a schematic view of a distribution profile of carbon (and / or nitrogen) according to some embodiments. Fig. Figure 22 shows a process flow for forming GAA transistors according to some embodiments. Fig. Figure 23 shows a process flow for forming a gate isolation region according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not to be understood as limiting. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not automatically dictate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, spatially relative terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used in this document to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to include other orientations of the device during use or operation, in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or in other orientations), and the spatially relative terms used in this document may be interpreted accordingly.

[0008] Gate-all-around transistors (GAA transistors), cut-metal-gate isolation regions (CMG isolation regions), and the method for forming them are provided. According to some embodiments of the present disclosure, a CMG isolation region comprises a first layer formed from a dielectric layer with a lower k-value, and a dielectric layer with a higher k-value on top of the lower k-value dielectric layer. The lower k-value dielectric layer can be formed from a low-k dielectric material (with a dielectric constant (k-value) smaller than that of silicon oxide). The formation of the CMG isolation can be carried out by selecting suitable precursors and adjusting RF parameters.

[0009] In the illustrated embodiments, the formation of GAA transistors is used as an example to explain the principle of the present disclosure. Other types of transistors, such as fin field-effect transistors (FinFETs), bifurcated-leaf transistors, complementary field-effect transistors (CFETs), or the like, may also apply to the principle of the present disclosure. Embodiments discussed herein are intended to serve as examples to enable making or using the subject matter of this disclosure, and those of ordinary skill in the art will readily appreciate modifications that may be made without departing from the intended scope of various embodiments. Like reference numerals are used throughout the views and illustrative embodiments to identify like elements.Although some procedural execution methods are discussed as being carried out in a specific order, other procedural execution methods can be carried out in any logical order.

[0010] The Fig. Figures 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B and 15-20 show views of intermediate stages in the formation of GAA transistors according to some embodiments of the present disclosure. Furthermore, the corresponding processes are shown in the Fig. The process flow shown in section 22 is schematically illustrated.

[0011] On Fig. Figure 1 shows a perspective view of a wafer 10. The wafer 10 has a multilayer structure comprising a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate (SiGe substrate), or the like, while other substrates and / or structures such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium-on-insulator, or the like could be used. The substrate 20 may be doped as a p-type semiconductor, although in other embodiments it may be doped as an n-type semiconductor.

[0012] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding process is described in the Fig. 22 as process 202. According to some embodiments, the multilayer stack 22 includes first layers 22A formed from a first semiconductor material and second layers 22B formed from a second semiconductor material different from the first semiconductor material.

[0013] According to some embodiments, the first semiconductor material of a first layer 22A is formed from or contains SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. According to some embodiments, the first layers 22A (for example, SiGe) are deposited by epitaxial growth, and the corresponding deposition method may be vapor deposition (VDE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure atomic layer deposition (LPCVD), atomic layer deposition (ALD), ultra-high vacuum atomic vapor deposition (UHVCVD), reduced-pressure atomic layer deposition (RPCVD), or the like. According to some embodiments, the first layer 22A is formed with a first thickness in the range of about 30 Å to about 300 Å. However, any suitable thickness that is still within the scope of protection of the embodiments may be used.

[0014] Once the first layer 22A has been deposited on the substrate 20, a second layer 22B is deposited on top of the first layer 22A. According to some embodiments, the second layers 22B are formed from or contain a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon germanium, the second layer 22B can be formed from silicon, or vice versa. It is understood that any suitable combination of materials can be used for the first layers 22A and the second layers 22B.

[0015] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition process similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a thickness different from the first layer 22A. For example, according to some embodiments, the first layer 22A has a thickness in the range between about 4 nm and 7 nm, while the second layer 22B has a thickness in the range between about 8 nm and 12 nm.

[0016] Once the second layer 22B has formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until a desired top layer of the multilayer stack 22 has been formed. According to some embodiments, the first layers 22A have the same or a similar thickness, and the second layers 22B have the same or a similar thickness. The first layers 22A may also have the same thickness as, or a different thickness than, that of the second layers 22B. According to some embodiments, the first layers 22A are removed in subsequent processes and are alternatively referred to throughout this description as sacrificial layers 22A. According to alternative embodiments, the second layers 22B are sacrificial layers and are removed in subsequent processes.

[0017] According to some embodiments, pad oxide layer(s) and hard mask layer(s) (not shown) may be present over multilayer stack 22. These layers are patterned and used for subsequent patterning of multilayer stack 22.

[0018] On Fig. 2, the multilayer stack 22 and a portion of the underlying substrate 20 are patterned in (an) etching process(es) such that trenches 23 are formed. The corresponding process is described in the Fig. The process flow 200 shown in Figure 22 is represented as process 204. The trenches 23 extend into the substrate 20. The remaining sections of the multilayer stacks are subsequently referred to as multilayer stacks 22'. Some sections of the substrate 20 remain beneath the multilayer stacks 22' and are subsequently referred to as substrate strips 20'. The multilayer stacks 22' have semiconductor layers 22A and 22B. Subsequently, the semiconductor layers 22A are alternatively referred to as sacrificial layers and the semiconductor layers 22B alternatively as nanostructures. The sections consisting of the multilayer stacks 22' and the underlying substrate strips 20' are collectively referred to as semiconductor strips 24.

[0019] In the embodiments described above, the GAA transistor structures can be structured by any suitable method. For example, the structures can be structured by one or more photolithography processes, including dual-structuring or multi-structuring processes. In general, dual-structuring or multi-structuring processes combine photolithography and self-aligning processes, which makes it possible to create structures with, for example, pitches smaller than what is otherwise achievable by a simple, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured by a photolithography process. Spacers are formed along the structured sacrificial layer by means of a self-aligning process.Then the sacrificial layer is removed, and the remaining spacers can then be used to structure the GAA structure.

[0020] Fig. Figure 3 shows the formation of isolation regions 26, which are also referred to as shallow trench isolation regions (STI regions) throughout the description. The corresponding process is described in the Fig. The process flow 200 shown in Figure 22 is represented as process 206. The STI regions 26 can contain a liner oxide (not shown), which can be a thermal oxide formed by the thermal oxidation of a surface layer of the substrate 20. The liner oxide can also be a deposited silicon oxide layer formed, for example, by ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, or the like. The STI regions 26 can also have a dielectric material over the liner oxide, the dielectric material being formed by flowable chemical vapor deposition (FCVD), spin deposition, HDPCVD, or the like.Then a planarization process such as a chemical-mechanical polishing process (CMP process) or a mechanical grinding process can be carried out to level the upper surface of the dielectric material, and the remaining sections of the dielectric material are the STI areas 26.

[0021] The STI regions 26 are then recessed such that the upper portions of the semiconductor stripes 24 protrude higher than the upper surfaces 26T of the remaining portions of the STI regions 26 to form protruding fins 28. The protruding fins 28 comprise the multilayer stacks 22' and the upper portions of the substrate stripes 20'. The recessing of the STI regions 26 may be performed by a dry etching process, using, for example, NF3 and NH3 as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, the recessing of the STI regions 26 is performed by a wet etching process. The etch chemistry may include, for example, HF.

[0022] On Fig. 4. With reference to this, dummy gate stacks 30 and gate spacers 38 are formed on the upper surfaces and side walls of the (projecting) fins 28. The corresponding process is described in the Fig. The process flow 200 shown in Figure 22 is represented as process 208. The dummy gate stacks 30 can have dummy gate dielectrics 32 and dummy gate electrodes 34 over the dummy gate dielectrics 32. The dummy gate dielectrics 32 can be formed by oxidizing the surface sections of the projecting fins 28 to form oxide layers or by depositing a dielectric layer such as a silicon oxide layer. The dummy gate electrodes 34 can be formed, for example, by using polysilicon or amorphous silicon, and other materials such as amorphous carbon can also be used.

[0023] Each of the dummy gate stacks 30 can also have one (or more) hard mask layer(s) 36 over the dummy gate electrode 34. The hard mask layers 36 can be made of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multilayers thereof. The dummy gate stacks 30 can cross one or more projecting fins 28 and the STI areas 26 between projecting fins 28. The dummy gate stacks 30 also have longitudinal directions perpendicular to the longitudinal directions of the projecting fins 28. The formation of the dummy gate stack 30 comprises forming a dummy gate dielectric layer, depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing one or more hard mask layers, and then structuring the formed layers by (a) structuring process(s).

[0024] Next, gate spacers 38 are formed on the side walls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacers 38 are formed from a dielectric material such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like, and can have a single-layer structure or a multi-layer structure having several dielectric layers. The formation process of the gate spacers 38 can include depositing one or more dielectric layers and then performing an anisotropic etching process on the dielectric layer(s). The remaining sections of the dielectric layer(s) are the gate spacers 38.

[0025] According to alternative embodiments, one or more layers of gate spacers 38 can be separated by the Fig. The processes shown in 19 are formed, and the resulting layer of gate spacers 38 contains the information relating to Fig. The material discussed in sections 19 to 21 is shown. For example, the Gate Spacers 38 can be made of or contain SiOCNH. The details of the forming processes are discussed in the following paragraphs.

[0026] Fig. 5A and Fig. 5B show the cross-sectional views of the Fig. 4 shown structure. Fig. 5A shows the reference cross section A1-A1 in Fig. 4, wherein this cross-section intersects the sections of the projecting fins 28 that are not covered by the gate stacks 30 and the gate spacers 38 and runs at right angles to the longitudinal direction of the gate. Fin spacers 38, which are arranged on the side walls of the projecting fins 28, are also shown. Fig. 5B shows the reference cross section BB in Fig. 4, wherein this reference cross-section runs parallel to the longitudinal directions of the projecting fins 28.

[0027] On Fig. 6A and Fig. 6B Referring to this, the sections of the projecting fins 28 that are not directly beneath the dummy gate stacks 30 and the gate spacers 38 are deepened by an etching process to form recesses 42. The corresponding process is described in the Fig. The process flow 200 shown in Figure 22 is represented as process 210. For example, a dry etching process can be carried out using C2F6, CF4, SO2, the mixture of HBr, Cl2 and O2, the mixture of HBr, Cl2, O2 and CH2F2, or the like, to etch the multilayer semiconductor stacks 22' and the underlying substrate strips 20'. The bottoms of the wells 42 are at least level with the bottoms of the multilayer semiconductor stacks 22' or can be (as in Figure 22) Fig. 6B) deeper than these. The etching can be anisotropic, so that the side walls of the multilayer semiconductor stacks 22' facing the depressions 42 are perpendicular and straight, as in Fig. 6B is shown.

[0028] On Fig. 7A and Fig. 7B Referring to this, the sacrificial semiconductor layers 22A are laterally recessed to form lateral depressions 41 that are set back from the edges of the respective overlying and underlying nanostructures 22B. The corresponding process is described in the Fig. 22 as process 212. The lateral recessing of the sacrificial semiconductor layers 22A may be accomplished by a wet etch process that utilizes an etchant that is more selective to the material (e.g., silicon germanium (SiGe)) of the sacrificial semiconductor layers 22A than to the material (e.g., silicon (Si)) of the nanostructures 22B and the substrate 20. For example, in an embodiment where the sacrificial semiconductor layers 22A are formed of silicon germanium and the nanostructures 22B are formed of silicon, the wet etch process may be performed using an etchant such as hydrochloric acid (HCl). The wet etch process may be performed using a dipping process, a spraying process, a spin-on process, or the like.

[0029] According to alternative embodiments, the lateral deepening of the sacrificial semiconductor layers 22A is carried out by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0030] On Fig. 8A and Fig. Referring to Figure 8B, inner spacers 44 are formed. The corresponding process is described in the Fig. The process sequence 200 shown in Figure 22 is represented as process 214. According to some embodiments, the formation of the inner spacers 44 comprises the deposition of a conformal dielectric layer extending into the lateral recesses 41 ( Fig. 7B). Next, an etching process (also called a spacer trimming process) is carried out to trim the sections of the spacer layer outside the lateral recesses 41 and to leave the sections of the spacer layer inside the lateral recesses 41. The remaining sections of the spacer layer are referred to as inner spacers 44.

[0031] Fig. 9A and Fig. Figure 9B shows the cross-sectional views and a perspective view of the formation of source / drain regions 48 in the depressions 42 by means of epitaxy. The corresponding process is described in the Fig. The process flow 200 shown in Figure 22 is represented as process 216. The term source / drain region(s) can refer to a source or a drain, individually or collectively, depending on the context. According to some embodiments, the source / drain regions 48 can apply voltage to the nanostructures 22B, which are used as channels for the corresponding GAA transistors, thereby improving performance.

[0032] According to some embodiments, the corresponding transistor is of the n-type, and epitaxial source / drain regions 48 are accordingly formed as n-type by doping with an n-type dopant. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown to form epitaxial source / drain regions 48. According to alternative embodiments, the corresponding transistor is of the p-type, and epitaxial source / drain regions 48 are accordingly formed as p-type by doping with a p-type dopant. For example, silicon boron (SiB), silicon germanium boron (SiGeB), or the like can be grown to form epitaxial source / drain regions 48. After the depressions 42 have been filled with epitaxial areas 48, the further epitaxial growth of the epitaxial areas 48 causes the epitaxial areas 48 to expand horizontally, and facets can form.Further growth of the epitaxial areas 48 can also cause adjacent epitaxial areas 48 to merge, resulting in voids 49 (. Fig. 10C).

[0033] Following the epitaxy process, an n-contamination or a p-contamination can further be implanted into the epitaxy regions 48 to form source and drain regions, which are also designated by the reference numeral 48. According to alternative embodiments of the present disclosure, the implantation process is omitted if epitaxy regions 48 are doped in situ with the n-contamination or the p-contamination during epitaxy, and the epitaxy regions 48 are also source / drain regions.

[0034] Fig. 10A and Fig. Figure 10B shows cross-sectional views of the structure after formation of a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. The corresponding process is described in Fig. 22 as process 218. The CESL 50 may be formed from silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed by CVD, ALD, or the like. The ILD 52 may include a dielectric material formed, for example, by FCVD, spin-on deposition, CVD, or any other suitable deposition method. The ILD 52 may be formed from an oxygen-containing dielectric material, which may be a silicon oxide-based material prepared using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0035] The CESL 50 and the ILD 52 are planarized by a planarization process such as a CMP process or a mechanical grinding process. The corresponding process is described in the Fig. The process flow 200 shown in Figure 22 is represented as process 220. According to some embodiments, the planarization process can remove the hard masks 36 to expose the dummy gate electrodes 34, as shown in Figure 22. Fig. Figure 10A is shown. According to alternative embodiments, the planarization process can expose the hard masks 36 and is stopped there. According to some embodiments, after the planarization process, the upper surfaces of the dummy gate electrodes 34 (or hard masks 36), the gate spacer 38, and the ILD 52 are level within process variations.

[0036] Next, the dummy gate electrodes 34 and the dummy gate dielectrics 32 (and any remaining hard masks 36) are removed in one or more etching processes, so that depressions 58 are formed, as shown in Fig. 11A and Fig. 11B. The corresponding process is shown in the Fig. The process sequence 200 shown in Figure 22 is represented as process 222. According to some embodiments, the dummy gate electrodes 34 and the dummy gate dielectrics 32 are removed by an anisotropic dry etching process. For example, the etching process can be carried out using reaction gas(es) that selectively etches the dummy gate electrodes 34 and the dummy gate dielectrics 32 faster than the ILD 52. Each well 58 exposes and / or lies above sections of the multilayer stacks 22' that will form the future channel regions in subsequently completed transistors.

[0037] Then the sacrificial layers 22A are removed to enlarge the depressions 58 between the nanostructures 22B. The corresponding process is described in the Fig. The process flow 200 shown in Figure 22 is represented as process 224. The sacrificial layers 22A can be removed by performing an isotropic etching process, such as a wet etching process, using etchants that are selective for the materials of the sacrificial layers 22A, while the nanostructures 22B, the substrate 20, and the STI regions 26 remain relatively unetched compared to the sacrificial layers 22A. According to some embodiments, where the sacrificial layers 22A contain, for example, SiGe and the nanostructures 22B contain, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the sacrificial layers 22A.

[0038] On Fig. 12A and Fig. Referring to 12B, gate dielectrics 62 and gate electrodes 68 are formed and thus constitute replacement gate stacks 70. The corresponding process is described in the Fig. 22 as process 226. According to some embodiments, each gate dielectric 62 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer may be formed of silicon oxide or may include silicon oxide, which may be deposited by a conformal deposition process such as ALD or CVD, or by an oxidation process. According to some embodiments, the high-k dielectric layers include one or more dielectric layers. For example, the high-k dielectric layer(s) may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0039] Gate electrodes 68 are also formed. During formation, conductive layers are first formed on the high-k dielectric layer, and the remaining sections of the wells 58 are filled. The gate electrodes 68 can contain a metal-containing material such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multilayers thereof. For example, the gate electrodes 68 can have any number of layers, any number of exit working layers, and optionally a filler material. The gate dielectrics 62 and the gate electrodes 68 also fill the spaces between adjacent nanostructures 22B and the spaces between the lowest nanostructures 22B and the underlying substrate strips 20'.After the wells 58 are filled, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove the excess sections of the gate dielectrics and the material of the gate electrodes 68, the excess sections being above the upper surfaces of the ILD 52. The gate electrodes 68 and the gate dielectrics 62 are collectively referred to as the gate stack 70 of the resulting transistors.

[0040] In the Fig. 13A and Fig. In the processes shown in Figure 13B, a gate isolation region 94, also referred to as the cut-metal gate region (CMG region), is formed to separate (cut) the gate stack 70. In this way, the gate stack 70 is separated into two sections 70A and 70B, which are electrically isolated from each other and are collectively referred to as the gate stack 70. Details of the formation of the gate isolation region 94 are given with reference to Figure 13B. Fig. 15-20 discussed in detail. The corresponding process is described in the Fig. The process flow shown in section 22 is represented as process 228. The corresponding process is also shown in detail as process flow 300 in Fig. 23 shown.

[0041] Furthermore, Fig. 13A and Fig. Referring to Figure 13B, the gate stacks 70 are recessed so that a recess (occupied by the gate isolation region 94) is formed directly above the gate stacks 70 and between opposing portions of the gate spacers 38. A gate mask 74 comprising one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like is filled into each of the recesses, followed by a planarization process to remove excess portions of the dielectric material extending beyond the ILD 52.

[0042] As further shown by Fig. 13A and Fig. 13B, the ILD 76 is deposited over the ILD 52 and over the gate masks 74. The corresponding process is shown in Fig. The process flow shown in Figure 22 is represented as process 230. An etch stop layer (not shown) may or may not be deposited prior to the formation of the ILD 76. According to some embodiments, the ILD 76 is formed by FCVD, CVD, PECVD, or the like. The ILD 76 is formed from a dielectric material, which may be selected from silicon dioxide, PSG, BSG, BPSG, USG, or the like.

[0043] In Fig. 14A and Fig. 14B, the ILD 76, the ILD 52, the CESL 50, and the gate masks 74 are etched to form depressions (occupied by contact plugs 80A and 80B) that expose surfaces of the source / drain regions 48 and / or the gate stack 70. The depressions can be formed by etching using an anisotropic etching process such as RIE, NBE, or the like. Although Fig. Figure 14B shows that the contact plugs 80A and 80B are located in the same cross-section; however, in different embodiments, the contact plugs 80A and 80B may be located in different cross-sections, which reduces the risk of short-circuiting with each other.

[0044] After the depressions have been formed, 48 silicide zones (78) are formed above the source / drain areas. The corresponding process is described in the Fig. The process flow 200 shown in Figure 22 is represented as process 232. Then, the contact plugs 80B are formed over the silicide areas 78. In addition, the contacts 80A (which can also be referred to as gate contact plugs) are formed in the recesses and are located over and in contact with the gate electrodes 68. The corresponding process is shown in Figure 22. Fig. The process sequence 200 shown in Figure 22 is represented as process 234. Thus, transistor 82 was formed.

[0045] Fig. Figures 15 to 20 show the formation of the gate isolation region 94 according to some embodiments. The corresponding processes are described in process flow 300. Fig. 23 shown. Fig. Figure 15 shows a cross-sectional view of an intermediate structure, which is also found in Fig. 12A is shown and in which the gate stack 70 has been formed and has the gate dielectrics 62 and the gate electrode 68.

[0046] According to some embodiments, the hard mask layer 88 is deposited and can have a multilayer structure comprising several layers. The corresponding process is described in the Fig. 23 as process 302. According to some embodiments, the hard mask layers 88 include a silicon nitride layer 88A, a silicon layer 88B, and a silicon nitride layer 88C. According to alternative embodiments, a single-layer hard mask 88 is used, which may be formed from or include silicon nitride.

[0047] Then an etching mask 90 is formed, as in Fig. 16 is shown. The corresponding process is described in the Fig. The process flow 300 shown in Figure 23 is represented as process 304. The etching mask 90 can also have a single-layer structure (which may include a photoresist) or a two-layer structure, which includes a bottom antireflective coating (BARC) and a photoresist. Alternatively, the etching mask 90 can have a triple layer, which includes a bottom layer, a middle layer above the bottom layer, and a top layer, which may be a textured photoresist. A groove 92 is formed in the etching mask 90.

[0048] Next, the etching mask 90 is used to etch the mask layers 88 so that the trench 92 extends into the hard mask layers 88. The corresponding process is described in the Fig. 23 is shown as process 306. The resulting structure is shown in Fig. 17. According to some embodiments, the etching process comprises a main etching process followed by an over-etching process. Depending on the materials of the mask layers 88, the main etching process may be performed using process gases selected from CH2F2, CF4, O2, Ar, and combinations thereof. The over-etching process may be performed using process gases selected from CH3F, O2, Ar, and combinations thereof. The etching may be anisotropic. According to some embodiments, the trench 92 extends to the top surface of the hard mask 88A. After the trench 92 is formed in the hard mask layers 88, the etch mask 90 may be removed.

[0049] Next, as in Fig. 17, the replacement gate stack 70 is etched. The corresponding process is described in the Fig. The process flow 300 shown in Figure 23 is represented as process 308. The etching of the replacement gate stack 70 is anisotropic. According to some embodiments, the etching is carried out until the STI area 26 is exposed. The trench 92 may extend into the STI area 26. After the etching process, the hard mask layers 88 may (or may not) be removed. The trench 92 may have a width in the range of approximately 10 nm to approximately 30 nm and a depth in the range of approximately 120 nm to approximately 200 nm. Thus, the gate stack 70 was separated into the gate stacks 70A and 70B.

[0050] In a subsequent process, dielectric layers 94 (comprising dielectric layer 94A and dielectric layer 94B) are deposited, as shown in Fig. 18 and Fig. 19 is shown. The dielectric layers 94 have some sections extending into the trenches 92 to form isolation areas and some horizontal sections above the gate stack 70.

[0051] On Fig. 18 With reference to this, the dielectric layer 94A is deposited. The corresponding process is described in the Fig. The process sequence 300 shown in Figure 23 is represented as process 310. According to some embodiments, the dielectric layer 94A has a silicon-containing dielectric material, which is designated as SiC. x O y N z can be represented. The value x can be less than approximately 1, the value y can be less than approximately 2, and the value z can be less than approximately 3, with these values ​​being outside the ranges mentioned above. According to some embodiments, the dielectric layer 94A contains SiCON, SiCN, SiON, SiCO, or the like.

[0052] The dielectric layer 94A can have a first dielectric constant (k-value) that is relatively low compared to that of the subsequently deposited dielectric layer 94B. According to some embodiments, the dielectric layer 94A has a k-value less than about 4.0, which may be in the range between about 3.0 and about 4.0. Thus, according to some embodiments, the dielectric layer 94A can be a low-k dielectric layer, with the corresponding k-value being less than 3.8 (the k-value of silicon oxide). The dielectric layer 94A can be porous, resulting in a low k-value.

[0053] According to some embodiments, the precursors for forming the dielectric layer 94A may comprise aminosilane or the like. The deposition method may include ALD, plasma-enhanced ALD (PEALD), CVD, plasma-enhanced CVD (PECVD), or the like. The chemical formula of the aminosilane may be C9H 23The aminosilane, which differs from the precursors otherwise used, such as silane, disilane, dichlorosilane (DCS, SiH2Cl2) or the like, contains carbon (and nitrogen), which can contribute to the reduction of the resulting dielectric layer 94A.

[0054] The use of aminosilane as a precursor can advantageously reduce the k-value of the resulting dielectric layer 94A. However, the aminosilane can also have the disadvantage of causing the dielectric layer 94A to extend thinly in the trench 92 and to be unable to cover the side walls of the gate stack 70. According to some embodiments, the deposition of the dielectric layer 94A can be carried out by generating plasma. Experimental results have shown that when plasma is generated using N2, NH3, and Ar, as in the embodiments of the present disclosure, the resulting dielectric layer 94A can extend deeper into the trench 92.

[0055] According to some embodiments, the reduction of the dielectric layer 94A can also be achieved by adjusting the process conditions. For example, the RF power for generating the plasma can be implemented with on-off cycles, which can have a duty cycle in the range between about 0.1 seconds and about 15 seconds. The flow rate of N2 can be less than about 6 slm. The flow rate of NH3 can be less than about 6 slm. The flow rate of Ar can be less than about 1.5 slm. The wafer temperature can be in the range between about 200°C and about 400°C.

[0056] By using aminosilane, N₂, NH₃, and Ar as precursors and adjusting the process conditions, the resulting dielectric layer 94A can exhibit a silicon atomic percentage in the range of approximately 20% to approximately 50%, an oxygen atomic percentage in the range of approximately 5% to approximately 35%, a carbon atomic percentage of less than approximately 25%, and a nitrogen atomic percentage of less than approximately 50%. The porosity of the dielectric layer 94A can be greater than approximately 15% and range from approximately 15% to approximately 45%. The k-value of the dielectric layer 94A is thus reduced.

[0057] According to some embodiments, by adjusting the process conditions, the dielectric layer 94A has a lower end that is higher than the lower end of the trench 92. Accordingly, the upper part of the trench 92 has the dielectric layer 94A lining the side walls of the gate stack 70 (and possibly the STI region 26), while the lower part of the trench 92 has no lining with the dielectric layer 94A. Consequently, some surfaces of the STI region 26 facing the trench 92 may be exposed.

[0058] When the dielectric layer 94A extends partially into the trench 92, the dielectric layer 94A completely covers all exposed sidewalls of the gate stacks 70A and 70B, so that the dielectric layer 94A, which has a low k value, can serve to reduce the parasitic capacitance in the resulting structure, for example, the parasitic capacitance between the adjacent gate stacks 70A and 70B. According to some embodiments, the lower ends of the dielectric layer 94A are substantially flush with, or slightly lower than, the interfaces between the STI region 26 and the overlying gate stack 70, and thus, some portions of the sidewalls of the STI region 26 are exposed to the trench 92.By adjusting the process conditions, the dielectric layer 94A is deposited better on the gate stacks 70A and 70B than on the STI region 26, and thus the lower ends of the dielectric layer 94A may be abrupt, as shown in FIG. Fig. 18 and Fig. 19 is shown.

[0059] According to alternative embodiments, due to its reduced ability to extend deeply into the trench 92, the dielectric layer 94A may have lower portions that have a gradually decreasing thickness as it extends deeper into the trench 92. Lines 94A-S1 represent a possible sidewall of the dielectric layer 94A, the lower end of which is located between the upper surface of the STI region 26 and the lower end of the trench 92. The lower portion of the dielectric layer 94A, including sidewall 94A-S1, also has a gradually decreasing thickness as it extends deeper into the trench 92. Lines 94A-S2 represent an alternative profile of the dielectric layer 94A that completely covers all sidewalls of the STI region 26 and the gate stacks 70 exposed to the trench 92.However, the lower section of dielectric layer 94A has a smaller thickness than the respective upper sections.

[0060] On Fig. 19 With reference to this, the dielectric layer 94B is deposited, for example by ALD, PEALD, CVD, PECVD or the like. The corresponding process is described in the Fig. 23 as process 312. According to some embodiments, dielectric layer 94B has a higher k-value and a higher density than dielectric layer 94A. For example, dielectric layer 94B may be a high-k dielectric layer having a k-value greater than about 6, and possibly greater than about 7. The k-value difference (k94B - k94A) may be greater than about 2 or greater than about 4, and may range between about 2 and about 5, where k-values ​​k94A and k94B are the k-values ​​of dielectric layers 94A and 94B, respectively.

[0061] The dielectric layer 94B can also be formed from or contain a silicon-containing dielectric material. According to some embodiments, the dielectric layer 94B can be formed by using a silicon-containing precursor, which may be free of carbon and nitrogen. For example, the silicon-containing precursor may contain silane, disilane, dichlorosilane, or the like, or a combination thereof. Using these precursors makes it easier to fill the resulting dielectric layer 94B to the bottom of the trench 92. According to some embodiments, the dielectric layer 94B may contain silicon dioxide (SiO2), SiN, or the like. Other carbon- and / or nitrogen-containing precursors, such as CO2, NO, NO2, N2, NH3, H2, or the like, may also participate (or not) in the formation, so that the resulting dielectric layer 94B may also contain carbon and / or nitrogen.Accordingly, the dielectric layer 94B can also contain SiN, SiO, SiCON, SiCN, SiON, SiCO or the like, or combinations thereof.

[0062] According to some embodiments, dielectric layers 94A and 94B contain different elements, wherein, after deposition, at least one of the elements (such as C and / or N) in one of dielectric layers 94A and 94B is not present in the other. According to alternative embodiments, dielectric layers 94A and 94B contain the same elements and may or may not have the same composition. Throughout the specification, when two layers are said to have the same composition, it means that the two layers contain the same elements and the percentages of the corresponding elements are the same in both layers.However, if it is stated that two layers have different compositions, this means that at least one of the two layers either contains an element that is not present in the other layer, or both layers contain the same elements, but the percentage proportions of the elements in the two layers are different.

[0063] According to some embodiments, dielectric layers 94A and 94B comprise the same elements but different compositions. For example, dielectric layers 94A and 94B may each comprise SiOCN, with the carbon atomic percentage of dielectric layer 94A being greater (e.g., two times or greater) than that in dielectric layer 94B. According to alternative embodiments, dielectric layer 94A contains carbon as deposited, while dielectric layer 94B is free of carbon after deposition.

[0064] According to some embodiments, the dielectric layers 94A and 94B have the same composition with the same elements and the same (or nearly the same, for example, with less than 20 percent variation). For example, both dielectric layers 94A and 94B may contain SiCON. However, the k-value k94A of dielectric layer 94A is lower than the k-value k94B of dielectric layer 94B. The lower k-value k94A can be achieved by using different precursors, different deposition methods, and / or different process conditions, so that the porosity of dielectric layer 94A is greater than the porosity of dielectric layer 94B, even if the compositions of dielectric layers 94A and 94B are the same or very similar.For example, the porosity P94A of dielectric layer 94A can range from approximately 20 percent to approximately 40 percent, and the porosity P94B of dielectric layer 94B can be less than approximately 10 percent or 5 percent. The porosity difference (P94A - P94B) can be greater than approximately 10 percent or greater than approximately 20 percent and range from 10 percent to approximately 40 percent.

[0065] According to some embodiments, the dielectric layer 94B completely fills the remaining trench 92 not filled by the dielectric layer 94A. Accordingly, no void is formed in the dielectric layer 94B. According to alternative embodiments, due to the greater thickness of the dielectric layer 94A, a void 96 is formed in the upper sections of the trench 92 compared to the lower sections. The void 96 is shown with a dashed line to indicate whether or not it may be formed. Since the dielectric layer 94A can completely cover the side walls of the gate stacks 70 without covering the lower sections, the void 96 can be formed deep within the trench 92. For example, the upper end of the void 96 can be lower than, or at the same level as, the interface between the STI area 26 and the overlying gate stacks 70A and 70B.

[0066] After the deposition of the dielectric layers 94A and 94B, a planarization process such as a CMP process or a mechanical grinding process is carried out. The corresponding process is described in the Fig. The process sequence 300 shown in Figure 23 is represented as process 314. The planarization process can be stopped at the upper surfaces of the gate stack 70. The remaining sections of the dielectric layers 94A and 94B are subsequently referred to collectively as the gate insulation region 94. After the process, which is described in Fig. 20, the remaining processes that are described in Fig. 13A, Fig. 13B, Fig. 14A and Fig. 14B are performed to complete the formation of the GAA transistors 82.

[0067] According to some embodiments, dielectric layer 94A contains carbon, while dielectric layer 94B is carbon-free or has a lower atomic percentage of carbon than dielectric layer 94A. Accordingly, the highest atomic percentage of carbon (and / or nitrogen, if dielectric layer 94B is also free of carbon and / or nitrogen after deposition) can be present in dielectric layer 94A. Fig. Figure 21 is a schematic view of a profile of carbon (and / or nitrogen) according to some embodiments. The x-axis represents the positions corresponding to arrow 98 in Fig.20. The Y-axis represents the atomic percentage of carbon (and / or nitrogen). It is shown that the percentage of carbon peaks in two sections of dielectric layer 94A, and this percentage is reduced in gate stacks 70A and 70B and dielectric layer 94B. The dashed line represents an alternative embodiment in which dielectric layer 94B does not include carbon (and / or nitrogen) and carbon (and / or nitrogen) cannot diffuse to the center of dielectric layer 94B.

[0068] The embodiments of the present disclosure have several advantageous features. When forming a gate isolation region (a CMG region) by forming a first dielectric layer to fill the trench and having a lower k value, the first dielectric layer has a greater effect on reducing parasitic capacitance. The second dielectric layer has a higher k value, is denser, and has better leakage current reduction capability. The difference in the compositions of the two dielectric layers of the gate isolation region can be observed, for example, using transmission electron microscopy (TEM).

[0069] According to some embodiments of the present disclosure, a method comprises forming a gate stack; etching the gate stack to form a trench penetrating the gate stack, wherein a dielectric insulating region located beneath the gate stack is exposed towards the trench and a first section and a second section of the gate stack are separated by the trench; performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first section and the second section of the gate stack, wherein the first dielectric layer has a first dielectric constant;and carrying out a second deposition process to form a second dielectric layer on top of the first dielectric layer, wherein the second dielectric layer fills the trench and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

[0070] In one embodiment, the first dielectric layer is deposited using aminosilane as the first precursor. In another embodiment, the second dielectric layer is deposited using a second precursor selected from the group consisting of silane, disilane, dichlorosilane, and combinations thereof, wherein the first and second dielectric layers have the same elements. In another embodiment, the first and second dielectric layers have the same composition. In another embodiment, the first dielectric layer has a higher porosity than the second dielectric layer. In yet another embodiment, the first dielectric layer is deposited using N₂, NH₃, and Ar as additional process gases.

[0071] In one embodiment, the method further comprises forming a projecting fin, wherein the gate stack is formed on the projecting fin; etching the projecting fin to form source / drain depressions; and forming source and drain regions in the source / drain depressions. In another embodiment, the method further comprises performing a planarization process to remove portions of the first dielectric layer and the second dielectric layer that are higher than an upper surface of the gate stack in order to form a gate isolation region. In one embodiment, the first dielectric layer has a lower surface that is higher than a lower end of the trench. In another embodiment, the second dielectric layer is in physical contact with the dielectric isolation region.

[0072] According to some embodiments of the present disclosure, a structure comprises a semiconductor substrate having a bulk section; a dielectric isolation region above the bulk section of the semiconductor substrate; a semiconductor region adjacent to the dielectric isolation region, wherein the semiconductor region has a section that is higher than the dielectric isolation region; a first gate stack and a second gate stack above the dielectric isolation region; and a gate isolation region between and in physical contact with the first gate stack and the second gate stack, wherein the gate isolation region extends from an upper surface level of the first gate stack to a level below a lower surface level of the first gate stack, and wherein the gate isolation region comprises a first dielectric layer containing a low-k dielectric material;and a second dielectric layer containing a high-k dielectric material, the first dielectric layer having a portion between and in contact with the second dielectric layer and the first gate stack;

[0073] In one embodiment, the first dielectric layer contains silicon and carbon. In another embodiment, the first dielectric layer contains SiOCN. In another embodiment, the first and second dielectric layers contain the same elements, and the first dielectric layer has a higher porosity than the second dielectric layer. In another embodiment, the first and second dielectric layers have the same composition. In another embodiment, part of the second dielectric layer is in physical contact with the dielectric insulating region.

[0074] According to some embodiments of the present disclosure, a structure comprises a first GAA transistor having a first gate stack; a second GAA transistor having a second gate stack; and a gate isolation region between and in contact with the first gate stack and the second gate stack, wherein the gate isolation region comprises a first dielectric layer containing SiOCN, wherein the first dielectric layer is in physical contact with the first gate stack and the second gate stack, and wherein the first dielectric layer has a first dielectric constant; and a second dielectric layer on top of the first dielectric layer, wherein the second dielectric layer has a second dielectric constant that is higher than the first dielectric constant.

[0075] In one embodiment, the first dielectric layer has lower sections that are thinner than upper sections, and the lower ends of the first dielectric layer are level with or lower than the lower surfaces of the first gate stack and the second gate stack. In another embodiment, the second dielectric layer also contains SiOCN, and the first dielectric layer has a higher porosity than the second dielectric layer. In yet another embodiment, the structure further comprises a dielectric isolation region that lies beneath and is in contact with the first and second gate stacks, wherein a lower section of the gate isolation region is within the dielectric isolation region, and wherein a lower section of the second dielectric layer is in physical contact with the dielectric isolation region.

[0076] The preceding description outlines features of several embodiments to enable those skilled in the art to better understand the aspects of this disclosure. Those skilled in the art should recognize that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same benefits as the embodiments presented in this document. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of protection of this disclosure and that they can make various changes, substitutions, and modifications therein without deviating from the nature and scope of protection of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 582,356

[0001]

Claims

[1] Method comprising: Forming a gate stack; Etching the gate stack to form a trench penetrating the gate stack, wherein a dielectric isolation region underlying the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench; Performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first portion and the second portion of the gate stack, the first dielectric layer having a first dielectric constant; and Performing a second deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer fills the trench and the second dielectric layer has a second dielectric constant greater than the first dielectric constant. [2] The method of claim 1, wherein the first dielectric layer is deposited by using aminosilane as the first precursor. [3] The method of claim 2, wherein the second dielectric layer is deposited using a second precursor selected from the group consisting of silane, disilane, dichlorosilane, and combinations thereof, and wherein the first dielectric layer and the second dielectric layer contain the same elements. [4] The method of claim 3, wherein the first dielectric layer and the second dielectric layer have a same composition. [5] The method of claim 4, wherein the first dielectric layer has a higher porosity than the second dielectric layer. [6] A method according to any one of claims 2 to 5, wherein the first dielectric layer is deposited by using N2, NH3 and Ar as additional process gases. [7] A method according to any one of claims 1 to 6, further comprising: forming a protruding fin, wherein the gate stack is formed on the protruding fin; Etching the protruding fin to form source / drain recesses; and Forming source and drain regions in the source / drain recesses. [8] The method of any one of claims 1 to 7, further comprising performing a planarization process to remove portions of the first dielectric layer and the second dielectric layer higher than a top surface of the gate stack to form a gate isolation region. [9] The method of any one of claims 1 to 8, wherein the first dielectric layer has a bottom surface higher than a bottom end of the trench. [10] The method of any one of claims 1 to 9, wherein the second dielectric layer is in physical contact with the dielectric isolation region. [11] Method comprising: Forming a dielectric isolation region over a bulk portion of a semiconductor substrate, wherein a semiconductor region is adjacent to the dielectric isolation region, and wherein the semiconductor region has a portion higher than the dielectric isolation region; Forming a replacement gate stack over the dielectric isolation region; Etching the replacement gate stack to form a first gate stack and a second gate stack; and Forming a gate isolation region between and in physical contact with the first gate stack and the second gate stack, wherein the gate isolation region extends from an upper surface level of the first gate stack to a level below a lower surface level of the first gate stack, and wherein forming the gate isolation region comprises: depositing a first dielectric layer containing a low-k dielectric material; and Depositing a second dielectric layer containing a high-k dielectric material, wherein the first dielectric layer has a portion between and in contact with the second dielectric layer and the first gate stack. [12] The method of claim 11, wherein depositing the first dielectric layer comprises depositing a silicon-and-carbon-containing dielectric layer. [13] The method of claim 12, wherein depositing the first dielectric layer comprises depositing SiOCN. [14] The method of any one of claims 11 to 13, wherein the first dielectric layer and the second dielectric layer are deposited as containing the same elements and the first dielectric layer has a higher porosity than the second dielectric layer. [15] The method of claim 14, wherein the first dielectric layer and the second dielectric layer are deposited having a same composition. [16] The method of any one of claims 11 to 15, wherein a portion of the second dielectric layer is in physical contact with the dielectric isolation region. [17] Structure comprising: a first gate all-around (GAA) transistor having a first gate stack; a second GAA transistor having a second gate stack; and a gate isolation region between and in contact with the first gate stack and the second gate stack, the gate isolation region comprising: a first dielectric layer comprising SiOCN, wherein the first dielectric layer is in physical contact with the first gate stack and the second gate stack, and wherein the first dielectric layer has a first dielectric constant; and a second dielectric layer on the first dielectric layer, the second dielectric layer having a second dielectric constant higher than the first dielectric constant. [18] The structure of claim 17, wherein the first dielectric layer has lower portions that are thinner than upper portions, and lower ends of the first dielectric layer are level with or lower than lower surfaces of the first gate stack and the second gate stack. [19] The structure of claim 17 or 18, wherein the second dielectric layer also contains SiOCN and the first dielectric layer has a higher porosity than the second dielectric layer. [20] The structure of any one of claims 17 to 19, further comprising a dielectric isolation region underlying and in contact with the first gate stack and the second gate stack, wherein a lower portion of the gate isolation region is in the dielectric isolation region, and wherein a lower portion of the second dielectric layer is in physical contact with the dielectric isolation region.

Images