BACK-END-OF-LINE STORAGE DEVICE
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2024-02-27
- Publication Date
- 2026-07-23
Abstract
Description
Reference to Related ApplicationThe present application claims priority to U.S. Provisional Patent Application Ser. No. 63 / 516,887, filed Aug. 1, 2023, and entitled "A Novel BEOL Compatible FeRAM NAND & FeRAM NOR Device and Method" ("New Comparable BEOL-FeRAM NAND and FeRAM NOR Device and Method"), which is incorporated herein by reference.BackgroundAs semiconductor technology advances, demands for higher storage capacity, faster processing systems, higher performance, and lower cost have increased. To meet these requirements, the semiconductor industry further reduces the dimensions of circuit elements such as memory devices. As the storage capacity increases and the number of circuit elements increases accordingly, the semiconductor manufacturing process becomes more and more complex.Brief Description of the DrawingsAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. FIG. 1 is a block-level diagram of a storage system, in accordance with some embodiments. FIG. 2 is a cross-sectional view of a semiconductor device using one or more elements of a memory system, in accordance with some embodiments. FIG. 3 is a cross-sectional view of a portion of a semiconductor device, in accordance with some embodiments. FIG. 4 is another cross-sectional view of a semiconductor device according to some embodiments. FIG. 5 is a circuit diagram of a portion of a memory array, in accordance with some embodiments. FIG. 6A is a top view layout diagram of a portion of a memory array, in accordance with some embodiments. FIG. 6B is an enlarged top view layout diagram of a portion of a memory array, in accordance with some embodiments. FIG. 7 is a cross-sectional view of a portion of a memory array, in accordance with some embodiments. FIG. 8 is another cross-sectional view of a portion of a memory array, in accordance with some embodiments. FIG. 9 is a circuit diagram of another portion of a memory array, in accordance with some embodiments. FIG. 10A is another top view layout diagram of a portion of a memory array, in accordance with some embodiments. FIG. 10B is another enlarged top view layout diagram of a portion of a memory array, in accordance with some embodiments. FIG. 11 is yet another cross-sectional view of a portion of a memory array, in accordance with some embodiments. FIG. 12 is an illustration of a method of fabricating a memory cell in a back end of line (BEOL) memory device area of a semiconductor device, in accordance with some embodiments.FIGS. 13 through 18 are partial cross-sectional views of a memory cell in a BEOL memory device portion of a semiconductor device at various stages of its fabrication process, in accordance with some embodiments.Detailed DescriptionThe following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed. Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper", and the like may be used herein to easily describe the relationship of an element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90° or in another orientation) and the spatially relative descriptors used herein interpreted accordingly.It should be noted that references in the specification to "one embodiment," "an example embodiment," "exemplary," etc., mean that the described embodiment may have a particular element, structure, or characteristic, but that not necessarily every embodiment must have the particular element, structure, or characteristic. Moreover, these phrases need not necessarily refer to the same embodiment. When a particular element, structure, or characteristic is described in connection with an embodiment, one skilled in the art will understand how to realize that element, structure, or characteristic in connection with other embodiments, whether it / they are explicitly described.It should be understood that the terminology or terminology used herein is for the purpose of description and not of limitation, and therefore the terminology or terminology of the present specification is intended to be interpreted by those skilled in the art in light of the principles.In some embodiments, the terms "about" and "substantially" may indicate a value of a given magnitude that varies within 5% of the value (e.g., +1%, ± 2%, ± 3%, ±.4%, ± 5% of the value). These values are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of the values interpreted by those skilled in the art in light of the principles used herein.As semiconductor technology advances, demands for higher storage capacity, faster processing systems, higher performance, and lower cost have increased. To meet these requirements, the semiconductor industry further reduces the dimensions of circuit elements such as memory devices. As memory capacity increases and the number of circuit elements increases accordingly, the semiconductor manufacturing process becomes more and more complex, the chip area for implementing memory devices presents a greater challenge.In the present disclosure, a semiconductor device including memory devices, e.g., FeRAM (ferroelectric random access memory) cells, in a BEOL region (e.g., interconnect structures disposed over a substrate of the semiconductor device) is described. The semiconductor device may include: a substrate; a first interconnect region disposed over the substrate; a second interconnect region disposed over the first interconnect region; and a third interconnect region disposed over the second interconnect region. The substrate may include electrical components, e.g., active devices, passive devices, or a combination thereof, fabricated thereon. The first interconnect region may include interconnect structures (e.g., metal line structures and metal via structures) for electrically connecting the electrical components to each other and to upper interconnect structures (e.g., interconnect structures in the second and third interconnect regions). The second interconnect region may include a memory device region and interconnect structures (e.g., metal line structures and metal via structures). The memory device region may include memory cells (e.g., FeRAM cells) electrically connected to the electrical components via the interconnect structures in the first interconnect region. Each of the ferroelectric memory cells may include a ferroelectric material (e.g., hafnium zirconium oxide) disposed on a top and side surfaces of a fin structure (e.g., made of indium gallium zinc oxide). Further, the third interconnect region may include interconnect structures (e.g., metal line structures and metal via structures).One of several benefits of implementing memory cells in the memory device area is that the BEOL area of the semiconductor device can be used to fabricate memory cells, such that the storage capacity in the semiconductor device increases. Another benefit of implementing memory cells in the BEOL area is that additional substrate area is available for implementing other electrical components to improve the functionality and performance of the semiconductor device.FIG. 1 is a block-level diagram of a storage system 100, in accordance with some embodiments. In some embodiments, the memory system 100 may include a row decoder 110, an input / output (I / O) circuit 120, a sense amplifier 130, a column decoder 140, and a memory array 150.The memory array 150 includes memory cells arranged in rows and columns accessed, for example, for read and write operations using a memory address. In some embodiments, the memory cells in memory array 150 may be FeRAM cells. Although the description below relates to a memory system having FeRAM cells, other types of systems and memory cells may be used to implement the embodiments described herein.Based on the memory address, row decoder 110 selects a row of memory cells for accessing (e.g., via word lines 112 o through 112 m), and column decoder 140 selects a column of memory cells for accessing (e.g., via bit lines 142 o through 142 n). An intersection of the selected row of memory cells and the selected column of memory cells corresponds to a selected memory cell in the accessible memory array 150. Sense amplifier 130 detects whether the selected memory cell is in a conductive or non-conductive state during a sample period corresponding to an on-state and an off-state, respectively, of the selected memory cell. The turn-on / turn-off state of the selected memory cell may correspond to either a number "0" or a number "1" with the I / O circuit 120 providing this digital representation of the state of the selected memory cell to an external circuit (not shown in FIG. 1). Further memory operations may be performed using row decoder 110, I / O circuit 120, sense amplifier 130, column decoder 140, and memory array 150. These other memory operations are also within the spirit and scope of the present disclosure.One of several challenges in the design of the memory system 100 is, among other things, to implement a memory array 150 with a higher storage capacity and therefore with a higher number of memory cells (e.g., FeRAM cells). For example, as system designs with higher functionality and performance become more complex, additional chip area is consumed to implement these complex designs, leaving only a limited chip area for additional memory cells to increase memory capacity. In the present disclosure, these challenges are addressed, among other things, by implementing a memory array 150 (e.g., the entire memory array or portions thereof) in a BEOL area (e.g., metal layers disposed over a substrate of a semiconductor device) of the chip design.FIG. 2 is a cross-sectional view of a semiconductor device 200 using one or more circuit elements of the memory system 100, in accordance with some embodiments. The semiconductor device 200 may include a substrate 210, a device region 220, and a BEOL region 230 in some embodiments.The substrate 210 may include a semiconductor material such as crystalline silicon (Si). In some embodiments, the substrate 210 may be: (I) an elemental semiconductor such as germanium (Ge); (II) a compound semiconductor such as silicon carbide (SiC), silicon arsenide (SiAs), gallium arsenide (GaAs), gallium phosphide (GaP), and / or a III-V semiconductor material; (III) an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium tin (GeSn), and / or aluminum gallium arsenide (AlGaAs); (IV) a semiconductor-on-insulator (SOI) structure; (V) a silicon germanium-on-insulator (SiGeOI) structure; (VI) a germanium-on-insulator (GeOI) structure; or (VII) a combination thereof. Alternatively, the substrate 210 may be made of an electrically non-conductive material such as glass or may be a sapphire wafer. In addition, the substrate 210 may be doped depending on design requirements (e.g., p- or n-substrate). In some embodiments, the substrate 210 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic).A device region 220 may be disposed on the substrate 210. In some embodiments, device area 220 may include electrical components, such as active devices, passive devices, or a combination thereof. Examples of active devices may be planar metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), gate-all-around transistors (GAA-FETs), and nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nanoribbon transistors). The device region 220 may include one or more of these different types of active devices that may be separated from each other using methods such as shallow trench isolation, deep trench isolation, local oxidation of silicon, other suitable isolation methods, or a combination thereof. Examples of passive devices may include resistors, capacitors, and inductors. The device area 220 may also include one or more of these different types of passive devices.In some embodiments, device area 220 may include one or more electrical components of storage system 100 of FIG. 1. For example, device portion 220 may include row decoder 110, I / O circuit 120, sense amplifier 130, and / or column decoder 140. In addition to the electrical components of the storage system 100, the device portion 220 may include other types of electrical components.In FIG. 2, a BEOL region 230 is disposed over the device region 220 (e.g., in the y-direction), which may include a first interconnect region 231, a second interconnect region 232, and a third interconnect region 236, in accordance with some embodiments. The first interconnect region 231 may include one or more interconnect structures, e.g., metal line structures and metal via structures, disposed in an interlayer dielectric structure (not shown in FIG. 2 ). The metal line structures and the metal via structures may include copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or other suitable conductive materials. The interlayer dielectric structure may include a dielectric material such as silicon oxide (SiO x), silicon hydroxide (SiOH), silicon oxynitride (SiON), silicon nitride (SiN x), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or a combination thereof. The interlayer dielectric structure may include a stack of dielectric layers to implement multiple layers of interconnect structures.The one or more interconnect structures in the first interconnect region 231 may be electrically connected to the electrical components in the device region 220. For example, the one or more interconnect structures in the first interconnect region 231 may be electrically connected to the active devices and / or the passive devices in the electrical components of the memory system 100 of FIG. 1 (e.g., the row decoder 110, the I / O circuit 120, the sense amplifier 130, and the column decoder 140) such that these electrical components may be electrically connected to each other and / or to upper interconnect structures (e.g., interconnect structures in the second interconnect region 232 and the third interconnect region 236).In FIG. 2, in accordance with some embodiments, the second interconnect region 232 is disposed over the first interconnect region 231 (e.g., in the y-direction) and may include a memory device region 233 and a metal via structure 234, both of which are disposed in an interlayer dielectric structure 235. Metal via structure 234 may electrically connect interconnect structures in interconnect region 231 to interconnect structures in interconnect region 236. Although not shown in FIG. 2, the second interconnect region 232 may also include metal line structures and other metal via structures. The metal line structures and the metal via structures (including metal via structure 234) may include Cu, Al, TiN, TaN, W, or other suitable conductive materials. The interlayer dielectric structure 235 may include a dielectric material such as SiO x, SiOH, SiON, SiN x, SiOC, SiOCN, or a combination thereof. The interlayer dielectric structure 235 may include a stack of dielectric layers to implement multiple layers of interconnect structures.In some embodiments, the memory device portion 233 may include one or more electrical components of the memory system 100 of FIG. 1, such as the memory array 150. One of several advantages of implementing the memory array 150 is that the BEOL region 230 may be used for manufacturing memory cells (e.g., FeRAM cells), thereby increasing the storage capacity in the semiconductor device 200. Another benefit of implementing the memory array 150 in the BEOL area is that an additional area in the device area 220 is available for implementing other electrical components to improve the functionality and performance of the semiconductor device 200.In FIG. 2, disposed over the second interconnect region 232 (e.g., in a y-direction) is the third interconnect region 236, which may include one or more interconnect structures disposed in an interlayer dielectric structure 238. The interconnect structures may include metal line structures 237 and metal via structures (not shown in FIG. 2 ). The metal line structures and the metal via structures may include Cu, Al, TiN, TaN, W, or other suitable conductive materials. The interconnect structures in the third interconnect region 236 may be electrically connected to the electrical components in the device region 220 via the metal via structure 234 (and other metal via structures not shown in FIG. 2 ) and the first interconnect region 231. The interlayer dielectric structure 238 may include a dielectric material such as SiO x, SiOH, SiON, SiN x, SiOC, SiOCN, or a combination thereof. The interlayer dielectric structure 238 may include a stack of dielectric layers to implement multiple layers of interconnect structures. Although three layers of metal line structures 237 are illustrated in the third interconnect region 236, the third interconnect region 236 may include more or less than three metal line structures depending on the design of the semiconductor device 200.FIG. 3 is a cross-sectional view of a portion 300 of the semiconductor device 200 in accordance with some embodiments. The portion 300 includes the substrate 210, the device region 220, and the first interconnect region 231. Although not shown in FIG. 3, the second interconnect region 232 and the third interconnect region 236 are disposed over the first interconnect region 231, as shown in FIG. 2.The device area 220 may include active devices 310 implemented in and / or on the substrate 210. The active devices 310 may include planar MOSFETs, FinFETs, GAA FETs, and / or nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nanoribbon transistors), in some embodiments. The active devices 310 may be separated from each other using methods such as shallow trench isolation, deep trench isolation, local oxidation of silicon, other suitable isolation methods, or a combination thereof. In some embodiments, the active devices 310 may represent one or more of the electrical components in the memory system 100 of FIG. 1 (e.g., the row decoder 110, the I / O circuit 120, the sense amplifier 130, and the column decoder 140). In some embodiments, the active devices 310 may represent one or more electrical components of the storage system 100, another system, or a combination of both systems. Although not shown in FIG. 3, the device portion 220 may also include passive devices (e.g., resistors, capacitors, and inductors) implemented in and / or on the substrate 210.In some embodiments, the first interconnect region 231 may include interconnect structures, e.g., metal line structures 320 and a metal via structure 234, disposed in an interlayer dielectric structure 321. The metal line structures 320 and the metal via structure 234 may be electrically connected to the active and / or passive devices in the device region 220 (e.g., the active devices 310) such that these electrical components may be electrically connected to each other and / or to upper interconnect structures (e.g., interconnect structures in the second interconnect region 232 and the third interconnect region 236, which are not shown in FIG. 3 ). Although not shown in FIG. 3, the first interconnect region 231 may include other metal via structures. The metal line structures and the metal via structures (including metal via structure 234) may include Cu, Al, TiN, TaN, W, or other suitable conductive materials. The interlayer dielectric structure 321 may include a dielectric material such as SiO x, SiOH, SiON, SiN x, SiOC, SiOCN, or a combination thereof. The interlayer dielectric structure 321 may include a stack of dielectric layers to implement multiple layers of interconnect structures.FIG. 4 is another cross-sectional view of a portion 400 of the semiconductor device 200 in accordance with some embodiments. Although not shown in FIG. 4, the second interconnect region 232 and the third interconnect region 236 are disposed over the first interconnect region 231, as shown in FIG. 2.The portion 400 includes the substrate 210, the device region 220, and the first interconnect region 231. Device area 220 may include a back-side interconnect area 410 and a device area 420, in some embodiments. In some embodiments, the back-side interconnect region 410 is disposed below the device region 220 (e.g., in the y-direction). The back side interconnect region 410 may include interconnect structures (e.g., as part of a network of redistribution layers of interconnect structures) disposed in an interlayer dielectric structure 417 and configured to provide a supply voltage for electrical components in the device region 420. The interlayer dielectric structure 417 may include a dielectric material such as SiO x, SiOH, SiON, SiN x, SiOC, SiOCN, or a combination thereof. The interlayer dielectric structure 417 may include a stack of dielectric layers to implement multiple layers of interconnect structures. In addition, the interconnect structures may include metal line structures 413, 415, and 416 and metal via structures 412 and 414 that are electrically connected to each other and to a voltage source to provide the supply voltage to device region 420. Metal line structures 413, 415, and 416 and metal via structures 412 and 414 may include Cu, Al, TiN, TaN, W, or other suitable conductive materials.Device region 420 may include active devices 422 disposed over substrate 210 (e.g., in the y-direction), in accordance with some embodiments. As shown in FIG. 4, in some embodiments, the active devices 422 may be GAA FETs electrically connected to the back-side interconnect region 410 and the first interconnect region 231 through metal contact structures 421, a metal contact structure 423, and metal line structures 411. In some embodiments, the active devices 422 may receive a supply voltage from the interconnect structures in the back-side interconnect region 410 via the metal contact structures 421 and the metal line structures 411. Additionally, in some embodiments, the active devices 422 may receive a voltage from the interconnect structures in the first interconnect region 231 via the metal contact structure 423. The metal contact structures 421 and 423 and the metal line structures 411 may include Cu, Al, TiN, TaN, W, or other suitable conductive materials.In some embodiments, the supply voltage provided to the device region 220 via the back-side interconnect region 410 is different than a supply voltage provided to the memory device region 233 of FIG. 2. For example, in FIGS. 2 and 4, the supply voltage provided to the active devices 422 in the device region 220 may need to be higher than the supply voltage required for the memory cells (e.g., FeRAM cells) in the memory device region 233. In some embodiments, the supply voltage for device area 220 may be provided by back side interconnect area 410 and the supply voltage for memory device area 233 may be provided by a voltage source electrically connected to second interconnect area 232 that includes interconnect structures electrically connected to memory device area 233.In FIG. 4, in some embodiments, the active devices 422 may be other types of devices, such as planar MOSFETs, FinFETs, nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nanoribbon transistors), or a combination thereof. The active devices 422 may be separated from each other using methods such as shallow trench isolation, deep trench isolation, local oxidation of silicon, other suitable isolation methods, or a combination thereof. In some embodiments, the active devices 422 may represent one or more of the electrical components in the memory system 100 of FIG. 1 (e.g., a row decoder 110, an I / O circuit 120, a sense amplifier 130, and a column decoder 140). In some embodiments, the active devices 422 may represent one or more electrical components of the storage system, another system, or a combination of both systems. Although not shown in FIG. 4, the device portion 220 may also include passive devices (e.g., resistors, capacitors, and inductors).In some embodiments, the first interconnect region 231 may include interconnect structures, e.g., metal line structures 431 and 432 and metal via structures 234 and 433, disposed in an interlayer dielectric structure 434. Metal line structures 431 and 432 and metal via structures 234 and 433 may be electrically connected to the active and / or passive devices in device region 220 (e.g., active devices 422) such that these electrical components may be electrically connected to each other and / or to upper interconnect structures (e.g., interconnect structures in second interconnect region 232 and third interconnect region 236, not shown in FIG. 4 ). The metal line structures and the metal via structures may include Cu, Al, TiN, TaN, W, or other suitable conductive materials. The interlayer dielectric structure 434 may include a dielectric material such as SiO x, SiOH, SiON, SiN x, SiOC, SiOCN, or a combination thereof. The interlayer dielectric structure 434 may include a stack of dielectric layers to implement multiple layers of interconnect structures.FIG. 5 is a circuit diagram of a portion 500 of the memory array 150, in accordance with some embodiments. In some embodiments, the portion 500 may be disposed in the storage device area 233 of FIG. 2. In FIG. 5, portion 500 includes the following elements: a first NOR string arrangement including FeRAM cells 510, 511, 512, and 513 electrically connected to each other along a first bit line (e.g., BL[K], where K is an integer equal to or greater than zero); a second NOR string arrangement including FeRAM cells 520, 521, 522, and 523 electrically connected to each other along a second bit line (e.g., BL[K+1]); a third NOR string arrangement including FeRAM cells 530, 531, 532, and 533 electrically connected to each other along a third bit line (e.g., BL[K+2]); and a fourth NOR string arrangement including FeRAM cells 540, 541, 542, and 543 electrically connected to each other along a fourth bit line (e.g., BL[K+13). In FIGS. 1 and 2, the bit lines BL[K], BL[K+1], BL[K+2], and BL[K+3] of the part 500 in the memory array 150 may be electrically connected to the column decoder 140. In some embodiments, the column decoder 140 may be disposed in the device area 220 and electrically connected to the FeRAM cells 510- 513, 520- 523, 530- 533, and 540- 543 of the first, second, third, and fourth NOR string arrays of the memory array 150 in the memory device area 233 through interconnect structures in the first interconnect area 231.In FIG. 5, the part 500 includes source lines SL[M] and SL[M+1] (where M is an integer equal to or greater than zero) electrically connected to common source terminals of the FeRAM cells. The source line SL[M] is electrically connected to common sources of the FeRAM cells 510, 511, 520, 521, 530, 531, 540, and 541. The source line SL[M+1] is electrically connected to common sources of the FeRAM cells 512, 513, 522, 523, 532, 533, 542, and 543. In some embodiments, source lines SL[M] and SL[M+1] are electrically connected to a reference voltage source, such as ground (e.g., 0 V).In FIG. 5, the part 500 also includes word lines WL[N], WL[N+1], WL[N+2], and WL[N+3] (where N is an integer equal to or greater than zero). The word line WL[N] is electrically connected to gate terminals of the FeRAM cells 510, 520, 530, and 540. The word line WL[N+1] is electrically connected to gate terminals of the FeRAM cells 511, 521, 531, and 541. The word line WL[N+2] is electrically connected to gate terminals of the FeRAM cells 512, 522, 532, and 542, and the word line WL[N+3] is electrically connected to gate terminals of the FeRAM cells 513, 523, 533, and 543. In FIGS. 1 and 2, word lines WL[N], WL[N+1], WL[N+2], and WL[N+3] in memory array 150 may be electrically connected to row decoder 110. In some embodiments, row decoder 110 may be disposed in device area 220 and electrically connected to the FeRAM cells in the first, second, third, and fourth NOR string arrangements of memory array 150 in memory device area 233 through interconnect structures in first interconnect area 231.Based on the present description, portion 500 may include more or less than four FeRAM cells for each NOR string array and more or less than four NOR string arrays for memory array 150. These alternative arrangements of the memory array 150 are also within the scope of the present disclosure.FIG. 6A is a top view layout diagram of portion 500 of memory array 150, in accordance with some embodiments. A portion 600 of the layout diagram will now be described based on the repetitive structure of the FeRAM cells in the portion 500. The description of portion 600 also applies to the remainder of memory array 150. For ease of explanation, FIG. 6B shows an enlarged representation of portion 600.In some embodiments, portion 600 includes fin structure 610, gate structure 620, gate contact structure 630, first metal line structure 640, source / drain contact structures 650, metal via structure 660, second metal line structure 670, and third metal line structure 680. In some embodiments, the fin structure 610 is formed along a first direction (e.g., an x-direction) and may include indium gallium zinc oxide or other suitable materials. The gate structure 620 is formed along a second direction (e.g., a z-direction, i.e., a direction that is perpendicular to the first direction) and over the fin structure 610. In some embodiments, the gate structure 620 may include polysilicon, Si, Ti, Ta, Al, W, nitrogen (N), zinc (Zn), indium (In), Ga, Ge, carbon (C), or other suitable materials. In some embodiments, the gate structure 620 may include TiN. A gate contact structure 630 is arranged on the gate structure 620. In addition, a first metal line pattern 640 (e.g., WL[N+3]) along the second direction (e.g., the z-direction) is formed on the gate contact pattern 630. The gate contact structure 630 and the first metal line structure 640 may include Cu, Al, TiN, TaN, W, or other suitable conductive materials.In FIG. 6B, source / drain contact structures 650 are further formed adjacent (e.g., in the z-direction) to the gate structure 620. On one of the source / drain contact structures 650, a second metal line structure 670 (e.g., SL[M+1]) is disposed. On the other source / drain contact structure 650, a metal via structure 660 is arranged. A third metal line structure 680 is disposed on the metal via structure 660. In some embodiments, the second metal line pattern 670 (e.g., SL[M+1]) and the first metal line pattern 640 (e.g., WL[N+3]) may be disposed in the same metallization layer (e.g., metallization layer [X]), and the third metal line pattern 680 may be disposed in the next higher metallization layer (e.g., metallization layer [X+1]). The source / drain contact structures 650, the metal via structure 660, the second metal line structure 670, and the third metal line structure 680 may each include Cu, Al, TiN, TaN, W, or other suitable conductive materials.FIG. 7 is a cross-sectional view of portion 600 in memory array 150, in accordance with some embodiments. This cross-sectional view runs along the x-direction and shows the interlayer dielectric structure 235, the fin structure 610, the gate structure 620, the gate contact structure 630, the first metal line structure 640 (e.g., WL[N+3]), the source / drain contact structures 650, the metal via structure 660, the second metal line structure 670, the third metal line structure 680, and a ferroelectric material layer 710. Elements in FIG. 7 with the same designations as elements in FIGS. 2, 6A, and 6B have been described above.In FIG. 7, the fin structure 610 is disposed on the interlayer dielectric structure 235. In some embodiments, the fin structure 610 may provide an n-channel for the FeRAM cell. As set forth above with reference to FIG. 2, the interlayer dielectric structure 235 may include a dielectric material (e.g., SiO x, SiOH, SiON, SiN x, SiOC, SiOCN, or a combination thereof) and may include a stack of dielectric layers to implement multiple layers of interconnect structures. Here, rather than forming multiple layers of interconnect structures on this portion of the interlayer dielectric structure 235, an FeRAM cell (e.g., one of the FeRAM cells 510- 513, 520- 523, 530- 533, and 540 of FIG. 5 ) is formed.In some embodiments, a ferroelectric material layer 710 is disposed on the fin structure 610 to form the FeRAM cell. The ferroelectric material layer 710 may include hafnium zirconium oxide having a zirconium content of about 30% to about 60%, in accordance with some embodiments. In some embodiments, the ferroelectric material layer 710 may be lead zirconate titanate (PbZrTiO), lead zirconate (PbZrO 3), lead titanate (PbTiO 3), barium titanate (BaTiO 3), lead niobate (PbNbO), bismuth titanate (BiTiO), lithium niobate (LiNbO 3), lithium tantalate (LiTaO 3) or other suitable material. The gate structure 620 is disposed on the ferroelectric material layer 710, and adjacent (e.g., in the x-direction) to the gate structure 620, the source / drain contact structures 650 are disposed, wherein in some embodiments, the gate structure 620 forms a gate terminal of the FeRAM cell, and the source / drain contact structures 650 are electrically connected to source / drain regions of the FeRAM cell. Source / drain regions may individually or collectively refer to a source or a drain depending on context. In some embodiments, when the FeRAM cell conducts current based on the voltages applied to the gate and source / drain regions of the FeRAM cell, electrons may flow through the fin structure 610 (e.g., an n-channel) between the source / drain regions. Gate and source / drain voltages for the FeRAM cells may be provided by the gate contact structure 630, the first metal line structure 640, the metal via structure 660, and the second metal line structure 670 to perform a memory read operation, a memory write operation, and other memory operations.FIG. 8 is another cross-sectional view of portion 600 in memory array 150, in accordance with some embodiments. This cross-sectional view runs along the y-direction and shows the interlayer dielectric structure 235, the fin structure 610, the gate structure 620, the gate contact structure 630, the first metal line structure 640 (e.g. WL[N+3]) and the ferroelectric material layer 710. Elements in FIG. 8 with the same designations as elements in FIGS. 2, 6A, 6B, and 7 have been described above.In FIG. 8, in some embodiments, the fin structure 610 may have a height H (e.g., in the y-direction) of about 50 nm to about 1000 nm. In some embodiments, if height H is less than about 50 nm, a device saturation current (I sat) (with fin structure 610) may not be suitable for the purpose of the device. In some embodiments, if the height H is greater than about 1000 nm, the fin structure 610 may collapse. In some embodiments, a thickness T of the ferroelectric material layer 710 (e.g., hafnium zirconium oxide) along a top and side surfaces of the fin structure 610 is greater than about 3 nm and has an orthorhombic phase. In some embodiments, if the thickness T is less than about 3 nm, hafnium zirconium oxide may not have an orthorhombic phase and ferroelectric properties desirable for the ferroelectric material layer 710.To address reliability issues due to higher voltages (e.g., about 5 V and greater) applied to the ferroelectric material layer 710 during various memory operations (e.g., a program memory operation), in some embodiments, the ferroelectric material layer 710 may include three layers: a first protective layer in contact with a top and side surfaces of the fin structure 610; a middle ferroelectric material layer (e.g., hafnium zirconium oxide) in contact with a top and side surfaces of the first protective layer; and a second protective layer in contact with a top and side surfaces of the middle ferroelectric material layer. In some embodiments, the first and second protective layers may each have a thickness of about 1 nm to about 2 nm. To reduce leakage in the FeRAM cell, in some embodiments, the first and second protective layers may be doped with about 1% to about 2% zirconium, respectively. Additionally, in some embodiments, the first and second protective layers may each include hafnium oxide (HfO 2), hafnium aluminum oxide (HfAlO x), hafnium silicate (HfSiO x) or other suitable materials, wherein the first protective layer may include the same material as or a different material than the second protective layer.FIG. 9 is a circuit diagram of another portion 900 of the memory array 150, in accordance with some embodiments. In some embodiments, the portion 900 may be disposed in the storage device area 233 of FIG. 2. In FIG. 9, portion 900 includes the following elements: a first NAND string arrangement including a bit line selection transistor 910, FeRAM cells 911, 912, and 913, and a ground selection transistor 914; and a second NAND string arrangement including a bit line selection transistor 920, FeRAM cells 921, 922, and 923, and a ground selection transistor 924. In the first NAND string arrangement, a source / drain terminal of the bit line selection transistor 910 is electrically connected to a first bit line (e.g., BL[K], where K is an integer equal to or greater than zero). In the second NAND string arrangement, a source / drain terminal of the bit line selection transistor 920 is electrically connected to a second bit line (e.g., BL[K+1]). In FIGS. 1 and 2, the bit lines BL[K] and BL[K+1] of the part 900 in the memory array 150 may be electrically connected to the column decoder 140. In some embodiments, column decoder 140 may be disposed in device region 220 and electrically connected to FeRAM cells 911- 913 and 921- 923 in the first and second NAND string arrangements of memory array 150 in memory device region 233 through interconnect structures in first interconnect region 231.In FIG. 9, the part 900 includes a bit line selection line BLS and a ground selection line GS. In some embodiments, the bit line select line BLS activates the bit line select transistors 910 and 920 to activate the first and second NAND string arrangements. In some embodiments, the ground select line GS activates the ground select transistors 914 and 924 to electrically connect the first and second NAND string arrays to a reference voltage source 930, such as ground (e.g., 0V).In FIG. 9, the part 900 further includes word lines WL[N], WL[N+1], and WL[N+2], where N is an integer equal to or greater than zero. The word line WL[N] is electrically connected to gate terminals of the FeRAM cells 911 and 921. The word line WL[N+1] is electrically connected to gate terminals of the FeRAM cells 912 and 922, and the word line WL[N+12] is electrically connected to gate terminals of the FeRAM cells 913 and 923. In FIGS. 1 and 2, word lines WL[N], WL[N+1], and WL[N+1] in memory array 150 may be electrically connected to row decoder 110. In some embodiments, row decoder 110 may be arranged in device area 220 and electrically connected to the FeRAM cells in the first and second NAND string arrangements of memory array 150 in memory device area 233 through interconnect structures in first interconnect area 231.Based on the present description, portion 900 may include more or less than three FeRAM cells for each NAND string array and more or less than two NAND string arrays for memory array 150. These alternative arrangements of the memory array 150 are also within the scope of the present disclosure.FIG. 10A is a top view layout diagram of portion 900 of memory array 150, in accordance with some embodiments. A portion 1000 of the layout diagram will now be described based on the repetitive structure of the FeRAM cells in the portion 900. The description of portion 1000 also applies to the remainder of memory array 150. For ease of explanation, FIG. 10B shows an enlarged representation of portion 1000.In some embodiments, the portion 1000 includes a fin structure 1010, a gate structure 1020, a gate contact structure 1030, and a metal line structure 1040. In some embodiments, the fin structure 1010 is formed along a first direction (e.g., an x-direction) and may include indium gallium zinc oxide or other suitable materials. The gate structure 1020 is formed along a second direction (e.g., a z-direction, i.e., a direction that is perpendicular to the first direction) and over the fin structure 1010. In some embodiments, gate structure 1020 may include polysilicon, Si, Ti, Ta, Al, W, N, Zn, In, Ga, Ge, C, or other suitable materials. In some embodiments, the gate structure 1020 may include TiN. A gate contact structure 1030 is arranged on the gate structure 1020. In addition, a metal line structure 1040 (e.g. WL[N+2]) along the second direction (e.g. the z-direction) is formed on the gate contact structure 1030. The gate contact structure 1030 and the metal line structure 1040 may include Cu, Al, TiN, TaN, W, or other suitable conductive materials.FIG. 11 is a cross-sectional view of portion 1000 in memory array 150, in accordance with some embodiments. This cross-sectional view runs along the y-direction and shows the interlayer dielectric structure 235, the fin structure 1010, the gate structure 1020, the gate contact structure 1030, the metal line structure 1040 (e.g. WL[N+2]) and the ferroelectric material layer 710. Elements in FIG. 11 with the same designations as elements in FIGS. 2, 7, 8, 10A, and 10B have been described above.In FIG. 11, in some embodiments, the fin structure 1010 may have a height H (e.g., in the y-direction) of about 50 nm to about 1000 nm. In some embodiments, if height H is less than about 50 nm, a saturation current (I sat) of the device (having fin structure 1010) may not be suitable for the purpose of the device. In some embodiments, if the height H is greater than about 1000 nm, the fin structure 1010 may collapse. In some embodiments, the fin structure 1010 may provide an n-channel for the FeRAM cell. In some embodiments, a thickness T of the ferroelectric material layer 710 (e.g., hafnium zirconium oxide) along a top and side surfaces of the fin structure 1010 is greater than about 3 nm and has an orthorhombic phase. In some embodiments, if the thickness T is less than about 3 nm, hafnium zirconium oxide may not have an orthorhombic phase and ferroelectric properties desirable for the ferroelectric material layer 710.To address reliability issues due to higher voltages (e.g., about 5 V and greater) applied to the ferroelectric material layer 710 during various memory operations (e.g., a program memory operation), in some embodiments, the ferroelectric material layer 710 may include three layers: a first protective layer in contact with a top and side surfaces of the fin structure 1010; a middle ferroelectric material layer (e.g., hafnium zirconium oxide) in contact with a top and side surfaces of the first protective layer; and a second protective layer in contact with a top and side surfaces of the middle ferroelectric material layer. In some embodiments, the first and second protective layers may each have a thickness of about 1 nm to about 2 nm. To reduce leakage in the FeRAM cell, in some embodiments, the first and second protective layers may be doped with about 1% to about 2% zirconium, respectively. Additionally, in some embodiments, the first and second protective layers may each include HfO 2, HfAlO x, HfSiO x or other suitable materials, where the first protective layer may include the same material as or a different material than the second protective layer.FIG. 12 is an illustration of a method 1200 of manufacturing a memory cell in a BEOL memory device portion of a semiconductor device, in accordance with some embodiments. Further operations may be performed between different operations of the method 1200 or may be omitted for clarity and ease of description. Further operations may be performed before, during, and / or after method 1200, wherein one or more of these further operations are only briefly described herein. Additionally, not all operations may be required to carry out the disclosure provided herein. Further, some of the operations may be performed simultaneously or in a different order than that indicated in FIG. 12. In some embodiments, one or more additional operations may be performed in addition to or in place of the operations described herein.For purposes of explanation, the operations indicated in FIG. 12 will be described using an example fabrication process for a memory cell in the memory device region 233 of the second interconnect region 232 in FIGS. 2-5, 6A, 6B, 7-9, 10A, 10B, and 11. FIGS. 13 through 18 are partial cross-sectional views of the memory cell at various stages of its fabrication process, in accordance with some embodiments. Elements in Figs. 13 to 18 having the same designations as elements in Figs. 1 to 5, 6A, 6B, 7 to 9, 10A, 10B and 11 have been described above.In FIG. 12, in an operation 1210, one or more electrical components are fabricated on a substrate. For example, in FIGS. 3 and 4, a device region 220 may be formed on a substrate 210. In FIG. 3, device region 220 may include active devices 310 (e.g., planar MOSFETs, FinFETs, GAA-FETs, and nanostructure transistors) implemented in and / or on substrate 210. In FIG. 4, device region 220 may include a back-side interconnect region 410 and a device region 420. The back side interconnect region 410 may include interconnect structures (e.g., as part of a network of redistribution layers of interconnect structures) disposed in an interlayer dielectric structure 417 and configured to provide a supply voltage for electrical components in the device region 420. The device region 420 may include active devices 422 (e.g., planar MOSFETs, FinFETs, GAA-FETs, and nanostructure transistors) disposed over the substrate 210 (e.g., in the y-direction). Although not shown in FIGS. 3 and 4, the device region 220 may also include passive devices (e.g., resistors, capacitors, and inductors).In FIG. 12, a first interconnect region is created over the substrate in an operation 1220. The first interconnect region includes first interconnect structures electrically connected to the one or more electrical components. For example, in FIGS. 3 and 4, a first interconnect region 231 may be created over the substrate 210. In FIG. 3, the first interconnect region 231 may include interconnect structures, e.g., metal line structures 320 and a metal via structure 234, disposed in an interlayer dielectric structure 321. The metal line structures 320 and the metal via structure 234 may be electrically connected to the active and / or passive devices in the device region 220 (e.g., the active devices 310) such that these electrical components may be electrically connected to each other and / or to upper interconnect structures (e.g., interconnect structures in a second interconnect region 232 and a third interconnect region 236, not shown in FIG. 3 ). In FIG. 4, the first interconnect region 231 may include interconnect structures, e.g., metal line structures 431 and 432 and metal via structures 234 and 433, disposed in an interlayer dielectric structure 434. Metal line structures 431 and 432 and metal via structures 234 and 433 may be electrically connected to the active and / or passive devices in device region 220 (e.g., active devices 422) such that these electrical components may be electrically connected to each other and / or to upper interconnect structures (e.g., interconnect structures in second interconnect region 232 and third interconnect region 236, not shown in FIG. 4 ).In FIG. 12, in an operation 1230, a second interconnect area is created over the first interconnect area. The second interconnect region includes second interconnect structures electrically connected to the first interconnect structures. For example, in FIG. 2, disposed over the first interconnect region 231 (e.g., in the y-direction) is the third interconnect region 236, which may include one or more interconnect structures disposed in an interlayer dielectric structure 238. The interconnect structures may include metal line structures 237 and metal via structures (not shown in FIG. 2 ).In FIG. 12, in an operation 1240, a memory device area is created between the first and second interconnect areas. The memory device region includes ferroelectric memory cells. In FIG. 2, a memory device area 233 is created between the first interconnect area 231 and the third interconnect area 236. In some embodiments, the memory device portion 233 may include one or more electrical components of the memory system 100 of FIG. 1, such as the memory array 150. In some embodiments, the memory array 150 may include ferroelectric memory cells.The fabrication of a memory cell (e.g., a ferroelectric memory cell) in the memory device region 233 will now be described with reference to Figs. 13 to 18. Although FIGS. 13 through 18 show partial cross-sectional views of only one memory cell at various stages of its fabrication process, the following description may also be used for fabricating multiple memory cells in the memory array 150 of FIG. 1, such as memory cells in a NOR string arrangement (e.g., in the portion 500 of the memory array 150 of FIGS. 5, 6A, and 6B ) and memory cells in a NAND string arrangement (e.g., in the portion 900 of the memory array 150 of FIGS. 9, 10A, and 10B ).In FIG. 13, a fin structure 610 / 1010 is formed on the interlayer dielectric structure 235. This formation may include a deposition of indium gallium zinc oxide or other suitable material (e.g., with an atomic layer deposition process and a physical vapor deposition process) on the interlayer dielectric structure 235 and a fin cutting operation to form the fin structure 610 / 1010. A height H (e.g., in the y-direction) of the fin structure 610 / 1010may be about 50 nm to about 1000 nm in some embodiments.In FIG. 14, for example, a ferroelectric material layer 710 and a gate structure 620 / 1020 are deposited on the fin structure 610 / 1010 using an atomic layer deposition process. In some embodiments, a thickness T of the ferroelectric material layer 710 (e.g., hafnium zirconium oxide) along a top and side surfaces of the fin structure 610 / 1010 is greater than about 3 nm and has an orthorhombic phase.In FIG. 15, a polishing operation (e.g., a chemical mechanical polishing operation) and a cutting operation are performed. In FIG. 16, another interlayer dielectric structure 235 is formed on the structure shown in FIG. 15. In FIG. 17, a gate pad 1710 and source / drain pads 1720 are formed with, for example, a photo pattern and etch process. In FIG. 18, the gate terminal opening 1710 and the source / drain terminal openings 1720 are filled with a conductive material, e.g., Cu, Al, TiN, TaN, W, or other suitable conductive materials, and the resulting filled structures are polished to produce a gate contact structure and source / drain contact structures.In the present disclosure, a semiconductor device (e.g., semiconductor device 200 of FIG. 2 ) including memory devices (e.g., FeRAM cells in memory device region 233 of FIG. 2 ) in a BEOL region (e.g., second interconnect region 232 of FIG. 2 ) will be described. The semiconductor device may include: a substrate; a first interconnect region disposed over the substrate; a second interconnect region disposed over the first interconnect region; and a third interconnect region disposed over the second interconnect region. The substrate (e.g., the substrate 210 of FIG. 2 ) may include electrical components, e.g., active devices, passive devices, or a combination of active and passive devices fabricated on the substrate. The first interconnect region (e.g., the first interconnect region 231 of FIG. 2 ) may include interconnect structures (e.g., metal line structures and metal via structures) to electrically connect the electrical components to one another and / or to upper interconnect structures (e.g., interconnect structures in the second interconnect region 232 and in a third interconnect region 236 of FIG. 2 ). The second interconnect region may include a memory device region (e.g., memory device region 233 of FIG. 2 ) and interconnect structures (e.g., metal line structures and metal via structures). The memory device region may include memory cells (e.g., FeRAM cells) electrically connected to the electrical components via the interconnect structures in the first interconnect region. The ferroelectric memory cells may each include a ferroelectric material (e.g., the ferroelectric material layer 710 of FIGS. 7, 8, and 11 ) disposed on a top and side surfaces of a fin structure (e.g., the fin structure 610 of FIGS. 6B, 7, and 8 and the fin structure 1010 of FIGS. 10B and 11 ). Additionally, the third interconnect region may include interconnect structures (e.g., metal line structures and metal via structures).One of several benefits of implementing memory cells in the memory device area is that the BEOL area of the semiconductor device can be used for the manufacture of memory cells, thereby increasing the storage capacity in the semiconductor device. Another benefit of implementing the memory cells in the BEOL area is that additional substrate area is available for implementing other electrical components to improve the functionality and performance of the semiconductor device.Embodiments of the present disclosure include a structure having a first interconnect area, a second interconnect area, and a memory device area. The first interconnect region is disposed over a substrate and includes first interconnect structures. The second interconnect region is disposed over the first interconnect region and includes second interconnect structures electrically connected to the first interconnect structures. The memory device region is disposed between the first and second interconnect regions and includes ferroelectric memory cells.Embodiments of the present disclosure include a semiconductor structure having a substrate, a first interconnect region, a second interconnect region, and a memory device region. The substrate has one or more electrical components fabricated thereon. The first interconnect region is disposed over the substrate and includes first interconnect structures electrically connected to the one or more electrical components. The second interconnect region is disposed over the first interconnect region and includes second interconnect structures electrically connected to the first interconnect structures. The memory device region is disposed between the first and second interconnect regions and includes ferroelectric memory cells electrically connected to the one or more electrical components through the first interconnect structures. The ferroelectric cells each contain a ferroelectric material arranged on a fin structure.Embodiments of the present disclosure include a method of manufacturing a memory cell in a BEOL memory device area of a semiconductor device. The method includes fabricating one or more electrical components on a substrate. The method further comprises: creating, over the substrate, a first interconnect region having first interconnect structures electrically connected to the one or more electrical components; and creating, over the first interconnect region, a second interconnect region having second interconnect structures electrically connected to the first interconnect structures. The method further comprises creating a memory device area between the first and second interconnect areas, the memory device area including ferroelectric memory cells.It is to be understood that the Detailed Description section, rather than the Summary section, is intended to be used to interpret the claims. In the Summary section, one or more, but not all, possible embodiments of the present disclosure contemplated by the inventors may be set forth and, therefore, are not intended to limit the appended claims in any way.Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objects and / or to achieve the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedUS 63 / 516,887
[0001]
Claims
A structure comprising: a first interconnect region over a substrate including a first plurality of interconnect structures; a second interconnect region over the first interconnect region including a second plurality of interconnect structures electrically connected to the first plurality of interconnect structures; and a memory device region between the first interconnect region and the second interconnect region, wherein the memory device region includes a plurality of ferroelectric memory cells.The structure of claim 1, wherein: the plurality of ferroelectric memory cells comprises a plurality of ferroelectric random access memory cells, each of the plurality of ferroelectric random access memory cells having a ferroelectric material layer with a first protective layer and a second protective layer, the first protective layer and the second protective layer having a width of about 1 nm to about 2 nm and being doped with about 1% to about 2% zirconium.The structure of claim 1 or 2, wherein each of the ferroelectric memory cells comprises: a fin structure including an indium gallium zinc oxide material; and a hafnium zirconium oxide layer disposed on the fin structure.The structure of claim 3, further comprising: a first protective layer disposed between the fin structure and the hafnium zirconium oxide layer; and a second protective layer disposed on the hafnium zirconium oxide layer, wherein the first protective layer and the second protective layer include hafnium oxide, hafnium aluminum oxide, and / or hafnium silicon oxide.The structure of any preceding claim, wherein: the plurality of ferroelectric memory cells are arranged in a NOR string array of ferroelectric memory cells.The structure of claim 5, wherein: the plurality of ferroelectric memory cells comprises a first ferroelectric memory cell and a second ferroelectric memory cell, and the NOR string arrangement of ferroelectric memory cells comprises: a source / drain (S / D) region of the first ferroelectric memory cell and an S / D region of the second ferroelectric memory cell electrically connected to a common source line; and another S / D region of the first ferroelectric memory cell and another S / D region of the second ferroelectric memory cell electrically connected to a bit line.The structure of claim 6, wherein the common source line is electrically connected to ground.The structure of any one of claims 1 to 4, wherein: the plurality of ferroelectric memory cells are arranged in a NAND string array of ferroelectric memory cells.The structure of claim 8, wherein: the plurality of ferroelectric memory cells comprise a first ferroelectric memory cell and a second ferroelectric memory cell, and the NAND string arrangement of ferroelectric memory cells comprises: a source / drain (S / D) region of the first ferroelectric memory cell electrically connected to a bit line selection transistor; an S / D region of the second ferroelectric memory cell electrically connected to a ground selection transistor; and another S / D region of the first ferroelectric memory cell and another S / D region of the second ferroelectric memory cell electrically connected to each other.The structure of any of claims 3 to 9, wherein: the fin structure has a height of about 50 nm to about 1000 nm.A semiconductor structure comprising: a substrate having one or more electrical components fabricated thereon; a first interconnect region over the substrate including a first plurality of interconnect structures electrically connected to the one or more electrical components; a second interconnect region over the first interconnect region including a second plurality of interconnect structures electrically connected to the first plurality of interconnect structures; and a memory device area between the first interconnect structures and the second interconnect area, the memory device area including a plurality of ferroelectric memory cells electrically connected to the one or more electrical components through the first plurality of interconnect structures, each of the plurality of ferroelectric memory cells including a ferroelectric material disposed on a fin structure.The semiconductor structure of claim 11, further comprising a third interconnect region disposed among the plurality of electrical components.The semiconductor structure of claim 11 or 12, wherein: the one or more electrical components comprise a plurality of active devices, a plurality of passive devices, or a combination thereof.The semiconductor structure of claim 13, wherein: the plurality of active devices comprises a fin field effect transistor, a gate-all-around transistor, a planar field effect transistor, or a combination thereof.The semiconductor structure of any of claims 11 to 14, wherein: the substrate includes a back side interconnect region having interconnect structures configured to provide a supply voltage to the one or more electrical components.A method comprising: forming one or more electrical components on a substrate; creating, over the substrate, a first interconnect region having a first plurality of interconnect structures electrically connected to the one or more electrical components; creating, over the first interconnect region, a second interconnect region having a second plurality of interconnect structures electrically connected to the first plurality of interconnect structures; and creating a memory device region between the first interconnect region and the second interconnect region, wherein the memory device region includes a plurality of ferroelectric memory cells.The method of claim 16, further comprising: fabricating a third interconnect structure among the one or more electrical components.The method of claim 16 or 17, wherein: creating the memory device area comprises fabricating a plurality of ferroelectric random access memory cells, each of the ferroelectric memory cells comprising: a fin structure including an indium gallium zinc oxide material; and a hafnium zirconium oxide layer disposed on the fin structure.The method of any of claims 16 to 18, wherein: creating the memory device area comprises creating a NOR string array of ferroelectric memory cells, the plurality of ferroelectric memory cells comprises a first ferroelectric memory cell and a second ferroelectric memory cell, and the NOR string of ferroelectric memory cells comprises: a source / drain (S / D) area of the first ferroelectric memory cell and an S / D area of the second ferroelectric memory cell electrically connected to a common source line; and another S / D area of the first ferroelectric memory cell and another S / D area of the second ferroelectric memory cell electrically connected to a bit line.The method of any of claims 16 to 19, wherein: creating the memory device area comprises creating a NAND string array of ferroelectric memory cells, the plurality of ferroelectric memory cells comprises a first ferroelectric memory cell and a second ferroelectric memory cell, and the NAND string of ferroelectric memory cells comprises: an S / D area of the first ferroelectric memory cell electrically connected to a bit line selection transistor; an S / D area of the second ferroelectric memory cell electrically connected to a ground selection transistor; and another S / D area of the first ferroelectric memory cell and another S / D area of the second ferroelectric memory cell electrically connected to each other.