Power electronic circuit arrangement with a first and second power switch

Abstract

A power electronic circuit arrangement is presented, comprising a substrate, a first conductor track arranged on the substrate with a first power switch, a second conductor track arranged on the substrate with a second power switch, wherein the first power switch has two first switchable semiconductor devices and the second power switch has two second switchable semiconductor devices, wherein the two first and second switchable semiconductor devices are arranged along a first principal direction such that the ratio of a first relative distance of the two first semiconductor devices to a second relative distance of the two second semiconductor devices is at least 1:10.

Description

[0001] The invention describes a power electronic circuit arrangement with a substrate, a first conductor track arranged on the substrate with a first power switch, a second conductor track arranged on the substrate with a second power switch, wherein the first power switch has two first switchable semiconductor devices and the second power switch has two second switchable semiconductor devices, wherein the two first and second switchable semiconductor devices are arranged along a first principal direction.

[0002] DE 11 2020 006 374 T5 discloses a power module comprising a group of at least three rectangular electrical power components arranged on a substrate, wherein at least one side of at least one of the rectangular electrical power components is not orthogonal or parallel to a line passing through the geometric centers of the remaining rectangular electrical power components of the group.

[0003] With knowledge of the prior art, the invention is based on the objective of arranging the semiconductor components of the power switches in an improved manner along a main direction.

[0004] This problem is solved according to the invention by a power electronic circuit arrangement with a substrate, a first conductor track arranged on the substrate with a first power switch, a second conductor track arranged on the substrate with a second power switch, wherein the first power switch has two first switchable semiconductor devices and the second power switch has two second switchable semiconductor devices, wherein the two first and second switchable semiconductor devices are arranged along a first principal direction such that the ratio of a first relative distance of the two first semiconductor devices to a second relative distance of the two second semiconductor devices is at least 1:10, preferably at least 1:20, and particularly preferably at least 1:30.

[0005] Here and subsequently, the term "along a principal direction" means that the respective semiconductor devices are arranged along a straight line, with the straight line intersecting the surface of each semiconductor device. The term "relative distance" here and subsequently means the product of the minimum distance between two semiconductor devices and their respective extents in the principal direction.

[0006] It can be advantageous if the first and second circuit breakers are arranged in a two-level half-bridge topology.

[0007] It can be particularly advantageous if the first two switchable semiconductor devices are arranged between the second two switchable semiconductor devices when viewed along the first principal direction.

[0008] It may be preferred if the distance of the respective second switchable semiconductor device to the edge of the substrate directly adjacent in the first principal direction is less than twice, preferably once, the width of the respective second switchable semiconductor device.

[0009] It may also be preferred if first load connection elements, preferably bond wires, extend from the respective top side of the first switchable semiconductor devices and are oriented orthogonally to the first principal direction.

[0010] It may also be preferred if second load connection elements, preferably bond wires, extend from the respective top side of the second switchable semiconductor devices and are oriented orthogonally to the first principal direction.

[0011] In this context, the term "bonding wire" should be understood to include not only a wire with a round cross-section, but also a ribbon-shaped design with a rectangular cross-section.

[0012] It can be advantageous if each power switch additionally has a power diode which, with respect to the switchable semiconductor components, is not arranged in the first principal direction, but orthogonally to it.

[0013] Additionally, it can be advantageous if the first to fourth power switches are arranged in a three-level half-bridge topology. It is particularly preferred if a third power switch is arranged on a third conductor track of the substrate and a fourth power switch is arranged on a fourth conductor track of the substrate. It can also be advantageous if the third power switch comprises two third-order switchable semiconductor devices and the fourth power switch comprises two fourth-order switchable semiconductor devices, wherein the two third-order and fourth-order switchable semiconductor devices are arranged along a second principal direction such that the ratio of the first relative distance of the two third-order semiconductor devices to the second relative distance of the two fourth-order semiconductor devices is 1:10 and preferably 1:20.

[0014] Finally, it may be preferred if the distance of the respective fourth switchable semiconductor device to the edge of the substrate directly adjacent in the first principal direction is less than twice, preferably one, the width of the respective fourth switchable semiconductor device. It may also be preferred if the second principal direction is oriented parallel or orthogonal to the first principal direction.

[0015] Naturally, unless explicitly or inherently excluded or contrary to the concept of the invention, the features mentioned in the singular can be present multiple times in the circuit arrangement according to the invention. It is understood that the features mentioned and explained above and below can be used not only in the combinations specified, but also in other combinations or individually, without departing from the scope of the present invention.

[0016] Further explanations of the invention, advantageous details and features, will become apparent from the following description of the invention contained in the Fig. 1 to 5 schematically illustrated embodiments of the invention or of respective parts thereof. Fig. Figure 1 schematically shows a first embodiment of the power electronic circuit arrangement according to the invention in a top view. Fig. 2 and Fig. Section 3 serves to further explain the invention. Fig. Figure 4 schematically shows a second embodiment of the power electronic circuit arrangement according to the invention in a top view. Fig. Figure 5 schematically shows a third embodiment of the power electronic circuit arrangement according to the invention in a top view.

[0017] Fig. Figure 1 schematically shows a first embodiment of the power electronic circuit arrangement 1 according to the invention in a top view. This power electronic circuit arrangement 1 has a substrate 2 of a conventional design, wherein the substrate 2 itself has an electrically insulating surface or is designed as a composite material with an electrically insulating surface. A first and a second conductor track 31, 32 are formed from this surface of the substrate 2, wherein the second conductor track 32 at least partially surrounds the first conductor track 31 in a U-shape. A groove or gap is formed between the two conductor tracks 31, 32 in order to electrically isolate them from each other.

[0018] A first power switch 41 is arranged on the first conductor track 31, which here is formed by two first switchable semiconductor devices 411, 412 connected in parallel. A second power switch 42 is arranged on the second conductor track 32, which here is formed by two second switchable semiconductor devices 421, 422 connected in parallel.

[0019] According to the invention, all first and second switchable semiconductor devices 411, 412, 421, 422 are arranged along a first principal direction H1, i.e., all semiconductor devices are arranged along a straight line G, wherein the straight line G intersects the surface of each of the semiconductor devices 411, 412, 421, 422, cf. Fig. 2. Due to the design of the substrate 2 and the first and second conductor tracks 31,32, the two first switchable semiconductor devices 411,412 are thus arranged between the two second switchable semiconductor devices 421,422 when viewed along the first main direction H1.

[0020] According to the invention, the ratio of a first relative distance between the two first semiconductor devices 411, 412 to a second relative distance between the two second semiconductor devices 421, 422 is also greater than 1:20. Here, as explained above, the term "first relative distance" denotes the product of the minimum distance 813 between two switchable semiconductor devices 411, 412 and their respective extension 811 in the main direction H1. Consequently, the second relative distance is certainly the product of the minimum distance 823 between two switchable semiconductor devices 421, 422 and their respective extension 821 in the main direction H1.

[0021] In this configuration, each switchable semiconductor component 411, 412, 421, 422 is assigned a power diode 511, 512, 521, 522. The entire circuit arrangement 1 thus forms a two-level half-bridge circuit with two power transistors, each with a power diode connected in parallel.

[0022] The respective power diodes 511, 512, 521, 522 are arranged orthogonally with respect to the main direction of the respective associated switchable semiconductor components 411, 412, 421, 422, not of the first main direction H1, but orthogonally to it.

[0023] According to Fig. 3. First load connection elements 611, here designed as bond wires, extend from a connection section of the second conductor track 32 to the respective top side of the first switchable semiconductor devices 411, 412 and further to the top side of the associated power diodes 511, 511. Due to the arrangement of the switchable semiconductor devices 411, 412 and the associated power diodes 511, 512, these bond wires run orthogonally to the first main direction H1.

[0024] Corresponding second load connection elements 621, also designed as bond wires, extend from the respective top surface of the second switchable semiconductor devices 421, 422, to the top surface of the associated power diodes 521, 522 and further to a further conductor track (not shown). Due to the arrangement of the switchable semiconductor devices 421, 422 and the associated power diodes 521, 522, these bond wires run orthogonally to the first principal direction H1.

[0025] In this embodiment, the distance 824 of the respective second switchable semiconductor device 412,422 to the edge 22 of the substrate 2 directly adjacent in the first principal direction H1 is less than the width 821 of the respective second switchable semiconductor device 421.

[0026] Fig. Figure 4 schematically shows a second embodiment of the power electronic circuit arrangement 1 according to the invention in a top view. This embodiment, in contrast to the Fig. 1 to 3 four instead of two switchable semiconductor devices 411,421 per power switch. However, field-effect power transistors are used here, which do not have an additional power diode as a separate component. The arrangement of the conductor tracks 31,32 and switchable semiconductor devices 411,421 corresponds to a mirror image of that shown in Figure 1. Fig. 1.

[0027] Fig.Figure 5 schematically shows a third embodiment of the power electronic circuit arrangement 1 according to the invention in a top view, wherein for the sake of clarity only the power switches 41, 42, 43, 44, or the switchable semiconductor components 411, 412, 421, 422, 431, 432, 441, 442 forming them, but not the associated conductor tracks are shown.

[0028] Naturally, the third circuit breaker 43 is arranged on a third conductor track of substrate 2, and the fourth circuit breaker 44 is arranged on a fourth conductor track of substrate 2. These four circuit breakers 41, 42, 43, 44 then form a three-level circuit.

[0029] In this embodiment, the two third and fourth switchable semiconductor devices are arranged along a second principal direction H2 such that the ratio of the first relative distance between the two third semiconductor devices 431, 432 and the second relative distance between the two fourth semiconductor devices 441, 442 is also 1:20. In this embodiment, the second principal direction H2 is oriented parallel to the first principal direction H1. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] DE 11 2020 006 374 T5

[0002]

Claims

[1] Power electronic circuit arrangement (1) with a substrate (2), a first conductor (31) arranged on the substrate with a first power switch (41), a second conductor (32) arranged on the substrate (2) with a second power switch (42), wherein the first power switch (41) has two first switchable semiconductor devices (411, 412) and the second power switch (42) has two second switchable semiconductor devices (421, 422), wherein the two first and second switchable semiconductor devices (411, 412, 421, 422) are arranged along a first principal direction (H1) such that the ratio of a first relative distance of the two first semiconductor devices (411, 412) to a second relative distance of the two second semiconductor devices (421, 422) is at least 1:10, preferably at least 1:20, and particularly preferably at least 1:

30. [2] Power electronic circuit arrangement according to claim 1, wherein the first and second power switches (41,42) are arranged in a two-level half-bridge topology. [3] Power electronic circuit arrangement according to one of the preceding claims, wherein the two first switchable semiconductor devices (411,412) are arranged between the two second switchable semiconductor devices (421,422) when viewed along the first principal direction (H1). [4] Power electronic circuit arrangement according to one of the preceding claims, wherein a distance (824) of the respective second switchable semiconductor device (412,422) to the edge (22) of the substrate (2) directly adjacent in the first principal direction (H1) is less than twice, preferably once, the width (821) of the respective second switchable semiconductor device (421). [5] Power electronic circuit arrangement according to one of the preceding claims, wherein first load connection elements (611), preferably bond wires, extend from the respective top side of the first switchable semiconductor devices (411,412) and are oriented orthogonally to the first principal direction (H1). [6] Power electronic circuit arrangement according to one of the preceding claims, wherein second load connection elements (621), preferably bond wires, extend from the respective top side of the second switchable semiconductor devices (421, 422) and are oriented orthogonally to the first principal direction (H1). [7] Power electronic circuit arrangement according to one of the preceding claims, wherein each power switch (41,42) additionally comprises a power diode (511,512) which is arranged not in the first principal direction (H1) but orthogonally to the switchable semiconductor devices (411,412,421,422). [8] Power electronic circuit arrangement according to one of the preceding claims, wherein a third power switch (43) is arranged on a third conductor track of the substrate (2) and a fourth power switch (44) is arranged on a fourth conductor track of the substrate (2). [9] Power electronic circuit arrangement according to claim 8, wherein the first to fourth power switches (41, 42, 43, 44) are arranged in a three-level half-bridge topology. [10] Power electronic circuit arrangement according to claim 8 or 9, wherein the third power switch (43) has two third switchable semiconductor devices (431, 432) and the fourth power switch (44) has two fourth switchable semiconductor devices (441, 442), wherein the two third and fourth switchable semiconductor devices are arranged along a second principal direction (H2) such that the ratio of the first relative distance of the two third semiconductor devices (431, 432) to a second relative distance of the two fourth semiconductor devices (441, 442) is at least 1:10 and preferably at least 1:

20. [11] Power electronic circuit arrangement according to one of claims 8 to 10, wherein the distance of the respective fourth switchable semiconductor device (441,442) to the edge (22) of the substrate (2) directly adjacent in the first principal direction (H1) is less than twice, preferably once, the width of the respective fourth switchable semiconductor device (441,442). [12] Power electronic circuit arrangement according to claim 11, wherein the second principal direction (H2) is oriented parallel or orthogonal to the first principal direction (H1).

Images