INTEGRATED HIGH-K CAPACITOR WITH DEEP TRENCH AND PROCESS

Abstract

The described examples include an integrated circuit having a dielectric layer disposed over a top surface of a semiconductor substrate and extending above a gate electrode. A trench extends from a top surface of the dielectric layer into the substrate. A conductive trench electrode is disposed within the trench, and a dielectric liner is disposed between the trench electrode and the semiconductor substrate. A dielectric cap layer is disposed on top of the conductive trench electrode and on top of the dielectric layer and extends above the gate electrode.

Description

TECHNICAL FIELD

[0001] This applies to capacitors in general and in particular to capacitors integrated into integrated circuits. BACKGROUND

[0002] Integrating capacitors into integrated circuits is challenging because the capacitance of a capacitor is proportional to the capacitor's area. However, there is typically not enough area on an integrated circuit to provide the required capacitance. Many techniques have been used to solve this problem, such as folded capacitors, but improving the capacitance per unit area remains a major challenge. SUMMARY

[0003] According to one example, an integrated circuit includes a dielectric layer disposed over a top surface of a semiconductor substrate and extending over a gate electrode. A trench extends from a top surface of the dielectric layer into the substrate. A conductive trench electrode is disposed within the trench, and a dielectric liner is disposed between the trench electrode and the semiconductor substrate. A dielectric cap layer is disposed over the conductive trench electrode and over the dielectric layer and extends over the gate electrode.

[0004] Another example provides a method of fabricating an integrated circuit. An electronic device including a gate electrode is formed in or on a semiconductor substrate having a top surface. A dielectric protective layer is deposited on the substrate and the gate electrode, and a trench is formed through the dielectric protective layer and extends into the substrate. A dielectric liner is deposited on a sidewall of the trench, and a conductive material is formed within the trench. A dielectric cap layer is formed contacting a top surface of the conductive material and extending over the gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a side view of an example integrated circuit. Fig. Figure 2 is a top view of an example capacitor. Fig. 3A-3J (together " Fig. 3") are side view diagrams illustrating an exemplary method for forming an example capacitor. DETAILED DESCRIPTION

[0005] In the drawings, corresponding numbers and symbols generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily to scale.

[0006] In this specification, the term "coupled" may include connections made with intervening elements, and additional elements and various connections may exist between the "coupled" elements. Furthermore, the terms "on" and "over" as used herein may include layers or other elements in which intervening or additional elements are located between an element and the element "over" or "on" which it is located.

[0007] Fig. 1 is a side view of an example integrated circuit 100 including a capacitor 102. The capacitor 102 includes trenches 104 formed in a substrate 106 and including a dielectric layer 109 and trench electrodes 108. The substrate 106 may be any suitable substrate, for example, a semiconductor such as silicon. The substrate 106 may be a doped layer over a bulk substrate, such as a portion of a handle wafer. In some examples, the substrate 106 is or includes an epitaxially formed layer and may be doped as n-type or p-type. The trench electrodes 108 include a high-conductivity metal, such as tungsten in this example. As discussed further below, the high-k dielectric layer 109 has a relative dielectric permittivity, colloquially referred to as "k" or "k-value," that is greater than that of silicon oxide.The high-k dielectric layer 109 may include a laminate of various dielectric materials, at least one of which is a high-k material. The first metallic interconnect 110 is connected to the trench electrodes 108 via unreferenced contact plugs. The first metallic interconnect 110, the contact plugs, and the trench electrodes 108 provide a first terminal of the capacitor 102. The substrate 106, the second metal contact 112, the trench contact 115, and the contact layer 113 comprise a second terminal of the capacitor 102. Isolation regions 118 in the substrate 106 separate the region of the capacitor 102 from the transistor 114 and transistor 116. In this example, the isolation regions 118 are trenches lined with a dielectric such as silicon dioxide and filled with a conductor such as doped polycrystalline silicon.In an alternative example, the isolation regions 118 may be formed simultaneously with the trench electrodes 108, filled with tungsten, and insulated with the same dielectric as the high-k dielectric layer 109.

[0008] Transistor 114 and transistor 116 are example devices. Integrated circuit 100 may include any devices that can be formed in a semiconductor device. In this example, gate 120 of transistor 114 is coupled to third metal contact 122 via contact layer 124. Source / drain 126 of transistor 114 is coupled to fourth metal contact 128 via contact layer 130. Source / drain 132 of transistor 114 is coupled to fifth metal contact 134 via contact layer 136. Additionally, gate 131 of transistor 116 is coupled to sixth metal contact 140 via contact layer 142. Source / drain 144 of transistor 116 is coupled to seventh metal contact 146 via contact layer 148. The source / drain 150 of the transistor 116 is coupled to the eighth metal contact 153 via the contact layer 154.The optional dielectric layer 107 may be a layer of silicon dioxide and / or silicon nitride, which prevents direct contact between the protective layer 105 and electronic components such as transistors 114 and 116. The pre-metal dielectric (PMD) layer 160 separates the components in the substrate 106 from the first level of metallic interconnections. A protection layer 105 completely covers the gates 120, 131, and a dielectric cap layer 111 is located between the PMD layer 160 and the protection layer 105. As explained further below, the protection layer 105 can protect electronic components located above the substrate 106, such as the transistor 114 and the transistor 116, from processing steps used to form the high-k dielectric layer 109 and from contamination by the constituents of the high-k dielectric layer 109.

[0009] Fig. 2 is a top view of an example capacitor 102. In Fig. 1 only three trench electrodes 108 are shown. In Fig. 2, twenty-eight trench electrodes 108 are shown. In most examples, a capacitor 102 includes many thousands of trench electrodes 108 to provide the desired capacitance. In the Fig. In the example shown in Figure 2, each column of trench electrodes 108 shifts vertically relative to the adjacent column, forming a hexagonal array in some examples. This achieves a higher density of trench electrodes 108 while keeping the spacing between trench electrodes 108 as large as possible. This is intended to mitigate the effect of fields from adjacent trench electrodes 108, which can affect the overall capacitance of capacitor 102, and to maintain the structural integrity of the die (and wafer).

[0010] Fig. 3A-3J (together " Fig. 3") are side view diagrams illustrating an exemplary method for forming an example capacitor 102. Fig. 3A shows transistor 114, transistor 116, and isolation regions 118 previously formed in and over substrate 106 by known or future developed processes. Dielectric layer 107 is deposited on substrate 106 and transistors 114, 116, in some examples using chemical vapor deposition (CVD) of silane in an oxygen ambient to a thickness of 20 nm to 40 nm, for example, 35 nm. Fig. 3B shows the protective layer 105. CVD forms the protective layer 105 on the structure of Fig. 3A. In this example, the protective layer 105 is a silicon nitride layer with a thickness of approximately 220 nm within a thickness range between 150 nm and 250 nm. Subsequently, the protective layer 105 is planarized using chemical mechanical polishing (CMP). In this example, the protective layer 105 is patterned and etched using photolithography, as shown in Fig. 3B, to provide openings for etching the trenches 152, for example, by reactive ion etching (RIE) using carbon tetrafluoride. In this example, the trenches 152 are approximately 1.2 µm wide and 8 µm deep. These dimensions may vary depending on design requirements and are limited only by the available etching and lithography technology.

[0011] Fig. Figure 3C shows an angled implant 155 being applied to the integrated circuit 100. In this example, the angled implant 154 has an angle of 18°, and the substrate 106 is rotated so that the sidewalls of the trenches 152 are evenly implanted. The angled implant 155 has a density of 5 × 10 14 up to 2 × 10 15 atoms / cm 2 and an energy of 150 keV to 300 keV, while the wafer is rotated 90° four times in this example. An additional vertical implant of 5 × 10 14 up to 1.5 × 10 15 atoms / cm 2and an energy of 25 keV to 75 keV dopes the bottom of the trenches 152. This implant has the same conductivity as the substrate 106 and increases the conductivity of the substrate 106 along the walls of the trenches 152, thereby forming a well region (not explicitly shown) around the trenches 152 that has the same conductivity type as the substrate 106. The well region may provide a higher conductivity than the unmodified substrate 106 to implement part of the second terminal of the capacitor 102. Fig. 3D-1 and 3D-2 illustrate the deposition of the high-k dielectric layer 109 as a laminate using atomic layer deposition (ALD). Optionally, a layer of titanium nitride (not shown) is formed by CVD to a thickness of 0.5 nm to 1 nm on the walls of the trenches 152 before depositing a high-k dielectric layer 109 to improve the conductivity of the surfaces of the trenches 152 and to provide a barrier between the high-k dielectric layer 109 and the substrate 106.

[0012] ALD is a thin-film deposition technique used to create precise, highly conformal, and ultrathin layers of material on substrates. ALD, a form of CVD, can deposit one atomic layer at a time, allowing excellent control over layer thickness and composition. ALD may rely on two chemical precursors that react with an exposed surface in a sequential, self-limiting manner. A first precursor may contain elements that provide the deposition (e.g., a metal or oxide), while a second precursor may be a reactive gas that removes an undesirable portion of the first precursor. In various examples, the substrate is subjected to a series of alternating steps. In examples using two precursors, a deposition process may include steps such as the following to deposit a layer of material on a substrate in a process chamber: Step 1: Introduction of the first precursor into the process chamber. The first precursor can chemisorb or react with exposed surfaces of the substrate. The reaction is self-limiting, meaning it stops when all available sites on the substrate surface are consumed. The temperature of the reaction chamber is 220°C to 300°C, which is generally lower than in other back-end semiconductor manufacturing processes. Step 2: After the substrate surface has been exposed to the first precursor, all unreacted precursors and by-products are removed from the chamber to prevent contamination. Step 3: Introduce the second precursor into the process chamber, react with the surface as modified by the first precursor, and saturate any remaining active sites on the substrate. Step 4: After the substrate surface has been exposed to the second step, all unreacted precursors and by-products are removed from the chamber to prevent contamination.

[0013] The ALD cycle is repeated as many times as necessary to achieve the desired film thickness. Over multiple cycles, the controlled, sequential deposition of atomic layers forms the desired thin film. The film thickness is precisely controlled by the number of ALD cycles.

[0014] As in Fig. As shown in Figures 3D-1 and 3D-2, the high-k dielectric layer 109 is deposited on the substrate 106 so that it covers the walls of the trenches 152 and the exposed area of the protection layer 105. As used herein, "high-k" means a relative dielectric permittivity, colloquially referred to as k, of at least 15. The high-k dielectric layer 109 includes alternating layers 156-1, 156-2, 156-3, and 156-4, as shown in the inset, which in this example are alternating zirconium oxide (ZrO2) and aluminum oxide (Al2O3). The aggregate relative permittivity of such a composite dielectric layer may be, for example, about 20. Other high-k dielectrics that can be used include hafnium oxide, titanium oxide, tantalum pentoxide, lanthanum oxide, barium oxide, scandium oxide, yttrium oxide, lutetium oxide, and niobium pentoxide. For clarity, four layers are shown. Twenty to fifty layers can be effectively used.In one example, the precursors of ZrO2 are bis(cyclopentadienyl)dimethylzirconium and ZyALD™ (commercially available from Tokyo Electron Limited, Air Liquide, and others) along with an oxygen-containing precursor such as ozone or water vapor. Examples of precursors of Al2O3 are trimethylaluminum, triethylaluminum, aluminum trichloride, and aluminum triisopropoxide along with an oxygen-containing precursor. This exemplary process is not limited to these chemicals. Many other ALD precursors can be effectively utilized, and new ALD precursor combinations are rapidly being developed.Currently, precursors for antimony, arsenic, barium, bismuth, boron, bromine, cadmium, calcium, carbon, cerium, chromium, cobalt, copper, dysprosium, erbium, europium, gadolinium, gallium, germanium, gold, hafnium, holmium, iridium, iron, lanthanum, lead, lithium, lutetium, magnesium, manganese, molybdenum, neodymium, nickel, niobium, osmium, palladium, phosphorus, platinum, praseodymium, rhenium, rhodium, ruthenium, samarium, scandium, selenium, silicon, silver, strontium, tantalum, terbium, thallium, thullium, tin, titanium, tungsten, vanadium, xenon, ytterbium, yttrium and zinc are also commercially available, allowing for a wide range of potential layers. In this example, the high-k dielectric layer 109 is a laminate of alternating 5 nm ZrO2 and 7.5 nm Al2O3 layers formed until the high-k dielectric layer 109 is 20 nm to 50 nm thick.Particularly importantly, the protective layer 105 protects the other components in the integrated circuit 100, such as the transistor 114 and the transistor 116, from the precursor chemicals used in the ALD process, both during and after manufacturing. For example, without the protective layer 105, the constituents of the precursors and / or the elements of the high-k layer will contaminate other electrical components, thereby affecting device properties such as threshold voltage or breakdown voltage. In particular, the high-k dielectric layer 109 is not limited to ZrO2 and Al2O3. In general, the constituents of the high-k dielectric layer can be selected to meet various electrical design goals, including capacitance per unit area of the capacitor 102, low DC leakage, and high breakdown voltage.In some examples, a thickness of 25 nm has been found to be sufficient to deliver a breakdown voltage greater than 20 V. Other applications may use ALD to provide conformal layers on trenches consistent with other design goals.

[0015] Fig. Figure 3E shows that a conductive layer 158, including a thin layer of titanium nitride (tin) followed by tungsten (W), deposited by sputtering or CVD, is formed to fill the trenches 152. Because the transistor 114 and transistor 116 are protected from the materials on the high-k dielectric layer 109, a variety of materials with desired properties can be used in the high-k dielectric layer 109. An important feature is good growth and adhesion for the desired conductor in the trenches 152. In this case, the top layer of the high-k dielectric layer 109 is Al2O3, which exhibits good adhesion to a wide variety of metals. In this example, titanium nitride provides good adhesion, and tungsten provides sufficient conductivity to ensure low resistance of the trench electrodes 108, even in very deep trenches.

[0016] Fig. 3F shows the conductive layer 158 after etching by chemical mechanical polishing (CMP), in which the portions of the conductive layer 158 outside the trenches 152 are removed. This leaves the trench electrodes 108 in the trenches 152. In addition, the portion of the high-k dielectric layer 109 outside the trenches 152 is removed by the CMP process. After the CMP process, the cap layer 111, for example, CVD silicon dioxide, is deposited using CVD and may have a thickness in a range of 10 nm to 20 nm, for example, about 15 nm. The cap layer 111 protects the upper surfaces of the trench electrodes 108 during silicide formation at a later stage of processing, thereby effectively acting as a silicide blocking layer. In various examples and as illustrated, the upper surfaces of the trench electrodes are higher than the upper surfaces of the gate electrodes 120 and 131 due to the presence of the protection layer 105.The position of a silicide blocking layer vertically spaced from the substrate 106 and the gates 120, 131 contrasts with some baseline integration schemes in which a silicide blocking layer is located directly on the top surface of the underlying substrate, possibly with a pad oxide in between.

[0017] The protective layer 105, the dielectric cap layer 111 and the dielectric layer 107 are then, as in Fig. 3G, to provide openings for the trench contact 115, the source / drain 126, the gate 120, the source / drain 132, the source / drain 144, the gate 131 and the source / drain 150. Fig. 3H shows a siliciding metal layer 164 sputtered into the openings in the protection layer 105 and contacting the trench contact 115, the source / drain 126, the gate 120, the source / drain 132, the source / drain 144, the gate 131, and the source / drain 150. Siliciding metals suitable for this example include titanium, molybdenum, cobalt, tungsten, and others. The dielectric cap layer 111 protects the trench electrodes 108 from the deposition of the siliciding metal layer 164 and the subsequent removal of unreacted portions of the siliciding metal layer 164.

[0018] Fig. Figure 3I shows the result of annealing the integrated circuit 100 with the siliciding metal layer 164 in position. The annealing step causes a metal silicide to form where the siliciding metal layer 164 is in contact with the substrate and the polysilicon gates. This annealing step forms the contact layer 113, the contact layer 130, the contact layer 124, the contact layer 136, the contact layer 148, the contact layer 142, and the contact layer 154. These contact layers provide an ohmic connection to the underlying silicon elements. The unreacted portion of the siliciding metal layer 164 is removed, e.g., by wet etching or another isotropic etching process. The resulting structure is shown in Fig. 3I. In various examples, and as illustrated, the cap layer 111 remains over various portions of the protective layer 105.

[0019] Subsequently, the PMD layer 160 is then deposited on the surface of the structure of Fig. 3J. The PMD layer 160 in this example includes silicon oxide formed by CVD deposition using tetraethylorthosilicate (TEOS) deposited to a thickness of about 1 µm. In some examples, the PMD layer 160 may be a phosphosilicate glass (PSG) and thus also contain phosphorus. It should be noted that the material layers in Fig. 3J are not necessarily drawn to scale, so the apparent similarity in the thickness of the protection layer 105 and the PMD layer 160 may not reflect examples of fabricated devices. Subsequently, the PMD layer 160 is patterned using photolithography and etching to form openings for the trench electrodes 108, the trench contact 115, the source / drain 126, the gate 120, the source / drain 132, the source / drain 144, the gate 131, and the source / drain 150, as shown in Fig. 3J. Unreferenced contact plugs are formed within the PMD layer to the trench electrodes 108 and various silicided electrical contacts. In various examples, the contact plugs are formed by tungsten CVD after a thin layer of titanium nitride.

[0020] After forming the contact plugs, processing may continue by any conventional or future developed techniques to form interconnect metallization and dielectric layers over the substrate 106, as shown in Fig.1. Such interconnects may utilize copper and / or aluminum metallization schemes and may connect the first and second terminals of capacitor 102 to other components of integrated circuit 100. The overall thickness of protection layer 105 and cap layer 111 may be consistent with otherwise standard integrated circuits, so that the extension of trench electrodes 108 above the top surface of substrate 106 does not affect subsequent interconnect processing.

[0021] In particular, since the trenches 152 and thus the high-k dielectric layer 109 are formed after the protection layer 105, contamination of other parts of the integrated circuit 100 with the materials used in the formation of the high-k dielectric layer 109, which could otherwise occur, is limited or prevented both during the formation of the high-k dielectric layer 109 and thereafter in the finished device. Using ALD to form the high-k dielectric layer 109 not only offers the advantage of increasing the capacitance per unit area of the capacitor 102, but the high conformality of ALD also enables the use of very deep trenches, which also increases the capacitance per unit area.Furthermore, ALD allows the selection of a high-k dielectric that has good adhesion to deposited metal, such as tungsten, which is more conductive than doped polysilicon, thus mitigating resistive effects on capacitance in the lower parts of the trench. In various examples, these aspects can provide significantly higher capacitance per unit area compared to analog baseline capacitors using thermal silicon dioxide as the trench liner. For example, in some experimental devices using a ZrO2 / Al2O3 composite dielectric capacitor, a capacitance of 54 fF / µm is observed. 2 which is about three times higher than baseline deep trench capacitors and 40 times higher than some planar capacitors.

[0022] Modifications of the described examples and other examples are possible within the scope of the claims.

Claims

[1] Integrated circuit comprising: a semiconductor substrate having a first upper surface; a first dielectric layer disposed over the first top surface and having a second top surface; a trench extending from the second top surface through the first dielectric layer and into the substrate; a conductive trench electrode within the trench; and a dielectric liner between the trench electrode and the semiconductor substrate. [2] The integrated circuit of claim 1, wherein the dielectric liner includes a high-k dielectric. [3] The integrated circuit of claim 2, wherein the high-k dielectric is selected from the group consisting of zirconium oxide, hafnium oxide, aluminum oxide, hafnium oxide, titanium oxide, tantalum pentoxide, lanthanum oxide, barium oxide, scandium oxide, yttrium oxide, lutetium oxide and niobium pentoxide. [4] The integrated circuit of claim 1, wherein the first dielectric layer covers a transistor gate electrode. [5] The integrated circuit of claim 4, wherein an upper surface of the gate electrode extends a first distance above the upper surface of the substrate and an upper surface of the trench electrode extends a second, greater distance above the substrate surface. [6] The integrated circuit of claim 1, wherein a second dielectric layer extends between the second top surface and an interconnect layer. [7] The integrated circuit of claim 1, wherein the dielectric liner is at least 200 nm thick. [8] The integrated circuit of claim 1, further comprising a first contact plug having a first length from the trench electrode to an interconnect metallization layer and a second contact plug having a greater second length from the substrate surface to the interconnect metallization layer. [9] The integrated circuit of claim 1, wherein the conductive trench electrode is one of an array of conductive trenches including a trench capacitor having a capacitance density of at least 50 fF / µm 2 form. [10] The integrated circuit of claim 1, wherein the dielectric liner includes alternating layers of different dielectric materials. [11] Method comprising: Forming an electronic device in or over a semiconductor substrate having a top surface, the electronic device including a gate electrode; Applying a dielectric protective layer over the substrate and the gate electrode; Forming a trench through the dielectric protection layer extending into the substrate; Applying a dielectric liner to a sidewall of the trench; Forming a conductive material within the trench and Forming a dielectric cap layer contacting a top surface of the conductive material and extending over the gate electrode. [12] The method of claim 11, wherein the dielectric liner has a dielectric constant of at least 15. [13] The method of claim 11, further comprising: Forming a pre-metal dielectric (PMD) layer over the dielectric protection layer; Forming a first contact plug extending through the PMD layer to the conductive material; and Forming a second contact plug extending through the PMD layer to the top side. [14] The method of claim 13, wherein the conductive material and the first and second contact plugs comprise tungsten. [15] The method of claim 11, wherein the dielectric liner is applied by atomic layer deposition. [16] The method of claim 11, wherein the dielectric liner includes alternating layers of different dielectric materials. [17] The method of claim 16, wherein the dielectric liner includes alternating layers of zirconia and alumina. [18] The method of claim 11, further comprising forming a dielectric cap layer on a top surface of the conductive material and forming a pre-metal dielectric (PMD) layer on the dielectric cap layer. [19] The method of claim 11, wherein the trench is one of an array of trenches of a trench capacitor having a capacitance density of at least 50 fF / µm 2 is. [20] The method of claim 11, wherein the dielectric liner comprises a material selected from the group consisting of zirconia, hafnia, alumina, hafnia, titania, tantalum pentoxide, lanthanum oxide, barium oxide, scandium oxide, yttrium oxide, lutetium oxide, and niobium pentoxide.

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