VOLTAGE INSULATION SYSTEM FOR A MICROCHIP

Abstract

A mechanism for controlling the flow of power from a voltage line to an electronic circuit within a microchip. A reset control system initially controls a voltage isolation circuit to prevent this power flow during microchip startup and allows it to resume only when one or more predetermined criteria are met. The voltage monitoring system generates a digital representation of the voltage on a supply line, which the reset control system monitors. The reset control system monitors this digital representation of the voltage to determine when one or more of the predetermined criteria are met.

Description

TECHNICAL AREA

[0001] The present disclosure relates to microchips and in particular to voltage isolation systems for microchips. BACKGROUND

[0002] Microchips are becoming increasingly prevalent in modern electronic devices and play a crucial role in various applications, ranging from consumer electronics to automotive systems and industrial equipment. As microchips become more complex and integrate multiple functions, managing power distribution and ensuring appropriate voltage levels across different components becomes increasingly challenging.

[0003] In safety-critical applications, such as those found in the automotive industry, there is a strong desire for microchips to perform at least two key power management tasks. First, a microchip should monitor all supply voltages (from different power domains) to ensure the proper operation of the various components. Second, they may need to ensure that no unexpected current paths are activated during power-up sequences or when supply voltage conditions are invalid. This second feature is often referred to as power domain isolation.

[0004] For the sake of completeness, it should be noted that a power domain is a section or area of ​​a microchip that operates at a specific voltage level and is equipped with a supply to provide that voltage level. Power domains allow different parts of the microchip to operate at different voltage levels, which can help optimize power consumption and performance and facilitate integration with other components that require different power levels (e.g., operating according to different standards). This subdivision of the power distribution thus enables more efficient and granular power management strategies, especially in complex microchips such as system-on-chips (SoCs), where different components may have different power requirements or operating states.

[0005] There is a persistent desire to configure a microchip to perform these two tasks reliably and efficiently. SUMMARY

[0006] This document proposes a voltage isolation system for controlling, in a microchip, the flow of power from a voltage line to an electronic circuit.

[0007] The voltage isolation circuit comprises: a voltage isolation circuit configured to control power flow between the voltage line and the electronic circuit in response to a control signal; a voltage monitoring system configured to generate a digital representation of a voltage on a supply line for the electronic circuit; and a reset control system configured to: provide the control signal to the voltage isolation circuit and: receive and monitor the digital representation of the voltage on the supply line from the voltage monitoring system.

[0008] The reset control system is further configured to: initially, using the control signal, control the voltage isolation circuit to prevent power flow from the voltage line to the electronic circuit; and, in response to each of one or more first predetermined criteria being met after the microchip has started, authorize the voltage isolation circuit to allow power flow from the voltage line to the electronic circuit, wherein one or more of the first predetermined criteria include a criterion that the digital representation of the voltage on the supply line meets each of one or more second predetermined criteria after the microchip has started.

[0009] The expert will recognize additional features and advantages upon reading the following detailed description and upon examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference symbols refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various examples shown may be combined, provided they are not mutually exclusive. Fig. 1 represents a section of an existing microchip. Fig. Figure 2 represents a proposed stress isolation system. Fig. Figure 3 represents a microchip that incorporates a proposed voltage isolation system. Fig. Figure 4 represents a section of a proposed microchip. DETAILED DESCRIPTION

[0011] The examples described herein provide a mechanism for controlling the flow of power from a voltage line to an electronic circuit within a microchip. A reset control system initially controls a voltage isolation circuit to prevent this power flow when the microchip starts up and allows it to resume only when one or more predetermined criteria are met. The voltage monitoring system generates a digital representation of the voltage on a supply line, which the reset control system monitors. The reset control system monitors this digital representation of the voltage to determine when one or more of the predetermined criteria are met.

[0012] In particular, the disclosed approach effectively proposes integrating or combining voltage monitoring and voltage / power isolation control into a single system. This integration leads to more compact layouts and improved power efficiency.

[0013] In the context of this disclosure, the term "microchip" does not necessarily mean that there is only a single semiconductor die in a package. In some cases, a microchip may, in addition to one or more cores, register memory, and additional functionality, include one or more additional chiplets integrated into a single package, for example, providing memory or input / output functionality. Thus, a microchip may comprise one or more semiconductor dies and / or chiplets integrated into a single package.

[0014] Fig. Figure 1 presents a section 100 of an existing microchip for the purpose of improved contextual understanding. In particular, the presented section 100 comprises a voltage isolation system 110 and a voltage monitoring system 120.

[0015] One objective of the voltage isolation system 110, known as power domain isolation, is to ensure that no unexpected current path or power flow is formed or activated during power-up or invalid supply voltage conditions. Such a current path or power flow could undesirably generate faulty signals, for example, to or from the electronic circuit, which could lead to unexpected behavior of the electronic circuit. In some applications, such as in the automotive industry, unexpected behavior could lead to catastrophic failures and / or damage.

[0016] The voltage isolation system 110 of the existing microchip includes a voltage isolation circuit 111 which is configured to control a power flow between a voltage line VL and an electronic circuit 190 in response to a control signal SC.

[0017] The voltage line VL can, for example, carry a circuit control signal to control an operation or function of the electronic circuit 190. It may be desirable to prevent the circuit control signal from controlling an operation of the electronic circuit until, for example, the power supply(s) in the microchip have stabilized or reached one or more predetermined levels. This reduces the risk of unexpected behavior of the electronic circuit 190.

[0018] The voltage isolation circuit 110 can, for example, be formed from one or more level shifters with an activation / deactivation function. In particular, the level shifter(s) can be connected between the voltage line VL and the electronic circuit 190 and configured to switch (in response to the control signal) between an activation state (in which current may flow between the voltage line VL and the electronic circuit) and a deactivation state (in which no or negligible current may flow between the voltage line VL and the electronic circuit).

[0019] The voltage isolation system 110 further comprises a reset control system 112, which is configured to generate the control signal SC for the voltage isolation circuit 111. In this way, the reset control system 112 controls the power flow between the voltage line VL and the electronic circuit 190 using the voltage isolation circuit 111 via the control signal SC.

[0020] In particular, the reset control system 112 is configured to initially control the voltage isolation circuit 111 after the microchip starts up, in order to prevent power flow from the voltage line VL to the electronic circuit 190. The reset control system 112 is also configured to allow the voltage isolation circuit to permit power flow from the voltage line VL to the electronic circuit (e.g., to enable the level shifter(s)) only if the voltage on a supply line VS1 (e.g., for the electronic circuit 190) meets one or more predetermined conditions (e.g., is stable and / or violates a predetermined voltage level). Thus, the reset control system 112 can monitor the voltage on the supply line and generate the control signal in response to the monitored voltage.

[0021] A supply line provides a supply voltage to power the electronic circuit and / or one or more other elements of a system (e.g. microchips) that includes or contains the electronic circuit 190.

[0022] The reset control system 112 may require that one or more additional conditions be met before the voltage isolation circuit is allowed to permit power flow from the voltage line VL to the electronic circuit 190. For example, the reset control system 112 may also monitor the voltage on each of one or more additional supply lines, such as a second supply line VS2. In such cases, the reset control system may allow the voltage isolation circuit to permit power flow from the voltage line to the electronic circuit (e.g., to enable the level shifter(s)) in response to the voltage on each supply line VS1, VS2 meeting a respective set of one or more predetermined conditions (e.g., each voltage is stable and / or violates a predetermined voltage level for the supply line).

[0023] The reset control system 112 of the existing voltage isolation system 110 performs analog-based monitoring of the voltage on the supply line VL (and, if applicable, each additional supply line VS2). Specifically, the reset control system 112 includes respective analog comparators 113A, ..., 113N to compare the voltage on each supply line with a respective reference voltage VREF. The respective reference voltage(s) is / are generated by a bandgap voltage reference circuit BG or a similar circuit of the reset control system 112. In some cases, the bandgap voltage reference circuit BG may be a power-on reset generator. The reset control system 112 also includes control logic 114 to generate the control signal when the voltage on each supply line violates a predetermined threshold.

[0024] Separately from the voltage isolation system 110, section 100 of the microchip also includes a voltage monitoring system 120. The voltage monitoring system 120 is configured to generate a digital representation of the voltage on the supply line for each supply line V21, VS2. Thus, each voltage monitoring system 120 can measure the voltage on the respective supply line(s) and generate a digital representation of this measurement.

[0025] The digital representations of the voltage(s) of the supply line(s) generated by the voltage monitoring system 120 can, for example, be used by a power management system (in Fig. (1 not shown) can be used to control the voltage on the supply line(s), e.g. to perform feedback control of the voltage on the supply line(s).

[0026] As the number of supply lines in the microchip increases, identifying and selecting suitable reference voltages for all supply lines becomes increasingly complex due to the need to account for tolerances in various microchip components. Furthermore, there is a significant dependence on analog components (whose accuracy varies due to manufacturing tolerances) for precise control of the voltage isolation system.

[0027] The isolation and monitoring system can become additionally complex in voltage isolation system implementations that must use CMOS devices (common in the prior art) which are unable to support supply voltages higher than those specified for the supply line. For example, there may be a need to provide isolation between a voltage line designed to carry 3.3 V and an electronic circuit using CMOS technology that only offers 1.8 V robust gates.

[0028] In such configurations, the voltage carried by the supply line can therefore function as a "high voltage" and would thus benefit from appropriate protection for circuit components. For the existing system, this protection must be implemented separately for the voltage isolation system and the voltage monitoring system.

[0029] Although high-voltage protection can be achieved by stacking transistors (e.g., in a cascode), the stacked transistors may need to be properly biased to prevent overvoltage. This is accomplished by using a resistive divider to generate gate voltages for the cascode transistors. However, using a resistive divider can require a static current on the supply line and a significant area for a high-impedance resistive divider—which is common. Furthermore, this use of high-impedance resistive dividers limits the routing distance of bias lines for the cascode transistors (or comes with power consumption disadvantages). This can necessitate multiple instances of bias generators, further increasing the area requirement.

[0030] The present disclosure proposes a new approach for controlling current flow between the voltage line VL and the electronic circuit 190. In particular, the proposed approach effectively combines the voltage monitoring system and the voltage isolation system into a single component. Specifically, the reset control system is modified to generate the control signal in response to the digital representation of the voltage(s) on the supply line(s) generated by the voltage monitoring system 120. Thus, the generation of the control signal is performed in response to the processing of the monitored voltage(s) in the digital domain, rather than analog domain processing of the voltage(s) on the supply line(s).

[0031] The proposed approach thus provides a voltage isolation circuit capable of performing these two functions within a single integrated system, thereby reducing the complexity, required chip area, and power consumption of the microchip. Existing solutions, such as the one previously exemplified, relied on separate systems for voltage monitoring and power domain isolation, resulting in increased chip area and power consumption.

[0032] This approach also reduces, if necessary, the number of circuits required to provide high-voltage protection.

[0033] The proposed system also overcomes many of the disadvantages of the known analog-based approach described above by switching to a digital-based approach.

[0034] Fig. Figure 2 presents a proposed voltage isolation circuit 200 for use in a microchip. The voltage isolation circuit 200 is designed to control, within the microchip, the flow of power from a voltage line VL to an electronic circuit 290. The voltage isolation system includes a voltage isolation circuit 210, a voltage monitoring system 220, and a reset control system 230.

[0035] The voltage isolation circuit 210 is configured to control power flow between the voltage line VL and the electronic circuit 290 in response to a control signal SC. This control can be achieved by enabling or disabling current flow between the voltage line and the electronic circuit 290, with the current flow in Fig. 2 is shown using a dashed line.

[0036] For example, the voltage isolation circuit 210 can include one or more level shifters for performing a level shifting operation between the voltage line VL and the electronic circuit 290. Each level shifter can have an enable / disable functionality, as described previously.

[0037] The voltage monitoring system 220 is configured to generate a digital representation of the voltage on a supply line VS1 (e.g., for the electronic circuit 290). This digital representation provides a measure of the voltage level on the supply line VS1 in a format suitable for digital processing. Specifically, the voltage monitoring system 220 includes an analog-to-digital converter 221 configured to generate the digital representation of the voltage on the supply line VS1. As a simple example, the voltage monitoring system 220 can include an analog-to-digital converter (ADC) that receives the voltage from the supply line VS1 as an input (e.g., via a sensing line) and generates the digital representation of the received voltage as an output.

[0038] The reset control system 230 receives and monitors the digital representation of the voltage on the supply line VS1 from the voltage monitoring system 220, for example, via a digital communication line or the like. The reset control system 230 is configured to provide the control signal to the voltage isolation circuit 210 and thereby controls the operation of the voltage isolation circuit 210. In this way, the reset control system makes control decisions based on digitized voltage information instead of analog comparisons.

[0039] In response to a microchip startup (which, for example, leads to a startup of the reset control system 230), the reset control system 230 initially controls the voltage isolation circuit 210 using the control signal to prevent power flow from the voltage line VL to the electronic circuit 290. This helps to avoid or significantly reduce the risk of problems or errors during the startup process.

[0040] After startup, the reset control system 230 is configured to authorize the voltage isolation circuit 210 to allow power flow from the voltage line VL to the electronic circuit 290 only when one or more predetermined criteria are met. Specifically, the reset control system 230 is configured to authorize the voltage isolation circuit to allow power flow from the voltage line VL to the electronic circuit 290 in response to each of the first predetermined criteria being met after the microchip has started.

[0041] The first or several predetermined criteria include at least one criterion that the digital representation of the voltage on the supply line VS1 (any of) fulfills one or more second predetermined criteria. As will be exemplified later, these second predetermined criteria may relate to voltage stability, voltage magnitude / level, and / or other properties that can be derived from the digital representation of the voltage.

[0042] For example, the second predetermined criterion may include at least one criterion that the digital representation of the voltage on the supply line indicates that the voltage on the supply line has stabilized.

[0043] By way of example, a voltage on the supply line can be considered stable when the digital voltage display indicates that the voltage on the supply line has not changed significantly for a predetermined period, i.e., remains within a tolerance range. In this way, the reset control system is able to ensure that the voltage on the supply line VS1 has stabilized before power is allowed to flow to the electronic circuit 290 from the voltage line VL. This helps to reduce the risk of a potential problem when supplying an unstable voltage to sensitive components, such as the unintentional triggering of one or more functions of the electronic circuit 290.

[0044] In some examples, the predetermined period can be greater than 5 µs but less than 100 µs, e.g., 10 µs or 25 µs. The predetermined period can be selected based on the specific characteristics of the power supply line, the voltage line, and / or the microchip, such as the expected settling time of the power supply line during startup.

[0045] In some examples, it can be determined that the voltage on supply line VS1 has not changed significantly in response to the fact that the difference between the maximum and minimum voltage (within the predetermined time period) does not exceed a predetermined percentage of the maximum or minimum voltage. The predetermined percentage could, for example, be 10%, 5%, 2%, or any other suitable value.

[0046] As another example, the voltage on supply line VS1 can be considered steady-state when the digital representation of the voltage on supply line VS1 indicates that the rate of change of the voltage on supply line VS1 is below a predetermined threshold. This criterion helps to ensure that the voltage is relatively stable. For example, the reset control system can monitor the rate of change of the voltage over a specified time window and control the control signal to allow power flow (from the voltage line VL to the electronic circuit 290) only when this rate falls below a defined threshold, e.g., 1% change per microsecond.

[0047] In some examples, the second predetermined criteria may include at least one criterion indicating that the digital representation of the voltage on the supply line VS1 shows that the voltage on the supply line exceeds a predetermined voltage. The predetermined voltage may be a minimum desired voltage level for the supply line, which can be defined in advance (e.g., representing an expected magnitude of the voltage level for the supply line). In this way, the voltage isolation system is able to prevent a current from flowing from the supply line to the electronic circuit 290 until the supply voltage has violated a minimum threshold.

[0048] In other examples, the second predetermined criteria can include at least one criterion indicating that the digital representation of the voltage on the supply line specifies that the voltage on the supply line does not exceed a second predetermined voltage. The second predetermined voltage can be a maximum desired voltage level for the supply line, which can be defined in advance (e.g., representing a permissible maximum voltage level for the supply line). In this way, the voltage isolation system is able to prevent power flow to the electronic circuit 290 from the supply line when the voltage on the supply line exceeds a safe operating range.This helps to protect the electronic circuit 290 from possible damage due to overvoltage conditions and / or to reduce the risk of incorrect signals being interpreted by the electronic circuit 290.

[0049] A wide variety of other suitable examples of second predetermined criteria will be obvious to the person skilled in the art.

[0050] Another example of a suitable first predetermined criterion is a criterion that a voltage from one or more additional supply lines VS2 each fulfills one or more further predetermined criteria. These further predetermined criteria can effectively mirror the second predetermined criteria applied to the (primary) supply line VS1.

[0051] Thus, the reset control system can receive and monitor a digital representation of a voltage on each of one or more additional supply lines, such as a second supply line VS2, in a manner similar to that described for supply line VS1.

[0052] In some examples, the voltage monitoring system 220 can be configured to generate the respective digital representation of a voltage on each of the one or more additional supply lines, such as the second supply line VS2.

[0053] In some examples, the reset control system 230 can receive a respective digital representation(s) of a voltage on each of the one or more additional supply lines via a digital input line DI1, e.g., from an element or component outside the voltage isolation system 200. For example, the digital input line DI1 can be connected to one or more digital output lines of one or more other voltage isolation systems.

[0054] Although only a single additional supply line VS2 and a single digital input line DI1 in Fig. As shown in Figure 2, the person skilled in the art will recognize that in practice the microchip may include a multitude of additional supply lines, e.g., a supply line for each power domain in the microchip, and / or a multitude of additional digital input lines.

[0055] Accordingly, the reset control system 230 can be configured to authorize the voltage isolation circuit to allow power flow from the voltage line VL to the electronic circuit 290 only when the digital representations of the voltages on both the primary supply line VS1 and on one or more additional supply lines VS2 meet their respective predetermined criteria.

[0056] Thus, one or more of the first criteria may include a criterion that the voltage on the supply line meets one or more of the second predetermined criteria, and a criterion that the voltage on each of the one or more further supply lines meets their respective predetermined criteria.

[0057] As mentioned previously, the further predetermined criteria for each additional supply line may include similar conditions to those described for the second predetermined criteria.

[0058] For example, the further predetermined criteria may include a criterion that the digital representation of the voltage on the further supply line indicates that the voltage of the further supply line has settled, using similar settling criteria as described for the supply line.

[0059] As another example, the further predetermined criteria can include a criterion that the respective digital representation of the voltage on the respective further supply line indicates that the voltage exceeds a predetermined minimum voltage level, e.g. specific to that supply line.

[0060] As yet another example, the further predetermined criteria can include a criterion that the respective digital representation of the voltage on the respective further supply line indicates that the voltage does not exceed a predetermined maximum voltage level, e.g. specific to this supply line.

[0061] A wide variety of other suitable examples for the further predetermined criteria will be readily obvious to the person skilled in the art.

[0062] This approach effectively configures the reset control system to ensure that relevant power supplies in the system have reached stable and / or appropriate levels before power is allowed to flow from the voltage line VL to the electronic circuit 290. This approach aims to prevent problems that could arise from inconsistent or inappropriate voltage levels across different power domains within the microchip.

[0063] In some of the approaches described above, such as some examples of the second predetermined criteria, the voltage monitoring system 230 monitors the digital representation of the voltage on the supply line from the voltage monitoring system over a predetermined period. Therefore, there may be a need to provide a clock source to accurately track the predetermined period.

[0064] In some examples, the voltage isolation circuit includes a dedicated clock source 235 configured to generate a clock signal for a clock line CLK connected to the reset control system 230. This clock source can be a crystal oscillator, a ceramic resonator, or any other suitable example of a clock source.

[0065] In other examples, the voltage isolation circuit includes a clock line CLK, which is connected to the reset control system 230 and to an external clock source carrying an (external) clock signal. This approach reduces the area requirement, the overall power consumption, and facilitates microchip-wide timing coordination.

[0066] The clock signal, whether generated internally or received externally, can be used by the reset control system to sample the digital representation of the voltage at regular intervals. This sampling process allows the reset control system to accurately measure time-dependent criteria, such as the elapsed time of a predetermined period and / or voltage change rates.

[0067] In some examples, the voltage monitoring system can integrate the clock signal into its analog-to-digital conversion process. For instance, the analog-to-digital converter can use the clock signal to determine its sampling rate.

[0068] To ensure reliable operation, the voltage isolation system may include mechanisms to verify the presence and stability of the clock signal. This may include a clock detection circuit (e.g., in the form of a counter or watchdog timer) that monitors the clock signal and alerts other components if the clock becomes unstable or stops.

[0069] In some examples, as through Fig. As shown in Figure 2, the voltage isolation system further comprises a reference voltage generator 240, which is configured to generate a reference voltage. The voltage monitoring system is configured to generate the digital representation of the voltage on the supply line with respect to the reference voltage.

[0070] As a simple example, the voltage monitoring system can include an analog-to-digital converter (ADC) that receives the voltage from the supply line VS1 as an input (e.g., via a sensing line). The ADC uses the reference voltage (generated by the reference voltage generator) as a reference for the conversion, allowing it to measure the voltage on the supply line VS1 relative to the reference. The output of the ADC can be a digital value representing the measured voltage, i.e., a digital representation of the voltage on the supply line VS1.

[0071] A reference voltage generator in the voltage isolation system serves to provide a stable reference point for measuring the voltage on the supply line VS1 and, if present, on the additional supply line VS2. This reference voltage thus acts as a baseline against which the voltage on the supply line VS1 (or, if present, on the additional supply line VS2) can be accurately compared and digitized.

[0072] The reference voltage generator 240 can be implemented using a bandgap reference, which provides improved stability over temperature variations.

[0073] In some examples, the reference voltage generator can be powered by the voltage on the supply line. This eliminates the need for a separate power supply for the reference voltage generator.

[0074] In some examples, the reference voltage generator can be extended by additionally including a power-on-reset (POR) generator. This extension can improve the reliability and functionality of the voltage isolation system, particularly during startup conditions or when power supplies are in a faulty state.

[0075] The POR generator can be configured to monitor the supply line voltage and generate a reset signal if this voltage falls below a predetermined threshold. Specifically, the POR generator can keep the reference voltage generator in a reset state during startup or when power supplies are invalid. This prevents the reference voltage generator from producing potentially faulty or unstable reference voltages that could lead to incorrect voltage measurements or system malfunctions. Once the supply line voltage reaches a stable and sufficient level, the POR generator can release the reset signal, allowing the reference voltage generator to resume normal operation.

[0076] The existing voltage isolation system ( Fig. 1) Relies on one or more threshold levels defined for analog comparators (usually bandgap-based). The accuracy of this analog solution therefore defines the performance of the voltage isolation system. By switching to the proposed solution, the bandgap generator only needs to cover one valid ADC operation. The actual accuracy for the voltage isolation is therefore derived from the ADC output, significantly improving the accuracy of the voltage isolation.

[0077] In some examples, such as in Fig. As shown in Figure 2, the voltage isolation system further comprises a high-voltage protection circuit 250, which is connected between the supply line VS1 and the voltage monitoring system 221. Although in Fig. 2 not shown, the voltage isolation system may (further) include one or more additional high-voltage protection circuits connected between the supply line VS1 and one or more other respective components of the voltage isolation system (such as between the supply line VS1 and the voltage isolation circuit 210 (e.g. the level shifter(s)) or the supply line VS1 and the reference voltage generator 240).

[0078] Examples of suitable high-voltage protection circuits are known in the prior art, such as those that use a cascode of (stacked) transistors to distribute voltage load and a suitably configured bias arrangement (e.g., a voltage divider).

[0079] The proposed approach, which effectively integrates voltage isolation and voltage monitoring functionality into a single system, advantageously reduces the number of high-voltage protection circuits required by the entire microchip, as multiple voltage protection circuits (e.g., one for each system) are effectively combined into a single block, thereby saving area and static current on the supply line VS1.

[0080] In some examples, the voltage monitoring system 100 includes a digital output line DO1 configured to provide a digital signal derived from the digital representation of the voltage to an element outside the voltage isolation system.

[0081] In some examples, the digital signal on the digital output line DO1 carries the digital representation of the voltage on the supply line VS1. In this way, the digital representation of the voltage on the supply line VS1 can be provided to an element outside the voltage isolation system.

[0082] In some examples, the voltage monitoring system 200 may include a digital filtering system 260. The digital filtering system is configured to receive the digital representation of the voltage (on the supply line VS1) from the voltage monitoring system, process this digital representation using one or more digital filters, and provide a filtered digital representation of the voltage as the digital signal on the digital output line. In this way, a filtered version of the digital representation of the voltage on the supply line VS1 can be provided to an element outside the voltage isolation system.

[0083] Various types of digital filters can be used in the digital filtering system. These can include low-pass filters, high-pass filters, band-pass filters, or more complex filter designs such as Kalman filters. The choice of filter type and parameters depends on the specific use case.

[0084] Fig. Figure 3 schematically represents a microchip 300 that uses one or more proposed voltage isolation systems, e.g., a plurality of proposed voltage isolation systems.

[0085] In particular, the microchip 300 includes a variety of voltage isolation systems 310, 320, 330. Each voltage isolation system 310, 320, 330 is configured to control a power flow from a respective supply line 311, 321, 331 to a respective electronic circuit 312, 322, 332.

[0086] Each supply line can be designed to carry a different voltage, e.g., a different voltage level. Thus, each voltage isolation system 310, 320, 330 and / or each electronic circuit 312, 322, 332 can be configured to function or operate in a different power domain.

[0087] Each voltage isolation system is designed as previously described, e.g., with reference to Fig. 2. In particular, each voltage isolation system is configured to provide a digital signal at a respective digital output line DO1, DO2, DO3, which is derived from the digital representation of the voltage at the respective supply line.

[0088] The microchip 300 further includes a power management system 390, which is connected to the digital output line of each voltage isolation system. The power management signal therefore effectively receives a (e.g., filtered) digital representation of the voltage on each supply line 311, 321, 331.

[0089] The 390 power management system can be configured to control the voltage on the respective supply line of each voltage isolation system in response to the digital signal provided by the voltage isolation system. Specifically, the microchip can include one or more power supplies and / or converters that generate the voltage(s) on each supply line 311, 321, 331. The 390 power management system can control the operation of each power supply and / or converter to control the voltage generated on each power supply. Exemplary power supplies and / or converters are well known in the prior art, such as those that convert a mains power supply to a desired voltage.

[0090] The proposed approach effectively provides a distributed voltage monitoring scheme for the 390 power management system, eliminating the need to route sensing lines directly from each supply line to the power management system. Instead, a digital representation of the voltage on each supply line can be generated by a dedicated voltage isolation system located in close proximity to the supply line. This significantly reduces power consumption, electromagnetic interference, and / or signal noise in the microchip.

[0091] It was previously explained how a reset control system can be configured to use a respective digital representation of a voltage on each of one or more additional supply lines.

[0092] In some variants, the voltage isolation system is configured to receive a digital representation of a voltage on each of the one or more additional supply lines from one or more other voltage isolation systems and / or the Power Management System 390. The voltage isolation system's reset control system can process the digital representation of each of these voltages using any previously described approach. As previously exemplified, the reset control system can use the received digital representations of voltages on the supply line and, optionally, one or more other supply lines as part of its criteria for allowing power flow. This approach ensures that multiple supply lines meet certain conditions before a single system allows power flow to its associated electronic circuitry.

[0093] Thus, in some examples, each voltage isolation system can be configured to include only a single voltage monitoring system for a single supply line. In this way, each voltage isolation system is responsible for monitoring and controlling the power flow from a single supply line to its associated electronic circuitry.

[0094] Furthermore, the voltage isolation systems can be interconnected to share information about the voltages they monitor. Specifically, each voltage isolation system can be configured to receive a digital representation of the voltage it monitors from any one or more other voltage isolation systems.

[0095] This digital communication between the voltage isolation systems can be implemented through a communication network or bus that allows the voltage isolation systems to exchange digital information.

[0096] In some examples, digital communication is coordinated or routed by another system on the microchip, such as the Power Management System 390 (which receives information about the voltage on each supply line, thus providing a more efficient system for routing information). In this way, each voltage isolation system can have a digital output line that provides its monitored voltage information and one or more input lines to receive voltage information from other systems and / or the Power Management System.

[0097] The present disclosure also proposes an improved approach for performing voltage monitoring. In particular, the present disclosure proposes an approach in which a master voltage monitor identifies a fault in a voltage reference generated by a first voltage reference generator of the same type as a voltage reference generator of each of one or more voltage isolation systems. This identified fault is used to correct a fault in a voltage monitored by the voltage monitoring system of the voltage isolation system.

[0098] Fig. Figure 4 represents section 400 of a proposed microchip, which includes a variant of the voltage isolation system.

[0099] The depicted section 400 comprises at least one voltage isolation system 200, as previously described; here, a single voltage isolation system. Optional components of the voltage isolation system (or systems) 200 are not shown for clarity, but may be included in some variants.

[0100] Thus, the voltage isolation system 200 comprises a voltage isolation circuit 210, a voltage monitoring system 220, and a reset control system 230. For the purposes of this approach, the voltage isolation system 200 further comprises a reference voltage generator 240 configured to provide a reference voltage V R to generate. The voltage monitoring system 220 is configured to generate a digital representation of the voltage on a supply line VS1 with respect to the reference voltage V. R to produce.

[0101] For the sake of clarity, only a single voltage isolation system 200 is shown, although in practice the microchip may include a variety of voltage isolation systems, e.g., a single voltage isolation system, two voltage isolation systems, three voltage isolation systems, four voltage isolation systems, or more than four voltage isolation systems. In particular, the voltage monitoring system may include one voltage isolation system for each power domain of the microchip.

[0102] The microchip 400 also includes a master voltage monitor 410, which includes a first master reference voltage generator 411, which provides a first master reference voltage V MR1 generated. The first master voltage generator 411 also includes a fault detection system 412.

[0103] The fault detection system 412 is configured to determine at least one digital fault. In this context, a digital fault is a digital representation in response to a fault measure of the first master reference voltage. Suitable examples of digital faults that can be determined by the fault detection system are provided later in this disclosure.

[0104] The reference voltage generator 240 (of each voltage isolation circuit 200) is of the same type as the first master reference voltage generator (i.e., it is of the first type) to ensure similar fault characteristics.

[0105] In this context, "same type" refers to the reference voltage generator and the first master reference voltage generator being of the same design or configuration. This means they are constructed using similar circuit topologies, components, and principles, resulting in comparable performance characteristics, particularly regarding their response to environmental factors such as temperature changes. Similarly, different types of reference voltage generators (e.g., the first and second type—which are referred to later in this disclosure) have different designs or configurations, meaning they are constructed using different circuit topologies, components, and / or principles.

[0106] Each voltage isolation system is thermally coupled to the master voltage monitor. This thermal coupling can be achieved by using a common heat sink or other thermal management system. Thus, since the first master reference voltage generator 411 of the master voltage monitor 410 and the reference voltage generator(s) 240 of the voltage isolation system(s) 200 are of the same type, a fault in the first master reference voltage due to thermal effects is similar to a fault in each reference voltage due to thermal effects.

[0107] As previously noted, if there are multiple voltage isolation systems, each system can be designed or configured to monitor a voltage for a different power domain of the microchip. In this way, the supply line for different voltage isolation systems can be configured to carry a power signal for one of a variety of power domains.

[0108] Each voltage isolation system 200 is configured to also include a fault correction system 490, which is configured to correct at least one fault in the digital representation of the voltage on the supply line VS1 using the at least one digital fault determined by the master voltage monitor. Specifically, each voltage isolation system 200 can include its own fault correction system 490 integrated into the voltage isolation system.

[0109] The error correction system receives the at least one digital error from the error detection system (the master voltage monitor), for example, via a communication bus 495. The error correction system then uses the received at least one digital error to correct the corresponding digital representation of the voltage on the supply line. Some exemplary approaches for correcting this digital representation of the voltage on the supply line are provided later in this disclosure.

[0110] It is evident that the error correction system operates in the digital domain and can be implemented using one or more (micro)processors or similar devices. Thus, the error correction system can comprise one or more processors or processing systems for processing the digital representation of the voltage on the supply line in order to generate a corrected measured voltage.

[0111] In the example shown, the fault correction system is depicted as a separate component from the voltage monitoring system and / or the reset control system. In practice, these modules and / or systems can be integrated into a single processing system.

[0112] It has been recognized that a significant source of error in generating a digital representation of a (measured) voltage is an error in the reference voltage against which the measured voltage is defined. The present disclosure provides a number of techniques for addressing this problem in order to improve the accuracy of generating a digital representation of a voltage on the supply line (i.e., performing a voltage measurement). In particular, the present disclosure identifies a variety of types of errors in the reference voltage(s) used to generate any voltage measurement and proposes techniques for at least partially mitigating these errors.

[0113] One type of error in a reference voltage results from the fact that the reference voltage V R generated using a less accurate, reliable, or robust reference voltage generator.

[0114] To overcome this problem, at least partially, the master voltage monitor 410 can include a second reference voltage generator 413 of a second type that is less sensitive to temperature changes than the first type (e.g., more accurate or robust than the first type). This second reference voltage generator 413 produces a second master reference voltage V. MR2 The fault detection system 412 of the master voltage monitor 410 can then be used as the first digital fault EG. LOC a digital representation of an error between the first master reference voltage V MR1 and the second master reference voltage V MR2 determine.

[0115] The first type of reference voltage generator is less robust (e.g., more sensitive to thermal effects or temperature drift) and / or less accurate than the second type of reference voltage generator.

[0116] The first type of reference voltage generator can be, for example, a bandgap voltage reference; and the second type of reference voltage generator can be a high-precision bandgap voltage reference. Examples of high-precision bandgap voltage references are well known in the prior art, such as those described by Zhou, Ze-Kun et al., "A resistorless high-precision compensated CMOS bandgap voltage reference," IEEE Transactions on Circuits and Systems I: Regular Papers 66.1 (2018): 428-437, and / or Xing, Xinpeng, Zhihua Wang, and Dongmei Li, "A low voltage high precision CMOS bandgap reference," Norchip 2007, IEEE 2007.

[0117] In some examples, the second type of reference voltage generator has a larger footprint, i.e., occupies a larger surface area, than the first type of reference voltage generator. A larger surface area is generally required by more sophisticated (and accurate) reference voltage generators. Thus, using the first type of reference voltage generator in the voltage isolation system reduces the system's footprint while still allowing for the correction of errors (faults) in the reference voltage generated by the system's reference voltage generator.

[0118] The first digital error is then transmitted to the error correction system, for example via the communication bus. The error correction system (e.g., each error correction system) then uses this first digital error to correct the reference voltage(s).

[0119] Since the first master reference voltage generator and the reference voltage generator(s) of each voltage isolation system are of the same type, it can similarly be assumed that any fault in the first master reference voltage generator will also occur in the reference voltage generator, in particular any faults resulting from thermal effects or temperature drift.

[0120] The first digital error can be expressed as a quotient of the second master reference voltage V. MR2 and the first master reference voltage V MR1 , especially V MR2 / V MR1 , defined. In such an example, the error correction system can correct the first type of error in the digital representation of the voltage on the supply line by subtracting each measured voltage from this quotient (V). MR2 / V MR1) multiplied. Other examples of defining an error and carrying out an appropriate correction will be obvious to the person skilled in the art.

[0121] By using a more accurate second master reference voltage generator 413 in the master voltage monitoring 410 and distributing the resulting error information, the proposed approach is able to compensate for inaccuracies in the less accurate reference voltage generator 240 used in each voltage isolation system 200. This approach allows the use of simpler, more cost-effective reference voltage generators in the voltage isolation systems while still maintaining high overall accuracy in voltage measurements.

[0122] A second type of fault in a reference voltage results from a fixed ground fault EG. HPin the second master reference voltage. This applies even if the second master reference voltage is generated using an accurate or reliable reference voltage generator (e.g., a high-precision bandgap reference).

[0123] To at least partially overcome this second type of error, the error correction system can be configured to store a second digital error representing an error in the second master reference voltage. The error correction system can then be configured to use this stored second digital error to correct each measured voltage.

[0124] One approach to defining the second digital error is to use a predetermined master calibration voltage V. C to provide on a master calibration voltage line 415 and to compare this voltage with respect to the second master reference voltage V MR2to measure. This predetermined master calibration voltage can be known to the fault detection system in advance (e.g., pre-programmed into the fault detection system or defined by a user / operator).

[0125] The predetermined master calibration voltage can be provided, for example, by an external high-precision voltage source connected to the voltage monitoring system and / or the system-on-chip (e.g., during a calibration phase). This provides a highly accurate calibration voltage.

[0126] The master voltage monitor 410 can determine a digital representation of the voltage on the master calibration voltage line relative to the second master reference voltage. The second digital error can then be defined as a response to a difference between the predetermined master calibration voltage and the digital representation of the measured voltage, which can then be passed to the error correction system 490 of each voltage isolation system 200. The second digital error represents the fixed ground error in the second master reference voltage, which may be due to offset voltages or other systematic errors in the voltage measurement system.

[0127] In some examples, the first master reference voltage generator 411 and / or the reference voltage generator 240 (of each voltage isolation system 200) are configured to generate their respective reference voltages using a chopper technique. This helps to ensure that temperature drift and / or temperature inaccuracies of these reference voltage generators are the same (so that the first digital error is accurately representative of errors due to temperature drift in each reference voltage generator—as well as the first master reference voltage generator).

[0128] The second digital error EG HP can be expressed as a ratio / quotient of the predetermined master calibration voltage V C and the digital representation of the voltage on the master calibration voltage line V CML , especially V C / V CML, defined. In such an example, the error correction system can correct the second error type in each measured voltage by applying this quotient (V) to each measured voltage. C / V CML ) multiplied. Other examples of defining an error and carrying out an appropriate correction will be obvious to the person skilled in the art.

[0129] It goes without saying that correcting the first type of error (EG) LOC ) and the second type of error (EC HP ) also serves to detect any fixed / ground fault in the first master reference voltage V MR1 to correct.

[0130] In some examples, the master calibration voltage line can be the supply line for providing power to the master voltage monitor, e.g., to provide power to at least the fault detection system.

[0131] A third type of fault in a reference voltage results from a fixed / ground fault EG. SAT in the reference voltage V R , which is generated by the reference voltage generator 240 of each voltage isolation system 200.

[0132] To at least partially overcome this third type of fault, the fault correction system 490 can be configured to provide a third digital fault EG for the respective voltage insulation system 200. SAT to store a fixed / ground error in the reference voltage V R This represents the error correction system 490, which can be configured accordingly to store the third digital error EG. SAT to use in order to correct any measured voltage.

[0133] One approach to defining the third digital fault is to assign a predetermined calibration voltage V to each voltage isolation system 490. SCto provide a calibration voltage (CVL) for the voltage isolation system 200. Each voltage isolation system, in particular the voltage monitoring system, can measure the voltage on its respective supply line relative to its reference voltage. Each predetermined calibration voltage can be known to the fault correction system in advance (e.g., pre-programmed into the fault correction system or defined by a user / operator).

[0134] The predetermined calibration voltage(s) can be provided, for example, by an external high-precision voltage source connected to the voltage monitoring system and / or the system-on-chip (e.g., during a calibration phase). This provides a highly accurate calibration voltage.

[0135] Every third digital error can then be defined as a response to, for each voltage isolation system, the difference between the predetermined calibration voltage and the digital representation of the measured voltage on the calibration voltage line. Every third digital error represents the fixed ground error in the corresponding reference voltage. The defined third digital error can then be stored by the 490 voltage correction system for future use.

[0136] For each voltage isolation system, the corresponding third digital error can be expressed as a ratio / quotient of the predetermined calibration voltage V. SC and the digital representation of the voltage V CSL on the calibration voltage line, in particular V SC IV CSL, defined. In such an example, the error correction system can correct the third error type in each measured voltage by subtracting the corresponding quotient (V) from each measured voltage. SC / V CSL ) multiplied. Other examples of defining an error and carrying out an appropriate correction will be obvious to the person skilled in the art.

[0137] In some examples, for each voltage isolation system, the calibration voltage line CVL can be the power line for supplying energy to the voltage isolation system, e.g., the supply line VS1.

[0138] In some examples, where more than one voltage isolation system is present, the calibration voltage lines of all voltage isolation systems can be electrically connected. This allows the same predetermined calibration voltage to be shared by each voltage isolation system.

[0139] In examples where both a master calibration voltage and a calibration voltage for each voltage isolation system are provided, the calibration voltage line of each voltage isolation system can be electrically connected to the master calibration voltage line of the master voltage monitor, so that each predetermined calibration voltage V SC the same as the predetermined master calibration voltage V C is.

[0140] The preceding examples provide exemplary approaches to determining three different digital faults (for each voltage insulation system), namely a first digital fault EG LOC , a second digital error EC HP and a third digital error EC SATThe first and second digital faults are determined using the master voltage monitor and are common to all voltage isolation systems. The third digital fault is determined separately using each voltage isolation system, so that every third digital fault is EG. SAT is specific to a particular voltage insulation system.

[0141] If each digital fault is represented by a ratio, the correction of the voltage monitored by the voltage monitoring system of the voltage isolation system can be carried out by multiplying the voltage by each specific digital fault (for the corresponding voltage isolation system).

[0142] Therefore, a corrected voltage VSATC can be calculated using the following equation: VSATC=VSAT.EGLOC.EGHP.EGSAT=VSAT.EGCOM where V SATThe voltage is what is monitored by the voltage monitoring system of the voltage isolation system, EC LOC The first digital error is, EC HP The second digital error is, EC SAT the third digital error is and EC COM the product of the first digital error, the second digital error, and the third digital error.

[0143] In some examples, the master voltage monitor can be integrated into a voltage isolation system. Thus, the master voltage monitor can further be configured to monitor the voltage on a master voltage line and control the power flow between the master voltage line and other electronic circuits. This effectively performs the functions of a voltage isolation system in addition to its role of generating at least one digital fault. This dual functionality can be achieved by integrating suitable additional components and circuitry within the master voltage monitor.

[0144] For example, the master voltage monitor may include a master voltage isolation circuit, a master voltage monitoring system, and a master reset control system, which may function in a similar manner to the corresponding components of the voltage isolation system.

[0145] The master voltage monitor may further include a master error correction system to correct the measured voltage from the master voltage line using similar principles and techniques to those previously disclosed. This may involve using the digital errors determined by the error detection system to correct any inaccuracies in the measured voltage from the master voltage line.

[0146] An error in the measured voltage from the master voltage line can be corrected differently depending on which master reference voltage is used for measurement by the master voltage monitoring system. For example, if the master voltage is relative to the first master reference voltage (V1), the error can be corrected using the first master reference voltage (V2). MR1 ) is measured, both the fixed mass error (EC) must be measured, HP ) as well as the local error (EC LOC) can be corrected. However, if the master voltage is in relation to the second master reference voltage (V) MR2 ) is measured, only the fixed mass error (EC) needs to be measured HP ) will be corrected.

[0147] By integrating this additional voltage monitoring capability, the master voltage monitor can provide voltage measurements for its own power domain, thus providing a more efficient microchip.

[0148] In addition to the examples described above, the following examples are disclosed. Example 1. Voltage isolation system for controlling, in a microchip, a power flow from a voltage line to an electronic circuit, wherein the voltage isolation circuit comprises the following: a voltage isolation circuit configured to control power flow between the voltage line and the electronic circuit in response to a control signal; a voltage monitoring system configured to generate a digital representation of the voltage on a supply line for the electronic circuit; and a reset control system configured to: Providing the control signal to the voltage isolation circuit and: Receiving and monitoring the digital representation of the voltage on the supply line from the voltage monitoring system, the reset control system is further configured, in response to a start of the microchip, to: initial control, using the control signal, of the voltage isolation circuit to prevent power flow from the voltage line to the electronic circuit; and as a response to each of one or more initial predetermined criteria being met after the microchip has been started, authorizing the voltage isolation circuit to allow power flow from the voltage line to the electronic circuit, wherein one or more first predetermined criteria include a criterion that the digital representation of the voltage on the supply line satisfies each of one or more second predetermined criteria after the microchip has been started. Example 2. Voltage isolation system according to Example 1, wherein one or more of the second predetermined criteria include a criterion that the digital representation of the voltage on the supply line indicates that the voltage on the supply line is steady. Example 3. Voltage isolation system according to Example 1 or 2, wherein one or more of the second predetermined criteria include a criterion that the digital representation of the voltage on the supply line indicates that the voltage on the supply line exceeds a predetermined voltage. Example 4. Voltage isolation system according to any one of Examples 1 to 3, further comprising a reference voltage generator configured to generate a reference voltage, wherein the voltage monitoring system is configured to generate the digital representation of the voltage on the supply line with respect to the reference voltage. Example 5. Voltage isolation system according to Example 4, wherein the reference voltage generator is powered by the voltage on the supply line. Example 6. Voltage isolation system according to one of Examples 4 or 5, wherein the reference voltage generator is a bandgap reference. Example 7. Voltage isolation system according to one of Examples 1 to 6, wherein the voltage isolation circuit includes one or more level shifters for performing a level shifting operation between the voltage line and the electronic circuit. Example 8. Voltage isolation system according to one of Examples 1 to 7, further comprising a high-voltage protection circuit connected between the supply line and the voltage monitoring system. Example 9. Voltage isolation system according to any of Examples 1 to 8, wherein the voltage monitoring system includes a digital output line configured to provide a digital signal derived from the digital representation of the voltage to an element outside the voltage isolation system. Example 10. Voltage isolation system according to Example 9, wherein the voltage monitoring system includes a digital filter system configured to: to receive the digital representation of the voltage from the voltage monitoring system; to process the digital representation of the voltage using one or more digital filters to produce a filtered digital representation of the voltage; and as the digital signal to provide the filtered digital representation of the voltage on the digital output line. Example 11. Microchip, comprehensive: one or more voltage isolation systems according to one of examples 9 or 10; For each voltage isolation system: a corresponding electronic circuit and a corresponding supply line; and A power management system that is connected to the digital output line of each voltage isolation system and is configured to control the voltage on the respective supply line of the voltage isolation system for each voltage isolation system in response to the digital signal provided by the voltage isolation system. Example 12. Microchip according to Example 11, wherein each voltage isolation system operates in a different voltage supply domain. Example 13. Microchip according to Example 11 or 12, wherein: each voltage isolation system as exemplified in any of the examples 4 to 6; and The microchip includes a master voltage monitor that is communicatively coupled to each voltage isolation system via a communication bus, the master voltage monitor comprising: a first master reference voltage generator configured to generate a first master reference voltage, wherein the first master reference voltage generator is of a first type; and a fault detection system configured to determine as a digital fault a digital representation in response to a fault measure of the first master reference voltage, where for each voltage insulation system: the reference voltage generator is of the first type; and The voltage isolation system further comprises a fault correction system which is communicatively connected via the communication bus to the fault detection system of the master voltage monitor, wherein the fault correction system is configured to correct a fault in the digital representation of the voltage on the supply line using the digital fault. Example 14. Microchip according to Example 13, wherein the master voltage monitor fault detection system includes: a second master reference voltage generator configured to generate a second master reference voltage, wherein the second master reference voltage generator is of a second type that is less sensitive to temperature changes than the first type; and a digitization system configured to determine as a digital error a digital representation of a difference between the first master reference voltage and the second master reference voltage. Example 15. Microchip according to Example 14, wherein the fault detection system includes a master voltage measurement system configured to: to measure a digital representation of a voltage on a first supply line with respect to the first master reference voltage as the first master measurement voltage; and to measure a digital representation of the voltage at the first supply line relative to the second master reference voltage as the second master measurement voltage; and wherein The digitization system is configured to determine a digital representation as a digital error in response to a difference between the first master measurement voltage and the second master measurement voltage.

[0149] Although specific examples have been presented and described here, the person skilled in the art will recognize that a variety of alternative and / or equivalent implementations can replace the specific examples shown and described without altering the scope of protection of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention is limited only by the claims and their equivalents.

[0150] It should be noted that the systems, including their preferred embodiments, as described in this document, can be used alone or in combination with the other systems disclosed in this document. Furthermore, all aspects of the systems described in this document can be combined in any way. In particular, the features of the claims can be combined with one another in any manner.

[0151] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. A person skilled in the art will be able to implement various arrangements which, although not explicitly described or shown here, embody the principles of the invention and are contained within its spirit and scope of protection. Furthermore, all examples and embodiments described in this document are expressly intended primarily for illustrative purposes only, to assist the reader in understanding the principles of the proposed methods and systems. Moreover, all statements made herein that provide principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include their equivalents. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited non-patent literature

[0000] Zhou, Ze-Kun et al. “A resistorless high-precision compensated CMOS bandgap voltage reference.” IEEE Transactions on Circuits and Systems I: Regular Papers 66.1 (2018): 428-437

[0116] Xing, Xinpeng, Zhihua Wang and Dongmei Li. “A low voltage high precision CMOS bandgap reference.” Norchip 2007. IEEE, 2007

[0116]

Claims

[1] Voltage isolation system for controlling, in a microchip, a power flow from a voltage line to an electronic circuit, wherein the voltage isolation circuit comprises: a voltage isolation circuit configured to control power flow between the voltage line and the electronic circuit in response to a control signal; a voltage monitoring system configured to generate a digital representation of the voltage on a supply line for the electronic circuit; and a reset control system configured to: Providing the control signal to the voltage isolation circuit and: Receiving and monitoring the digital representation of the voltage on the supply line from the voltage monitoring system, the reset control system is further configured, in response to a start of the microchip, to: initial control, using the control signal, of the voltage isolation circuit to prevent power flow from the voltage line to the electronic circuit; and as a reaction to each of one or more initial predetermined criteria being met after the microchip has started, authorizes the voltage isolation circuit to allow power flow from the voltage line to the electronic circuit, wherein one or more first predetermined criteria include a criterion that the digital representation of the voltage on the supply line satisfies each of one or more second predetermined criteria after the microchip has been started. [2] Voltage isolation system according to claim 1, wherein one or more of the second predetermined criteria include a criterion that the digital representation of the voltage on the supply line indicates that the voltage on the supply line has stabilized. [3] Voltage isolation system according to claim 1 or 2, wherein one or more second predetermined criteria include a criterion that the digital representation of the voltage on the supply line indicates that the voltage on the supply line exceeds a predetermined voltage. [4] Voltage isolation system according to any one of claims 1 to 3, further comprising a reference voltage generator configured to generate a reference voltage, wherein the voltage monitoring system is configured to generate the digital representation of the voltage on the supply line with respect to the reference voltage. [5] Voltage isolation system according to claim 4, wherein the reference voltage generator is supplied with energy by the voltage on the supply line. [6] Voltage isolation system according to one of claims 4 or 5, wherein the reference voltage generator is a bandgap reference. [7] Voltage isolation system according to any one of claims 1 to 6, wherein the voltage isolation circuit comprises one or more level shifters for performing a level shifting operation between the voltage line and the electronic circuit. [8] Voltage isolation system according to any one of claims 1 to 7, further comprising a high voltage protection circuit connected between the supply line and the voltage monitoring system. [9] Voltage isolation system according to any one of claims 1 to 8, wherein the voltage monitoring system comprises a digital output line configured to provide a digital signal derived from the digital representation of the voltage to an element outside the voltage isolation system. [10] Voltage isolation system according to claim 9, wherein the voltage monitoring system comprises a digital filter system configured to: to receive the digital representation of the voltage from the voltage monitoring system; to process the digital representation of the voltage using one or more digital filters to produce a filtered digital representation of the voltage; and as the digital signal to provide the filtered digital representation of the voltage on the digital output line. [11] Microchip, comprising: one or more voltage isolation systems according to one of claims 9 or 10; For each voltage isolation system: a corresponding electronic circuit and a corresponding supply line; and a power management system that is connected to the digital output line of each voltage isolation system and is configured to control the voltage on the respective supply line of the voltage isolation system for each voltage isolation system in response to the digital signal provided by the voltage isolation system. [12] Microchip according to claim 11, wherein each voltage isolation system operates in a different voltage supply domain. [13] Microchip according to claim 11 or 12, wherein: any voltage isolation system as claimed in any one of claims 4 to 6; and The microchip includes a master voltage monitor that is communicatively coupled to each voltage isolation system via a communication bus, the master voltage monitor comprising: a first master reference voltage generator configured to generate a first master reference voltage, wherein the first master reference voltage generator is of a first type; and a fault detection system configured to determine as a digital fault a digital representation in response to a fault measure of the first master reference voltage, wherein for each voltage isolation system: the reference voltage generator is of the first type; and The voltage isolation system further comprises a fault correction system which is communicatively connected via the communication bus to the fault detection system of the master voltage monitor, wherein the fault correction system is configured to correct a fault in the digital representation of the voltage on the supply line using the digital fault. [14] Microchip according to claim 13, wherein the fault detection system of the master voltage monitor comprises: a second master reference voltage generator configured to generate a second master reference voltage, wherein the second master reference voltage generator is of a second type that is less sensitive to temperature changes than the first type; and a digitization system configured to determine as a digital error a digital representation of a difference between the first master reference voltage and the second master reference voltage. [15] Microchip according to claim 14, wherein the fault detection system comprises a master voltage measurement system configured to: to measure a digital representation of a voltage on a first supply line with respect to the first master reference voltage as the first master measurement voltage; and to measure a digital representation of the voltage at the first supply line relative to the second master reference voltage as the second master measurement voltage; and wherein The digitization system is configured to determine a digital representation as a digital error in response to a difference between the first master measurement voltage and the second master measurement voltage.

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