Vertical power transistor and method for fabricating a vertical power transistor

Abstract

Vertical power semiconductor transistor (200) with a drift zone (202) comprising a first semiconductor material, wherein p-doped regions (203) and n-doped regions (204) extend into the drift zone (202) from a surface of the drift zone (202), the p-doped regions (203) and the n-doped regions (204) being arranged laterally immediately alternating with each other, and a semiconductor heterostructure arranged above the drift zone (202), the semiconductor heterostructure comprising a second layer (206) comprising a second semiconductor material and a third layer (207) comprising a third semiconductor material, the third layer (207) being arranged on the second layer (206), and the first semiconductor material, the second semiconductor material, and the third semiconductor material being different, the first semiconductor material having a smaller band gap than the second semiconductor material, characterized in thatthat an electrically conductive intermediate layer (205) is arranged between the drift zone (202) and the semiconductor heterostructure.

Description

[0001] The invention relates to a vertical power transistor and a method for manufacturing a vertical power transistor. State of the art

[0002] Due to its high breakdown field strength, power semiconductor devices are preferably made from gallium nitride. Because of its low specific on-resistance, the vertical high electron mobility transistor (HEMT) represents an interesting implementation. This utilizes a two-dimensional electron gas at the junction of an AlGaN / GaN heterostructure as the channel region, as well as a GaN drift zone, thereby achieving very high channel mobility in vertical GaN transistors.

[0003] Due to its function, the vertical HEMT features a current aperture consisting of an n-doped region positioned between two p-doped regions. The process engineering implementation in GaN presents a significant challenge, particularly since the activation of the p-type species, introduced into specific regions via ion implantation, lies far above the decomposition temperature of GaN.

[0004] Furthermore, reverse operation of the vertical power transistor is very lossy. There are two possible current paths: one through the p-doped regions of the current aperture and the other through the channel region. In the first case, the current flows through the pn diode formed by the p-doped region and the drift zone. The losses arise from the large forward voltage due to the wide band gap of the gallium nitride and the high-resistance electrical contacts to the p-doped regions. In the second case, the current flows through the two-dimensional electron gas, which is significantly less lossy when the gate voltage is 0V, since the forward voltage is determined by the transistor's threshold voltage. However, a negative voltage is usually applied to the gate during turn-off to prevent unintentional turn-on.This negative voltage increases the forward voltage of the alternative current path, so that losses in reverse operation also increase significantly here.

[0005] The purpose of the invention is to overcome these disadvantages. Disclosure of the invention

[0006] A vertical power transistor comprises a drift zone with a first semiconductor material, wherein p-doped regions and n-doped regions extend laterally into the drift zone, alternating immediately with each other, starting from a surface of the drift zone. A semiconductor heterostructure is arranged above the drift zone, the semiconductor heterostructure comprising a second layer with a second semiconductor material and a third layer with a third semiconductor material, the third layer being arranged on top of the second layer. The first, second, and third semiconductor materials are different, with the first semiconductor material having a smaller band gap than the second semiconductor material. According to the invention, an electrically conductive intermediate layer is arranged between the drift zone and the semiconductor heterostructure.

[0007] The advantage here is that the losses in reverse operation of the power semiconductor device are low.

[0008] In a further training, the electrically conductive intermediate layer exhibits a dopant concentration greater than 1e19 cm^-3.

[0009] An advantage here is that the electrical contact between the transistor head, i.e. the layers above the current aperture, and the substructure consisting of current aperture, drift zone and substrate is low-resistance.

[0010] In a further embodiment, the electrically conductive intermediate layer comprises AlGaN, in particular in an Al0.25Ga0.75N composition.

[0011] The advantage here is that the connection between the n-doped regions of the current aperture and the second layer is low-resistance.

[0012] In a further development, the electrically conductive intermediate layer comprises a fourth layer and a fifth layer, with the fifth layer arranged on top of the fourth layer. The fourth layer consists of AlGaN, and the fifth layer has a gradual transition from an AlGaN composition to a GaN composition, with the GaN composition oriented towards the second layer.

[0013] The advantage here is that the number of interface defects and the conductor band mismatch are low.

[0014] In another embodiment, the second semiconductor material is GaN and the third semiconductor material is AlGaN. In other words, the semiconductor heterostructure comprises AlGaN / GaN.

[0015] The advantage here is that a two-dimensional electron gas can be formed between the second and third layers, but within the second layer, which has a high electron mobility.

[0016] In a further training course, the first semiconductor material covered is SiC.

[0017] The advantage here is that the current aperture can be generated using established SiC process technology.

[0018] The inventive method for manufacturing a vertical power transistor comprises generating a drift zone by means of epitaxy, wherein the drift zone comprises a first semiconductor material, generating p-doped regions and n-doped regions by means of ion implantation, wherein the p-doped regions and n-doped regions extend from a surface of the drift zone into the drift zone, are arranged laterally immediately alternating to each other and form a current aperture, and activating the p-doped regions and the n-doped regions of the current aperture by means of a high-temperature process.Furthermore, the method comprises generating an electrically conductive intermediate layer on the drift zone, and generating a semiconductor heterostructure on the electrically conductive intermediate layer, wherein the semiconductor heterostructure has a second layer with a second semiconductor material and a third layer with a third semiconductor material, wherein the third layer is arranged on the second layer, the first semiconductor material, the second semiconductor material and the third semiconductor material are different and the first semiconductor material has a smaller band gap than the second semiconductor material.

[0019] The advantage here is that the production costs are low.

[0020] Further advantages arise from the following description of exemplary embodiments or the dependent patent claims. Brief description of the drawings

[0021] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. These show: Fig. 1 a vertical HEMT from the state of the art, Fig. 2 a first embodiment of a vertical power transistor according to the invention, Fig. 3 a second embodiment of the vertical power transistor according to the invention, Fig. 4 a third embodiment of the vertical power transistor according to the invention, and Fig. 5 a method according to the invention for manufacturing a vertical power transistor.

[0022] Fig. Figure 1 shows a prior art vertical HEMT 100. The vertical HEMT 100 comprises a GaN substrate 101 on which a GaN drift zone 102 is arranged. Alternating p-doped GaN regions 103 and n-doped GaN regions 104 extend laterally from a surface of the drift zone 102 into the drift zone 102, forming a so-called stroma. A semiconductor heterostructure is arranged on the stroma above the GaN drift zone 102. The semiconductor heterostructure comprises a layer 106 of undoped GaN and an overlying layer 107 of undoped AlGaN. A two-dimensional electron gas forms at the transition or interface between the two layers in the undoped GaN layer 106. A p-doped region 108 is arranged on the undoped AlGaN layer 107.This ensures the normally-off operation of the vertical HEMT 100 by depleting the two-dimensional electron gas below the p-doped region. A gate electrode 109 is arranged on the p-doped region 108, forming a Schottky or Ohmic contact. A source electrode 110 is arranged above the gate electrode 109, with the gate electrode 109 and the source electrode 110 being electrically separated from each other by an insulating layer 111. A drain electrode 112 is arranged below the GaN substrate 101, enabling vertical current flow. In other words, in the prior art, both the transistor head and the substructure consisting of the current aperture, drift layer, and substrate comprise GaN.

[0023] Fig. Figure 2 shows a first embodiment of a vertical power transistor 200 according to the invention. The vertical power transistor 200 comprises a substrate 201 having a first semiconductor material. The first semiconductor material comprises, for example, SiC or Si. An n-doped drift zone 202, comprising the first semiconductor material, is arranged on the substrate 201. Starting from a surface of the n-doped drift zone 202, p-doped regions 203 and n-doped regions 204 extend into the n-doped drift zone 202. The p-doped regions 203 and the n-doped regions 204 are arranged alternately side by side. The p-doped regions 203 and the n-doped regions 204 form a current aperture. An electrically conductive intermediate layer 205 is arranged on the current aperture. It functions as an electrical connection between the transistor head and the substrate.A semiconductor heterostructure is arranged on the conductive intermediate layer 205. The semiconductor heterostructure comprises a second layer 206, which has undoped GaN, and a third layer 207, which is arranged on the second layer 206 and has undoped AlGaN. That is, it is an AlGaN / GaN heterostructure. Alternatively, the heterostructure can also include InGaN. In this case, the InGaN is arranged between the second layer 206 and the third layer 207. A p-doped region 208 is arranged on the semiconductor heterostructure, and a gate electrode 209 is arranged on the p-doped region 208. A source electrode 210 is arranged above the gate electrode 209, wherein the gate electrode 209 and the source electrode 210 are electrically separated from each other by an insulating layer 211. A drain electrode 212 is arranged below the substrate 201. In other words, the transistor head, i.e.The layers above the drift zone 202 and the substructure, i.e., current aperture, drift zone 202, and substrate 201, comprise different semiconductor materials. Preferably, the transistor head is made of GaN and the substructure of SiC. This means that the drift layer, which in the prior art consists of GaN, is replaced by SiC. As a result, the current aperture is also made of SiC. The electrical connection between the transistor head and the substructure is ensured via the conductive intermediate layer 205, and the pn diode for reverse operation is entirely implemented in SiC, thereby reducing losses.

[0024] Substrate 201, for example, has a dopant concentration greater than 1 e^18 1 / cm². 3 and the drift zone 202 has a dopant concentration between 5e15 1 / cm 3 and 1e17 1 / cm 3The p-doped region 203, for example, has a dopant concentration of between 1 e17 1 / cm². 3 and 1e19 1 / cm 3 and the n-doped region 204 has a dopant concentration between 1e17 1 / cm² 3 and 5e18 1 / cm 3 The conductive intermediate layer 205 has a dopant concentration greater than 1 × 10⁹ 1 / cm². 3 and the p-doped region 208 has a dopant concentration between 1e17 1 / cm² 3 and 1e19 1 / cm 3 on.

[0025] The electrical intermediate layer 205 comprises AlGaN, for example in an Al0.25Ga0.75N composition. Alternatively, the electrical intermediate layer 205 can comprise a stack of layers consisting of a fourth layer with AlGaN and a fifth layer exhibiting a gradual transition from AlGaN to GaN composition, with the pure GaN composition facing the GaN layer 206. The side of the electrically conductive intermediate layer 205 facing the SiC substrate 201 comprises AlGaN, preferably in the Al0.25Ga0.75N composition. This means that, for forward operation of the vertical power transistor 205, electrons flow with minimal loss from the two-dimensional electron gas through the conductive intermediate layer 205 and the n-doped region 204 of the current aperture into the drift zone 202. In reverse operation, the current flows through the pn diode, which is formed between the p-doped region 203 and the drift zone 202.

[0026] The vertical power transistor 200 is designed as a vertical HEMT.

[0027] Fig. Figure 3 shows a second embodiment of the vertical power transistor 300 according to the invention. The substructure of the Fig. 3 corresponds to the substructure made of Fig. 2. Here, the same posterior reference numerals denote identical features. The substructure comprises the substrate 301, the drift zone 302, as well as the p-doped regions 303 and the n-doped regions 304. They all have the same semiconductor material, preferably SiC. The conductive intermediate layer 305 is arranged on the current aperture or the drift zone 302. On the conductive intermediate layer 305 is an n-doped GaN layer 313 with a dopant concentration of 1 e^17 1 / cm². 3 and 1e19 1 / cm 3 arranged. On the n-doped GaN layer 313 is a p-doped channel layer 314 with a dopant concentration between 5e17 1 / cm². 3 and 1e19 1 / cm 3arranged. On the p-doped channel layer 314, a source layer 315 is arranged, which has a dopant concentration between 5e18 1 / cm². 3 and 1e19 1 / cm 3 The source layer 315 and the channel layer 314 are penetrated by a trench that terminates in the n-doped GaN layer 313. A gate electrode 316 is arranged within the trench, which contains a gate dielectric 317. An insulating layer 318 is arranged on the gate electrode 316, electrically separating it from the source electrode 319. The drain electrode 312 is located below the substrate 301.

[0028] The vertical power transistor 300 is designed as a GaN trench MOSFET.

[0029] Fig. Figure 4 shows a third embodiment of the vertical power transistor 400 according to the invention. The structure of the vertical power transistor 400 corresponds to that of the vertical power transistor 300 shown in Figure 4. Fig. 3, wherein an additional region 420 is arranged laterally next to the electrically conductive intermediate layer 405 and the n-doped GaN layer 413. This additional region 420 can comprise an insulating material. This prevents source-drain leakage currents. Alternatively, the additional region 420 can be metallic, so that a Schottky contact is formed with the conductive intermediate layer 405 and the n-doped GaN layer 413. This also prevents leakage currents, and the path can contribute to current flow in diode operation.

[0030] The invention, the combination of a GaN transistor head and a SiC substructure, is applicable to a variety of vertical power transistors based on GaN. The GaN transistor heads can be designed in various ways.

[0031] Fig.Figure 5 shows a process 500 for fabricating a vertical power transistor. The process 500 starts with a step 510 in which a drift zone is created by epitaxy, the drift zone comprising a first semiconductor material. The drift zone is lightly doped and comprises SiC. In a subsequent step 520, p-doped and n-doped regions are created by ion implantation. The p-doped and n-doped regions extend from a surface of the drift zone into the drift zone and are arranged laterally, alternating with each other. These p-doped and n-doped regions form a current aperture. In a subsequent step 530, the p-doped and n-doped regions of the current aperture are activated by a high-temperature process. In a subsequent step 540, an electrically conductive intermediate layer is epitaxially created on the drift zone.In a subsequent step 550, a semiconductor heterostructure is fabricated on the electrically conductive intermediate layer. This semiconductor heterostructure comprises a second layer with a second semiconductor material and a third layer with a third semiconductor material. The third layer is arranged on top of the second layer. The first, second, and third semiconductor materials are different, and the first semiconductor material has a smaller band gap than the second semiconductor material. For example, the second semiconductor material is GaN and the third semiconductor material is AlGaN. The vertical power transistor is then fabricated according to the prior art by epitaxial growth, metallization, and appropriate structuring.

[0032] The invention is used, for example, in the manufacture of vertical GaN power transistors with a high reverse voltage, in particular vertical HEMTs and MOSFETs, which are used in the electric drive systems of electric or hybrid vehicles, for example in DC / DC converters and inverters, as well as in vehicle chargers. The power transistors can also be used in inverters for household appliances such as washing machines.

Claims

[1] Vertical power semiconductor transistor (200) with a drift zone (202) comprising a first semiconductor material, wherein p-doped regions (203) and n-doped regions (204) extend into the drift zone (202) from a surface of the drift zone (202), the p-doped regions (203) and the n-doped regions (204) being arranged laterally immediately alternating with each other, and a semiconductor heterostructure arranged above the drift zone (202), the semiconductor heterostructure comprising a second layer (206) comprising a second semiconductor material and a third layer (207) comprising a third semiconductor material, the third layer (207) being arranged on top of the second layer (206), and the first semiconductor material, the second semiconductor material, and the third semiconductor material being different, the first semiconductor material having a smaller band gap than the second semiconductor material. characterized by, that an electrically conductive intermediate layer (205) is arranged between the drift zone (202) and the semiconductor heterostructure. [2] Vertical power transistor (200) according to claim 1, characterized by , that the electrically conductive intermediate layer (205) has a dopant concentration greater than 1e19 cm^-3. [3] Vertical power transistor (200) according to one of claims 1 or 2, characterized by , that the electrically conductive intermediate layer (205) comprises AlGaN, in particular in an Al0.25Ga0.75N composition. [4] Vertical power transistor (200) according to any one of the preceding claims, characterized by, that the electrically conductive intermediate layer (205) has a fourth layer and a fifth layer, wherein the fifth layer is arranged on the fourth layer, the fourth layer comprises AlGaN and the fifth layer has a gradual transition from an AlGaN composition to a GaN composition, wherein the GaN composition is arranged in the direction of the second layer (206). [5] Vertical power transistor (200) according to any one of the preceding claims, characterized by , that the second semiconductor material is GaN and the third semiconductor material is AlGaN. [6] Vertical power transistor (200) according to any one of the preceding claims, characterized by , that the first semiconductor material includes SiC. [7] Method (500) for manufacturing a vertical power transistor comprising the steps: • Generating (510) a drift zone by epitaxy, wherein the drift zone comprises a first semiconductor material, • Generating (520) p-doped regions and n-doped regions by ion implantation, wherein the p-doped regions and n-doped regions extend from a surface of the drift zone into the drift zone, are arranged laterally immediately alternating with each other and form a stromal aperture, • Activation (530) of the p-doped regions and the n-doped regions of the current aperture by means of a high-temperature process, • Generating (540) an electrically conductive intermediate layer on the drift zone, and • Creating (550) a semiconductor heterostructure on the electrically conductive intermediate layer, wherein the semiconductor heterostructure comprises a second layer with a second semiconductor material and a third layer with a third semiconductor material, wherein the third layer is arranged on the second layer, the first semiconductor material, the second semiconductor material and the third semiconductor material are different and the first semiconductor material has a smaller band gap than the second semiconductor material.

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