Methods and procedures for improving performance in long-term businesses

Abstract

This section describes techniques for partial SIMD returns for long-latency operations. For example, a processor includes a processing unit for handling a SIMT (Single Instruction Multiple Threat) instruction, where the SIMT instruction offloads the work to a shared functional unit. In response to the SIMT instruction, the processing unit should: split the SIMT instruction into a multitude of submessages; send the submessages independently to the shared functional unit for processing; track result dependencies for subsequent instructions with a granularity per submessage; and resume execution for lanes or threads corresponding to submessages for which results have been received.

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