Integrated circuit device and manufacturing process
DE102025100202A1Pending Publication Date: 2025-12-24TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Patent Information
- Application Number
- DE102025100202
- Authority / Receiving Office
- DE · DE
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-10-10
- Filing Date
- 2025-01-07
- Publication Date
- 2025-12-24
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Abstract
An integrated circuit device (IC device) comprises a device stack, an upper contact structure, a lower contact structure, a conductor, a via interconnect, and a rear-side power supply line. The device stack contains a lower semiconductor device and an upper semiconductor device stacked along a thickness direction above the lower semiconductor device. The upper contact structure is positioned above a source / drain of the upper semiconductor device and is in electrical contact with the source / drain. The lower contact structure is positioned below a source / drain of the lower semiconductor device and is in electrical contact with the source / drain. The conductor is at the same level as, and spaced apart from, the lower contact structure. The via interconnect extends between the upper contact structure and the conductor, electrically connecting them.The rear operating voltage line is located under the conductor and is electrically connected to it.
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Citation Information
Patent Citations
63/663.413