POWER SHELL CONDUCTOR PACKAGE COMPLIMENTING STACKED FET DIES, AND METHOD FOR MAKING THE SAME

Abstract

A power semiconductor package comprising: a power electronic substrate comprising a first side and an opposing second side; a first FET chip comprising a first side and an opposing second side, wherein the first FET chip is arranged on the power electronic substrate such that the first side of the first FET chip faces away from the power electronic substrate and such that the second side of the first FET chip faces the first side of the power electronic substrate; a second FET chip comprising a first side and an opposing second side, wherein the second FET chip is arranged on the first side of the first FET chip such that the second side of the second FET chip faces the first FET chip; a first conductive layer arranged between the first and the second FET chips and electrically connecting the first and the second FET chips;an encapsulation body encapsulating the first and second FET chips; a first metal clip comprising a first section and a second section, the first section being positioned over the first side of the second FET chip and electrically connected to a first power electrode on the first side of the second FET chip, and the second section being positioned laterally next to the first and second FET chips; and a first connector electrically connecting a control electrode on the first side of the first FET chip to the first metal clip.

Images