Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor device includes transistor cells formed in a semiconductor substrate and electrically coupled in parallel to form a power transistor. The transistor cells include trenches extending in a vertical direction from a first main surface of the semiconductor substrate into the semiconductor substrate. The trenches include: a gate electrode; a field electrode below the gate electrode; and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate. The at least one dielectric material is thicker between the field electrode and a bottom of the trenches than between the field electrode and each sidewall of the trenches. Each trench has a tapered width that decreases across a depth of the trench in the vertical direction. A method of manufacturing the semiconductor device is also described.

Description

BACKGROUND

[0001] DC-DC power conversion for servers, high-performance computing (HPC), and artificial intelligence (AI) requires higher efficiency and higher density. With increasing frequencies, the figure of merit (FOMoss) = Rdson*Qoss becomes a dominant power loss mechanism, where Rdson is an on-state resistance and Qoss is an output charge. Some conventional power semiconductor devices used in DC-DC power conversion systems employ a dual-polysilicon field-plate design, where the field plate is used to fully compensate the drift region. For these devices, FOMoss is reduced by Rdson reduction. These devices have been optimized for low Rdson over several generations of geometry reductions, making further FOMoss reductions difficult.Single-trench polysilicon devices with a trench bottom oxide exhibit a figure of merit (R*AA) (on-resistance times active area) that is too high for modern, space-constrained, high-power applications. Monolithic devices for high-frequency DC-DC power conversion are not capable of vertical power flow like vertical trench MOSFETs (metal-oxide-semiconductor field-effect transistors).

[0002] Thus, there is a need for an improved semiconductor device design optimized for DC-DC power conversion systems. SUMMARY

[0003] According to one embodiment of a semiconductor device, the semiconductor device comprises: a semiconductor substrate; and a plurality of transistor cells formed in the semiconductor substrate and electrically coupled in parallel to form a power transistor, wherein the plurality of transistor cells comprises a plurality of trenches extending in a vertical direction from a first main surface of the semiconductor substrate into the semiconductor substrate, each trench of the plurality of trenches comprising: a gate electrode; a field electrode under the gate electrode;and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and a bottom of the trenches than between the field electrode and each sidewall of the trenches, each trench having a tapered width that decreases across a depth of the trench in the vertical direction;

[0004] According to one embodiment of a method for manufacturing a semiconductor device, the method comprises: forming a plurality of transistor cells in a semiconductor substrate; and electrically coupling the plurality of transistor cells in parallel to form a power transistor, wherein forming the plurality of transistor cells comprises: etching a plurality of trenches into a first main surface of the semiconductor substrate, extending in a vertical direction into the semiconductor substrate;and in each trench, forming a gate electrode, a field electrode below the gate electrode, and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and a bottom of the trenches than between the field electrode and each sidewall of the trenches, wherein each trench has a tapered width that decreases across a depth of the trench in the vertical direction;

[0005] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. SHORT DESCRIPTION OF THE CHARACTERS

[0006] The elements of the drawings are not necessarily to scale relative to one another. Like reference numerals indicate corresponding similar parts. The features of the various illustrated embodiments may be combined, provided they are not mutually exclusive. Embodiments are illustrated in the drawings and described in detail in the following description. Fig. 1A illustrates a partial plan view of a semiconductor device in a region of a plurality of adjacent transistor cells formed in a semiconductor substrate. Fig. Figure 1B illustrates a cross-sectional view of the semiconductor device taken along the line shown in Fig. 1A is labeled AA'. Fig. Figure 2 illustrates a cross-sectional view of the semiconductor device taken along the line shown in Fig. 1A is designated AA', according to another embodiment. Fig. 3A to Fig. 3F illustrates a partial cross-sectional view between two (2) adjacent trenches of the semiconductor device during various stages of manufacturing according to one embodiment. DETAILED DESCRIPTION

[0007] The embodiments described herein provide a semiconductor device optimized for DC-DC power conversion systems and a method for fabricating the semiconductor device. A thick dielectric region is provided beneath the field electrode (field plate) of the power transistor cells to significantly reduce FOMoss. The thick dielectric region is thicker than the field oxide laterally surrounding the field electrode, e.g., 1.5 to 10 times thicker. The field electrode can extend to a shallower depth into the semiconductor substrate compared to a conventional device that does not have the thick dielectric region.

[0008] The field oxide surrounding the field electrode can be thinner or thicker than in a conventional device to optimize the Rdson-Qoss trade-off. Epitaxial doping can be reduced compared to a conventional device to reduce Qoss. The thick dielectric region, trench depth, and field electrode depth can be optimized.

[0009] The new design can be based on a stripe dual polysilicon structure, with the field electrode located under a gate electrode in the same trench, and the thick dielectric region located under the field electrode. However, the new design can also be applied to a needle trench cell or a stripe device design that uses a gate trench separate from the field electrode trench. In this case, the gate trench may or may not include the thick dielectric region under the gate electrode.

[0010] The thick dielectric region provides several advantages in a power MOSFET device. First, the thick dielectric region partially shields the field electrode from the drain potential, resulting in a smaller change in the local field electrode voltage when the drain voltage is switched. Second, the thick dielectric region provides a dielectric RESURF (reduced surface field) to enable higher epitaxial doping and lower Rdson than a simple trench device. Third, the thick dielectric region introduces beneficial crystalline strain into the drift region, increasing the mobility of charge carriers (e.g., electrons) and reducing Rdson. Fourth, the output capacitance is reduced because the source-drain capacitance of the field electrode is reduced.

[0011] Next, embodiments of the semiconductor device and a method for manufacturing the semiconductor device will be described with reference to the figures.

[0012] Fig. 1A illustrates a partial top view of the semiconductor device in a region of a plurality of adjacent transistor cells 100 formed in a semiconductor substrate 102. Fig. Figure 1B illustrates a cross-sectional view of the semiconductor device taken along the line shown in Fig. 1A is labeled AA'.

[0013] The transistor cells 100 are electrically coupled in parallel to form a power transistor, such as a vertical power MOSFET (metal oxide semiconductor field-effect transistor), wherein the transistor cells 100 have the same or a similar structure. In general, the semiconductor device may comprise tens, hundreds, thousands, or even more transistor cells 100.

[0014] The semiconductor substrate 102, in which the transistor cells 100 are formed, comprises one or more semiconductor materials used to form a power semiconductor device, such as a Si or SiC power MOSFET. For example, the semiconductor substrate 102 may comprise Si, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and the like. The semiconductor body 100 may include one or more epitaxial layers.

[0015] The transistor cells 100 formed in the semiconductor substrate 102 include trenches 104 extending in a vertical direction (z-direction in Fig. 1A and Fig. 1B) extend from a first main surface 106 of the semiconductor substrate 102 into the semiconductor substrate 102. In Fig. 1A, the trenches 104 are striped trenches. The term “striped,” as used herein, means a structure having a longest linear dimension in one direction (y-direction in Fig. 1A and Fig. 1B), which are generally perpendicular to the depth direction (z-direction in Fig. 1A and Fig. 1B) of the semiconductor substrate 102.

[0016] Each trench 104 includes a gate electrode 108, a field electrode 110 below the gate electrode 108, and at least one dielectric material (such as a single dielectric material or a material stack) 112 separating the gate electrode 108 and the field electrode 110 from each other and from the semiconductor substrate 102. Each transistor cell 100 further includes a source region 114 of a first conductivity type and a body region 116 of a second conductivity type opposite to the first conductivity type. The source region 114 of each transistor cell 100 is separated from a (common) drift region 118 of the first conductivity type by the corresponding body region 116. In the case of a vertical power transistor, a drain region 120 is arranged on the backside of the semiconductor substrate 102.

[0017] The first conductivity is n-type and the second conductivity is p-type for an n-channel device formed by transistor cells 100, whereas the first conductivity is p-type and the second conductivity is n-type for a p-channel device formed by transistor cells 100. For either an n-channel device or a p-channel device, source region 114 and body region 116 form part of a transistor cell 100, and transistor cells 100 are electrically connected in parallel between source (S) and drain (D) terminals of the semiconductor device to form a power transistor.

[0018] The body regions 116 of the transistor cells 100 may include a body contact region 122 of the second conductivity type. The body contact region 122 has a higher doping concentration than the body regions 116 to provide an ohmic connection to a source / emitter metallization 124 through a contact structure 126, such as electrically conductive vias extending through an interlayer dielectric 128 separating the source metallization 124 from the semiconductor substrate 102. The source regions 114 of the transistor cells 100 are also electrically connected to the source metallization 124 through the contact structure 126. The source metallization 124, the contact structure 126, and the interlayer dielectric 128 are in Fig. 1A to provide an unobstructed view of the semiconductor substrate 102.

[0019] The gate electrodes 108 are electrically connected to a gate terminal (G), e.g., by a gate metallization not shown in the figures. The gate metallization may be part of a patterned power metallization that also includes the source metallization 124. Such a patterned power metallization may include a thick power metal layer comprising Cu, Al, AlCu, AlSiCu, etc., a diffusion barrier, and / or an adhesion promoter such as Ti and / or TiN and / or W between the thick power metal layer and the interlayer dielectric 128. A drain metallization 130 may be provided on the opposite side of the semiconductor substrate 102 as the source metallization 128.

[0020] The adjacent trenches 104, which are in Fig. 1A are "active" trenches because the semiconductor mesas 111 defined by the active trenches 104 contribute to the main current flow of the semiconductor device. For these adjacent active trenches 104, the trenches 104 may have the same dimensions (e.g., depth, width, length) throughout the active area of the device where the main current flow occurs, where the active area is the portion of the semiconductor substrate 102 that includes the source region 114. The gate electrodes 108 may have the same dimensions (e.g., depth, width, length) throughout the active area of the device. The field electrodes 110 may have the same dimensions (e.g., depth, width, length) throughout the active area of the device. The thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trenches 104 may be uniform throughout the active area of the device.The trench width and therefore the width of the gate electrode 108 may be at a location along the length (y-direction in . Fig. 1A and Fig. 1B) of the trenches 104, e.g., to accommodate gate contacts outside the active area. It may also include a region along the length (y-direction in Fig. 1A and Fig. 1B) of the active trenches 104 without the gate electrode 108 and where the field electrode 110 is contacted outside the active area. For example, the field electrode 110 could extend to the first main surface 106 at this location.

[0021] The at least one dielectric material (such as a single dielectric material or a stack of materials) 112 disposed in the trenches 104 and separating the gate electrode 108 and the field electrode 110 from each other and from the semiconductor substrate 102 may use the same material throughout, e.g., thermal and / or deposited oxide. In one embodiment, the at least one dielectric material 112 includes any combination of thermal and / or deposited SiO2 between the gate electrode 108 and the body regions 116. Between the field electrode 110 and the drift region 118, the at least one dielectric material 112 may include any combination of thermal and / or deposited SiO2, and an oxynitride or nitride may be included (e.g., in a stack).In other embodiments, the at least one dielectric material 112 may include a stack of thermal oxide, HDP (high density plasma) oxide, and deposited oxide from a field oxidation process between the field electrode 110 and the drift region 118, and an oxynitride or nitride may be included (e.g., in a stack). In some embodiments, the at least one dielectric material 112 may include a stack of thermal oxide and HDP oxide between the gate electrode 108 and the field electrode 110. Still other insulating material combinations are contemplated for the at least one dielectric material 112.

[0022] The at least one dielectric material 112 is thicker (T_b_ox > W_f_ox) between the field electrode 110 and the bottom 132 of the trenches 104 than between the field electrode 110 and each sidewall 134 of the trenches 104. Each trench 104 has a tapered width (CD1 > CD2) that decreases along the depth D_t of the trench 104.

[0023] In one embodiment, the at least one dielectric material (such as a single dielectric material or a stack of materials) 112 between the field electrode 110 and the bottom 132 of the trenches 104 is 1.5 to 10 times thicker, e.g., 4 to 10 times thicker, e.g., 2 to 6 times thicker, than between the field electrode 110 and each sidewall 134 of the trenches 104. For example, the thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trenches 104 may be about 200 nm, and the thickness W_f_ox of the at least one dielectric material 112 between the field electrode 110 and each sidewall 134 of the trenches 104 may be about 70 nm. An additional benefit can be achieved by further increasing T_b_ox to 300 nm, 400 nm, or beyond. For T_b_ox between 200 nm and 400 nm, FOMoss (i.e., Rdson*Qoss) is further reduced by about 10%.

[0024] Between the field electrode 110 and the bottom 132 of the trenches 104, the at least one dielectric material 112 may extend 10% to 67% of the total trench depth D_t. For example, the trench depth D_t may be approximately 870 nm, and the thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trenches 104 may be approximately 200 nm. For D_t of 1000 nm and T_b_ox of 150 nm, the at least one dielectric material 112 spans 15% of D_t between the field electrode 110 and the bottom 132 of the trenches 104. The total trench depth D_t is proportional to the nominal (breakdown) voltage of the device, and a higher percentage thickness of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trenches 104 relative to D_t results in a larger Qoss reduction.For the minimum case, D_t may be 1000 nm, T_b_ox may be 100 nm, and the at least one dielectric material stack 112 may extend through 10% of D_t between the field electrode 110 and the bottom 132 of the trenches 104. For the maximum case, D_t may be 900 nm, T_b_ox may be 600 nm, and the at least one dielectric material 112 may extend through 67% of D_t between the field electrode 110 and the bottom 132 of the trenches 104.

[0025] The field electrode 110 may have a thickness T_f in the vertical direction (z-direction in Fig. 1A and Fig. 1B) ranging from 100 nm to 1200 nm, and the at least one dielectric material 112 may have a thickness T_b_ox in the vertical direction between the field electrode 110 and the bottom 132 of the trenches 104 ranging from 100 nm to 600 nm. For a nominal (breakdown) voltage of 25 V, T_f may range from 150 nm to 400 nm. The T_f value may increase for higher voltage devices and decrease for lower voltage devices. The field plate thickness T_f is a variable that allows for adjustment of the Rdson-breakdown-Qoss trade-off (no field electrode results in the highest Rdson but the lowest Qoss for the same breakdown voltage, whereas the highest field electrode results in the lowest Rdson but the highest Qoss).

[0026] For nominal voltages up to 40 V, T_f can range from 100 nm to 1200 nm, T_b_ox can range from 100 nm to 600 nm, and the T_f / T_b_ox ratio can range from a minimum of 0.17 (100 nm / 600 nm) to a maximum of 6 (600 nm / 100 nm). For example, for a nominal voltage of 25 V, T_f can range from 100 nm to 600 nm, and for a nominal voltage of 40 V, T_f can range from 100 nm to 1200 nm. For nominal voltages up to 40 V, the thickness T_g of the gate electrode 108 in the vertical direction (z-direction in Fig. 1A and Fig. 1B) may range from 100 nm to 500 nm, and the thickness T_f_ox of the at least one dielectric material 112 between the gate electrode 108 and the field electrode 110 may range from 50 nm to 300 nm. The thickness T_f_ox of the at least one dielectric material 112 between the gate electrode 108 and the field electrode 110 may be greater or lesser than the thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trenches 104.

[0027] Depending on the processing used to form the at least one dielectric material 112, which will be described in more detail later herein, each sidewall 134 of the trenches 104 may have a step profile 136 near the bottom 138 of the field electrode 110. The step profile 136 may occur when a thermal oxide liner is used to achieve good oxide interface quality with a low number of interface states. The step profile 136 may be avoided by using a SiN liner that remains in the trenches 104. In another embodiment, the trenches 104 have a uniform width (i.e., no step profile 136) across the trench depth D_t.

[0028] The field electrodes 110 may terminate at a depth of 33% to 90% of the trench depth D_t, where the depth is measured from the first main surface 106 of the semiconductor substrate 102 and is given by D_t - T_b_ox. For example, the field electrodes 110 may terminate at a depth of approximately 620 nm, while the trenches 104 may terminate at a depth of approximately 870 nm. The depth of the field electrodes 110 helps determine the breakdown voltage of the device and also effects the R*AA-Qoss trade-off. For a nominal voltage of 25 V, the depth of the field electrodes 110 may be in a range of 620 nm + / - 150 nm. The trench depth beyond the field electrode termination point is then equivalent to the thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trenches 104.More generally, the field electrodes 110 may terminate at a depth in a range of 300 nm to 900 nm, and the trenches 104 may terminate at a depth of 350 nm to 2600 nm.

[0029] In Fig. 1B, the trenches 104 terminate vertically in the drift region 118 of the semiconductor device. In one embodiment, the drift region 118 has a doping concentration in the range of 2e16 cm -3 up to 2e17 cm -3 The doping concentration of drift region 118 depends on the device's voltage class. Even with some increase in on-resistance (Rdson), reducing Qoss more than compensates for this increase. For example, Rdson may be 10 to 30% higher, but Qoss is 50 to 60% lower. At switching frequencies of 1.5 to 2 MHz, for example, higher efficiency can be achieved across the load range.

[0030] A junction region 140 having a higher average doping concentration than the drift region 118 may be arranged vertically between the drift region 118 and the drain region 120. The drain region 120 has a higher average doping concentration than the junction region 140. The drift region 118, the junction region 140, and the drain region 120 have the same conductivity type (e.g., n-type for an n-channel device and p-type for a p-channel device).

[0031] Fig. Figure 2 illustrates a cross-sectional view of the semiconductor device taken along the line shown in Fig. 1A is designated AA', according to another embodiment. In Fig. 2, the trenches 104 extend vertically through the drift region 118 and into the more highly doped transition region 140. The trenches 104 end before they reach the drain region 120 in Fig. 2. A more highly doped junction region 140 results in less hot carrier injection during the avalanche, but increases Qoss. For some devices, a less doped junction region 140 may be advantageous. If the field electrode 110 does not extend into the junction region 140, e.g., as in Fig. 2, Qoss does not increase as much.

[0032] Fig. 3A to Fig. 3F illustrate a partial cross-sectional view between two (2) adjacent trenches 104 of the semiconductor device during various stages of manufacturing according to one embodiment.

[0033] Fig. 3A shows the semiconductor substrate 102 after the trenches 104 are etched into the first main surface 106 of the semiconductor substrate 102 to a depth D_t and a liner 200 is formed on each sidewall 134 and the bottom 132 of the trenches 104. The liner 200 may be a single layer (e.g., thermal oxide or SiN) or a layer stack (e.g., thermal oxide and SiN).

[0034] Fig. Figure 3B shows the semiconductor substrate 102 after the trenches 104 are at least partially filled with an oxide 202 formed by high-density plasma chemical vapor deposition (HDP-CVD). High-density plasma chemical vapor deposition is a form of plasma-enhanced chemical vapor deposition (PECVD) that uses an inductively coupled plasma source to provide a high plasma density.

[0035] The HDP-CVD oxide 202 grows thick on planar surfaces and the trench bottom 132, but thin on the sidewalls 134 due to a sputtered component. To avoid the formation of voids in the HDP-CVD oxide 202, an iterative process can be used, as in Fig. 3B and Fig. 3C, and according to which the trenches 104 are at least partially filled with the HDP-CVD oxide 202 in two or more iterations of an HDP-CVD process followed by a wet etch process before the next iteration.

[0036] In Fig. 3B, the sidewall HDP-CVD oxide is removed by a wet etching process. If the liner 200 comprises only a single layer of thermal oxide or an outer layer of thermal oxide, the thermal oxide is also removed by the wet etching process, as shown in Fig. 3B. If the liner 200 comprises only a single layer of SiN or an outer layer of SiN with an inner layer of thermal oxide, the liner 200 would not be affected by the wet etching.

[0037] In Fig. 3C, the HDP-CVD process and the wet etch process are repeated at least once to completely fill the trenches 104 with the HDP-CVD oxide 202. In some embodiments, the HDP-CVD oxide 202 could instead be formed with a single HDP-CVD / etch step, but the HDP-CVD process may be limited by the trench aspect ratio.

[0038] Fig. 3D shows the semiconductor substrate 102 after the HDP-CVD oxide 202 and the liner 200 have been removed from the first main surface 106 of the semiconductor substrate 102 by a planarization process. For example, the HDP-CVD oxide 202 and the liner 200 may be removed from the first main surface 106 of the semiconductor substrate 102 by CMP (chemical mechanical polishing).

[0039] Fig. 3E shows the semiconductor substrate 102 after removing the HDP-CVD oxide 202 from the upper part of the trenches 104. In one embodiment, the HDP-CVD oxide 202 is removed from the upper part of the trenches 104 by a wet etching process to avoid rounding the corners of the trenches 104. If the liner 200 comprises only a single layer of thermal oxide or an outer layer of thermal oxide, the sidewall step profile 136 described hereinbefore in connection with Fig. 1A. The step profile 136 can be minimized by making the thermal oxide layer thinner, which improves field electrode shielding.

[0040] The liner 200 could instead comprise only a single layer of SiN or an outer layer of SiN with an inner layer of thermal oxide. Such a liner composition would avoid the step profile 136 along the trench sidewalls 134. Furthermore, the liner 200 can remain in the upper and lower parts of the trenches 104, since the wet etch process would not attack SiN. The SiN liner could be removed before forming the field plate / gate electrode stack using a separate SiN liner removal process. The SiN liner could instead remain permanently on each sidewall 134 in the upper part of the trenches 104 and form part of the at least one dielectric material 112. A (thermal) pad oxide could be formed under the nitride to form a liner stack structure.

[0041] In any case, the recess etch of the HDP-CVD oxide 202 from the upper part of the trenches 104 in Fig. 3E illustrates the thickness T_b_ox of the at least one dielectric material 112 between the field electrode 110 and the bottom 132 of the trenches 104. T_b_ox may be in a range from 100 nm to 600 nm. The removal of the HDP-CVD oxide 202 from the top of the trenches 104 may include a bulk etch followed by a controlled wet etch to yield a well-controlled trench bottom oxide height or thickness T_b_ox.

[0042] Fig.3F shows the semiconductor substrate 102 after lining each exposed trench sidewall 134 with an electrically insulating material 204 in the upper part of the trenches 104. For example, the electrically insulating material 204 may include a thinner thermal oxide (e.g., ~5 nm) 206 covered by a thicker oxide (e.g., 30 nm) 208 formed by ALD (atomic layer deposition) and / or TEOS (tetraethoxysilane). For example, the electrically insulating material 204 may include about 30 nm of thermal oxide and about 50 nm of deposited oxide (e.g., TEOS). The electrically insulating material 204 may instead be formed using only ALD for better control.

[0043] The method proceeds with standard trench processing to form the gate electrode 108 and the field electrode 110 in the trenches 104. This may include a polysilicon deposition followed by a polysilicon recess to define the field electrodes 110. An oxide component of the at least one dielectric material 112 is then deposited on the field electrodes 110, and the gate electrodes 108 are formed on the field oxide.

[0044] Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the disclosure.

[0045] Example 1. A semiconductor device comprising: a semiconductor substrate; and a plurality of transistor cells formed in the semiconductor substrate and electrically coupled in parallel to form a power transistor, wherein each trench of the plurality of transistor cells comprises a plurality of trenches extending in a vertical direction from a first main surface of the semiconductor substrate into the semiconductor substrate, the plurality of trenches comprising: a gate electrode; a field electrode below the gate electrode; and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and a bottom of the trenches than between the field electrode and each sidewall of the trenches, each trench having a tapered width that decreases across a depth of the trench in the vertical direction.

[0046] Example 2. The semiconductor device of example 1, wherein the at least one dielectric material between the field electrode and the bottom of the trenches is 1.5 to 10 times thicker than between the field electrode and each sidewall of the trenches.

[0047] Example 3. The semiconductor device according to example 1 or 2, wherein the at least one dielectric material between the field electrode and the bottom of the trenches extends 10% to 67% of the trench depth.

[0048] Example 4. The semiconductor device according to any one of Examples 1 to 3, wherein the field electrode has a thickness in the vertical direction ranging from 100 nm to 600 nm, and wherein the at least one dielectric material between the field electrode and the bottom of the trenches has a thickness in the vertical direction ranging from 100 nm to 600 nm.

[0049] Example 5. The semiconductor device according to any one of Examples 1 to 4, wherein each sidewall of the trenches has a step profile near a bottom of the field electrode.

[0050] Example 6. The semiconductor device according to any one of examples 1 to 4, wherein the trench has a uniform width across the trench depth.

[0051] Example 7. The semiconductor device according to any one of Examples 1 to 6, wherein the trenches in the vertical direction terminate in a drift region of the semiconductor device, and wherein the drift region has a doping concentration in a range of 2e16 cm -3 up to 2e17 cm -3 has.

[0052] Example 8. The semiconductor device according to any one of Examples 1 to 7, wherein the trenches extend in the vertical direction through a drift region of the semiconductor device and into a junction region having a higher average doping concentration than the drift region, wherein the junction region is arranged vertically between the drift region and a substrate region having a higher average doping concentration than the junction region, and wherein the drift region, the junction region, and the substrate region have a same conductivity type.

[0053] Example 9. The semiconductor device according to any one of examples 1 to 8, wherein the field electrode ends at a depth of 33% to 90% of the trench depth.

[0054] Example 10. The semiconductor device according to any one of Examples 1 to 9, wherein the power transistor has a rated voltage of 40 V or less.

[0055] Example 11. The semiconductor device according to any one of Examples 1 to 10, wherein the field electrode has a thickness in the vertical direction ranging from 100 nm to 1200 nm, and wherein the gate electrode has a thickness in the vertical direction ranging from 100 nm to 500 nm.

[0056] Example 12. The semiconductor device according to any one of Examples 1 to 11, wherein the at least one dielectric material between the field electrode and the bottom of the trenches has a thickness in the vertical direction ranging from 100 nm to 600 nm, and wherein the at least one dielectric material between the gate electrode and the field electrode has a thickness in the vertical direction ranging from 50 nm to 300 nm.

[0057] Example 13. The semiconductor device of any one of Examples 1 to 12, wherein the at least one dielectric material between the field electrode and the bottom of the trenches is 4 to 10 times thicker than between the field electrode and each sidewall of the trenches.

[0058] Example 14. The semiconductor device according to any one of Examples 1 to 13, wherein the semiconductor device has a rated voltage of 25 V or less, wherein the field electrode has a thickness in the vertical direction ranging from 100 nm to 600 nm, and wherein the at least one dielectric material between the field electrode and the bottom of the trench has a thickness in the vertical direction ranging from 100 nm to 600 nm.

[0059] Example 15. The semiconductor device according to any one of Examples 1 to 13, wherein the semiconductor device has a rated voltage of 40 V or less, wherein the field electrode has a thickness in the vertical direction ranging from 100 nm to 1200 nm, and wherein the at least one dielectric material between the field electrode and the bottom of the trench has a thickness in the vertical direction ranging from 100 nm to 600 nm.

[0060] Example 16. A method of manufacturing a semiconductor device, the method comprising: forming a plurality of transistor cells in a semiconductor substrate; and electrically coupling the plurality of transistor cells in parallel to form a power transistor, wherein forming the plurality of transistor cells comprises: etching a plurality of trenches into a first main surface of the semiconductor substrate that extend in a vertical direction into the semiconductor substrate;and in each trench, forming a gate electrode, a field electrode below the gate electrode, and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material is thicker between the field electrode and a bottom of the trenches than between the field electrode and each sidewall of the trenches, wherein each trench has a tapered width that decreases across a depth of the trench in the vertical direction;

[0061] Example 17. The method of Example 16, wherein forming the at least one dielectric material comprises: forming a liner on each sidewall and the bottom of the trenches; after forming the liner, at least partially filling the trenches with an oxide formed by high density plasma chemical vapor deposition (HDP-CVD); and removing the HDP-CVD oxide from an upper portion of the trenches.

[0062] Example 18. The method of claim 16, wherein forming the dielectric material or material stack comprises: forming a liner on each sidewall and the bottom of the trenches; after forming the liner, completely filling the trenches with an oxide formed by high density plasma chemical vapor deposition (HDP-CVD); and removing the HDP-CVD oxide from an upper portion of the trenches.

[0063] Example 19. The method of Example 18, wherein the liner is a thermal oxide, and wherein the thermal oxide and the HDP-CVD oxide are removed from the top of the trenches by a wet etch process.

[0064] Example 20. The method of Example 19, further comprising: after removing the thermal oxide and the HDP-CVD oxide from the upper portion of the trenches, lining each sidewall with an electrically insulating material in the upper portion of the trenches.

[0065] Example 21. The method of Example 18, wherein the liner is silicon nitride.

[0066] Example 22. The method of Example 21, further comprising: after removing the HDP-CVD oxide from the top of the trenches, removing the silicon nitride from the top of the trenches.

[0067] Example 23. The method of Example 21, wherein the silicon nitride liner remains permanently on each sidewall in the upper portion of the trenches.

[0068] Example 24. The method of Example 18, wherein the liner comprises a thermal oxide covered by silicon nitride.

[0069] Example 25. The method of example 18, wherein completely filling the trenches with the HDP-CVD oxide comprises two or more iterations of an HDP-CVD process followed by a wet etch process before the next iteration.

[0070] Terms such as "first," "second," and the like are used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the specification.

[0071] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of specified elements or features but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and singular unless the context clearly indicates otherwise.

[0072] The expression "and / or" should be interpreted to cover all possible conjunctive and disjunctive combinations, unless explicitly stated otherwise. For example, the expression "A and / or B" should be interpreted to mean only A, only B, or both A and B. The expression "at least one of" should be interpreted in the same way as "and / or" unless explicitly stated otherwise. For example, the expression "at least one of A and B" should be interpreted to mean only A, only B, or both A and B.

[0073] It is understood that the features of the various embodiments described herein may be combined with one another unless expressly stated otherwise.

[0074] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] A semiconductor device comprising: a semiconductor substrate; and a plurality of transistor cells formed in the semiconductor substrate and electrically coupled in parallel to form a power transistor, wherein the plurality of transistor cells comprises a plurality of trenches extending in a vertical direction from a first main surface of the semiconductor substrate into the semiconductor substrate, wherein each trench of the plurality of trenches comprises: a gate electrode; a field electrode below the gate electrode; and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material between the field electrode and a bottom of the trenches is thicker than between the field electrode and each sidewall of the trenches, wherein each trench has a tapered width that decreases in the vertical direction over a depth of the trench. [2] The semiconductor device of claim 1, wherein the at least one dielectric material between the field electrode and the bottom of the trenches is 1.5 to 10 times thicker than between the field electrode and each sidewall of the trenches. [3] The semiconductor device of claim 2, wherein the at least one dielectric material between the field electrode and the bottom of the trenches is 4 to 10 times thicker than between the field electrode and each sidewall of the trenches. [4] The semiconductor device of claim 1, wherein the at least one dielectric material extends between the field electrode and the bottom of the trenches from 10% to 67% of the trench depth. [5] The semiconductor device according to claim 1, wherein the field electrode has a thickness in the vertical direction ranging from 100 nm to 600 nm, and wherein the at least one dielectric material between the field electrode and the bottom of the trenches has a thickness in the vertical direction ranging from 100 nm to 600 nm. [6] The semiconductor device according to claim 1, wherein each sidewall of the trenches has a step profile near a bottom of the field electrode. [7] The semiconductor device according to claim 1, wherein the trenches terminate in the vertical direction in a drift region of the semiconductor device, and wherein the drift region has a doping concentration in a range of 2e16 cm -3 up to 2e17 cm 3 has. [8] The semiconductor device according to claim 1, wherein the trenches extend in the vertical direction through a drift region of the semiconductor device and into a junction region having a higher average doping concentration than the drift region, the junction region being arranged vertically between the drift region and a substrate region having a higher average doping concentration than the junction region, and the drift region, the junction region and the substrate region having a same conductivity type. [9] The semiconductor device according to claim 1, wherein the field electrode terminates at a depth of 33% to 90% of the trench depth. [10] The semiconductor device according to claim 1, wherein the power transistor has a rated voltage of 40 V or less. [11] The semiconductor device according to claim 1, wherein the field electrode has a thickness in the vertical direction ranging from 100 nm to 1200 nm, and wherein the gate electrode has a thickness in the vertical direction ranging from 100 nm to 500 nm. [12] The semiconductor device according to claim 1, wherein the at least one dielectric material between the field electrode and the bottom of the trenches has a thickness in the vertical direction ranging from 100 nm to 600 nm, and wherein the at least one dielectric material between the gate electrode and the field electrode has a thickness in the vertical direction ranging from 50 nm to 300 nm. [13] The semiconductor device according to claim 1, wherein the semiconductor device has a rated voltage of 25 V or less, wherein the field electrode has a thickness in the vertical direction ranging from 100 nm to 600 nm, and wherein the at least one dielectric material between the field electrode and the bottom of the trench has a thickness in the vertical direction ranging from 100 nm to 600 nm. [14] The semiconductor device according to claim 1, wherein the semiconductor device has a rated voltage of 40 V or less, wherein the field electrode has a thickness in the vertical direction ranging from 100 nm to 1200 nm, and wherein the at least one dielectric material between the field electrode and the bottom of the trench has a thickness in the vertical direction ranging from 100 nm to 600 nm. [15] A method of manufacturing a semiconductor device, the method comprising: Forming a plurality of transistor cells in a semiconductor substrate; and electrically coupling the plurality of transistor cells in parallel to form a power transistor, wherein forming the plurality of transistor cells comprises: Etching a plurality of trenches into a first main surface of the semiconductor substrate, extending in a vertical direction into the semiconductor substrate; and in each trench, forming a gate electrode, a field electrode under the gate electrode and at least one dielectric material separating the gate electrode and the field electrode from each other and from the semiconductor substrate, wherein the at least one dielectric material between the field electrode and a bottom of the trenches is thicker than between the field electrode and each sidewall of the trenches, wherein each trench has a tapered width that decreases in the vertical direction over a depth of the trench. [16] The method of claim 15, wherein forming the at least one dielectric material comprises: Forming a lining on each side wall and the bottom of the trenches; after forming the liner, at least partially filling the trenches with an oxide formed by high-density plasma chemical vapor deposition (HDP-CVD); and Removing the HDP-CVD oxide from an upper part of the trenches. [17] The method of claim 15, wherein forming the at least one dielectric material comprises: Forming a lining on each side wall and the bottom of the trenches; after forming the lining, completely filling the trenches with an oxide formed by high-density plasma chemical vapor deposition (HDP-CVD); and Removing the HDP-CVD oxide from an upper part of the trenches. [18] The method of claim 17, wherein the liner is a thermal oxide, and wherein the thermal oxide and the HDP-CVD oxide are removed from the upper part of the trenches by a wet etching process. [19] The method of claim 18, further comprising: after removing the thermal oxide and the HDP-CVD oxide from the upper part of the trenches, lining each sidewall with an electrically insulating material in the upper part of the trenches. [20] The method of claim 17, wherein the lining is silicon nitride. [21] The method of claim 20, further comprising: after removing the HDP-CVD oxide from the upper part of the trenches, removing the silicon nitride from the upper part of the trenches. [22] The method of claim 20, wherein the silicon nitride liner remains permanently on each sidewall in the upper part of the trenches. [23] The method of claim 17, wherein the liner comprises a thermal oxide covered by silicon nitride. [24] The method of claim 17, wherein completely filling the trenches with the HDP-CVD oxide comprises two or more iterations of an HDP-CVD process followed by a wet etching process before the next iteration.

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