Methods for forming pseudo-CFET structures

Abstract

A method comprising: forming a first multilayer stack (22) in a first fixture region (100C); forming a first gate stack (42) over the first multilayer stack (22); forming a second multilayer stack (22) in a second fixture region (100PSC); forming a second gate stack (42) over the second multilayer stack (22); etching the first multilayer stack (22) to form a first source / drain recess (46); etching the second multilayer stack (22) to form a second source / drain recess (46); forming a hard mask (49) in the second source / drain recess (46); forming a lower source / drain region (62L-C) in the first source / drain recess (46); after the lower source / drain region (62L-C) is formed, removing the hard mask (49) from the second source / drain recess (46). Source / Drain recess (46);correspondingly forming both a first upper source / drain region (62U-C) in the first source / drain recess (46) and a second upper source / drain region (62U-PSC) in the second source / drain recess (46); and after the hard mask (49) is removed from the second source / drain recess (46), a contact etch stop layer (66) and an interlayer dielectric (68) are formed over the contact etch stop layer (66), wherein parts of the contact etch stop layer (66) and the interlayer dielectric (68) are located in the second source / drain recess (46) and at the same level as the lower source / drain region (62L-C), wherein the first upper source / drain region (62U-C) and the second upper source / drain region (62U-PSC) are formed after the contact etch stop layer (66) and the interlayer dielectric (68) have been formed.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the following provisional US patent application: Application No. 63 / 699.715, filed on September 26, 2024, entitled “HM scheme to achieve cut P EPI for mCFET SRAM;”, which is incorporated by reference into the present application. BACKGROUND

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate, and by structuring the various material layers using lithography to form circuit components and elements.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows for the integration of more components in a given area. However, reducing the minimum element dimensions introduces additional problems that need to be addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates a perspective view of exemplary complementary field-effect transistors (CFETs) according to some embodiments. The Fig. Figures 2 to 13A and 13B are views of intermediate stages in the formation of CFETs according to some embodiments. The Fig. 14A and Fig. Figure 14B illustrates a CFET structure which, according to some embodiments, can be used to form part of a static RAM cell (SRAM cell). Fig. Figure 15 illustrates a circuit diagram of an SRAM cell according to some embodiments. Fig. Figure 16 illustrates a flowchart for forming CFETs and pseudo-CFETs according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and also embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or symbols in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself dictate a relationship between the various described embodiments and / or configurations.

[0006] Furthermore, spatially relative terms such as "underlying," "below," "under," "lower," "above," "above," "upper," and the like may be used herein to facilitate discussion and describe the relationship of one element or feature to another element or feature, or to other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass, in addition to the orientation shown in the figures, various orientations of the device during its use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0007] A complementary field-effect transistor (CFET), a pseudo-CFET, and the method for constructing the latter are provided. The pseudo-CFET has a similar structure to the CFET but lacks one of the FETs, such as a lower FET. According to some embodiments, the CFET and the pseudo-CFET form part of a static RAM cell (SRAM cell) (such as the one in Fig. 15 SRAM cell 100 shown).

[0008] It is understood that, while in the exemplary embodiments PFETs are the lower FETs within the CFETs, in alternative embodiments the PFETs can also be formed as the upper FETs. Furthermore, in the illustrated exemplary embodiments, the pseudo-CFET lacks the lower FET and includes the upper FETs. The concept of the process can also be applied to form a pseudo-CFET in which the upper FET is absent and the lower FET is present. While in some embodiments the CFET and the pseudo-CFET are described as forming SRAM cells, they can be used in any other circuit where there are more PFETs than NFETs or more NFETs than PFETs. Throughout this description, the terms "FET" and "transistor" are used interchangeably.

[0009] Fig. Figure 15 illustrates a circuit diagram of the SRAM cell 100 according to some embodiments. The SRAM cell 100 has pull-up transistors PU-1 and PU-2, which are PFETs. The SRAM cell 100 also has pull-down transistors PD-1 and PD-2, as well as pass-gate transistors PG-1 and PG-2, which are NFETs. The gates of the pass-gate transistors PG-1 and PG-2 are connected to and controlled by the word line WL, which determines whether the SRAM cell 100 is selected or not.

[0010] A bistable circuit, consisting of pull-up transistors PU-1 and PU-2 and pull-down transistors PD-1 and PD-2, can store one bit, with the complementary values ​​of the bit stored in memory nodes SN-1 and SN-2. The stored bit can be written to or read from SRAM cell 100 via complementary bit lines, including the bit line (BL) and bit line strip (BLB).

[0011] According to some embodiments, the PFETs and NFETs of the SRAM cell 100 can be implemented using CFETs, which may have the structure described in Fig. Figure 1 shows that the SRAM cell 100 can be implemented through the processes as provided in the processes described in the Fig. Figures 2 to 13A and 13B are shown. It is understood that CFETs can have PFETs and NFETs in pairs. However, the SRAM cell 100 can have a number of PFETs that differs from the number of NFETs, such as four PFETs and two NFETs, as shown in Fig. Figure 15 shows that the PFETs and NFETs are not paired. The embodiments of the present disclosure provide the methods and structures for implementing the unpaired PFETs and NFETs.

[0012] Fig. Figure 1 illustrates an example of CFETs 10 (including the FETs (transistors) 10U and 10L) according to some embodiments, which has the structure that can be used to implement the unpaired PFETs and NFETs such as the SRAM cell 100. Fig. Figure 1 is a three-dimensional view, with some features of the CFETs omitted for illustrative purposes.

[0013] The CFETs feature multiple vertically stacked FETs. For example, a CFET can have a lower nanostructure FET 10L of a first device type (e.g., type n / type p) and an upper nanostructure FET 10U of a second device type (e.g., type p / type n) oriented opposite to the first device type. The nanostructure FETs 10U and 10L feature semiconductor nanostructures 26' (including the lower semiconductor nanostructures 26'L and the upper semiconductor nanostructures 26'U), with the semiconductor nanostructures 26' acting as channel regions for the nanostructure FETs. The lower semiconductor nanostructures 26'L are for the lower nanostructure FET 10L, and the upper semiconductor nanostructures 26'U are for the upper nanostructure FET 10U.

[0014] The gate dielectrics 78 enclose the corresponding semiconductor nanostructures 26'. The gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectrics 78. The source / drain regions 62 (including the lower source / drain regions 62L and the upper source / drain regions 62U) are arranged on opposite sides of the gate dielectrics 78 and the corresponding gate electrodes 80. The source / drain region(s) can refer to a single source or drain, either individually or collectively, depending on the context. Insulating elements (not shown) can be formed to separate desired source / drain regions 62 and / or desired gate electrodes 80 from one another.

[0015] Fig. Figure 1 further illustrates reference cross-sections used in later figures. Cross-section AA' is a vertical cross-section running parallel to a longitudinal axis of the semiconductor nanostructures 26' of a CFET and in a direction of, for example, current flow between the source / drain regions 62 of the CFET. Cross-section BB' is a vertical cross-section running perpendicular to cross-section AA' and along a longitudinal axis of a gate electrode 80 of the CFET. For clarity, subsequent figures may refer to these reference cross-sections.

[0016] The Fig. Figures 2 to 13A and 13B illustrate the cross-sectional views of intermediate stages in the formation of CFETs (as schematically shown in Fig. (1 shown) according to some embodiments. The corresponding processes are referred to as monolithic CFET formation processes (mCFET formation processes). The corresponding processes are also described in the Fig. The process flow shown in section 16 is shown schematically.

[0017] In Fig. In step 2, the wafer 2, which has the substrate 20, is provided. The substrate 20 can be a semiconductor substrate such as a bulk semiconductor, a semiconductor on an insulator substrate (SOI substrate), or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The SOI substrate may have a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulator layer is provided on a substrate, such as a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 20 may be silicon, germanium, carbon-doped silicon, a III-V compound semiconductor, or the like, or combinations thereof.

[0018] A multilayer stack 22 is formed on top of the substrate 20. The corresponding process is described as process 202 in the Fig. The process flow 200 shown in Figure 16 is illustrated. The multilayer stack 22 has alternating dummy semiconductor layers 24 (including dummy semiconductor layers 24A and 24B) and semiconductor layers 26 (including lower semiconductor layers 26L and upper semiconductor layers 26U). The lower semiconductor layers 26L and upper semiconductor layers 26U serve accordingly to form a lower FET and an upper FET.

[0019] Suitable wells (not shown separately) can be formed in the lower semiconductor layers 26L and the upper semiconductor layers 26U. The semiconductor layers 26L and 26U can, for example, be doped in situ (if grown epitaxially) and / or implanted to achieve the desired conductivity types.

[0020] In the illustrated example, the multilayer stack 22 has six dummy semiconductor layers 24 and six semiconductor layers 26. It is understood that the multilayer stack 22 can have any number of dummy semiconductor layers 24 and semiconductor layers 26. Each layer of the multilayer stack 22 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE) and deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.

[0021] The dummy semiconductor layers 24A are formed from a first semiconductor material, and the dummy semiconductor layer 24B is formed from a second semiconductor material that differs from the first. The first and second semiconductor materials can be selected from the semiconductor material candidates of substrate 20. The first and second semiconductor materials exhibit high etch selectivity with each other. Therefore, the dummy semiconductor layer 24B can be removed more quickly in subsequent processes than the dummy semiconductor layers 24A.

[0022] The semiconductor layers 26 (including the lower semiconductor layers 26L and the upper semiconductor layers 26U) are formed from one or more semiconductor materials. The semiconductor material(s) can be selected from the semiconductor material candidates of the substrate 20. The lower semiconductor layers 26L and the upper semiconductor layers 26U can be formed from the same semiconductor material or from different semiconductor materials.

[0023] In some embodiments, the dummy semiconductor layers 24A are formed from or contain silicon germanium, the semiconductor layers 26 are formed from silicon, and the dummy semiconductor layer 24B can be formed from germanium or silicon germanium having a higher germanium atom percentage than in the semiconductor layer 24A.

[0024] In Fig. 3. The multilayer stacks 22 and the substrate 20 are structured to form the semiconductor strips 28. The corresponding process is described as process 204 in the Fig. The process flow 200 shown in Figure 16 is illustrated. Each of the semiconductor strips 28 has the semiconductor strip 20' (the sections of the original substrate 20) and the multilayer stack 22', which is the remaining section of the multilayer stack 22. The remaining sections 22' of the multilayer stack 22 are hereafter referred to as nanostructures, which are referenced using the appropriate reference number followed by a ' ' ' sign. Accordingly, the multilayer stack 22' has the dummy nanostructures 24'A, the dummy nanostructures 24'B, the lower semiconductor nanostructures 26'L, the middle semiconductor nanostructures 26'M, and the upper semiconductor nanostructures 26'U. Etching can be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching can be anisotropic.The dummy nanostructures 24'A and 24'B can also be referred to individually and collectively as dummy nanostructures 24'. The lower semiconductor nanostructures 26'L and the upper semiconductor nanostructures 26'U can also be referred to collectively as semiconductor nanostructures 26'.

[0025] The lower semiconductor nanostructures 26'L function as channel regions for the lower nanostructure FETs of the CFETs. The upper semiconductor nanostructures 26'U act as channel regions for the upper nanostructure FETs of the CFETs. The middle semiconductor nanostructures 26'M are the semiconductor nanostructures 26' located directly above / below (e.g., in contact with) the dummy nanostructures 24'B. The middle semiconductor nanostructures 26'M can be used for insulation and may or may not act as channel regions for the CFETs. The dummy nanostructures 24'B are subsequently replaced by insulation structures. The insulation structures and the middle semiconductor nanostructures 26'M can define the boundaries of the lower and upper nanostructure FETs.

[0026] In Fig. 4. The insulation regions 32 are formed above the substrate 20 and between the adjacent semiconductor strips 28. The corresponding process is described as process 205 in the Fig. The process flow shown in Figure 16 illustrates the process flow 200. The insulation regions 32 can have a dielectric lining and a dielectric material over the dielectric lining. The insulation regions 32 are then recessed. Some upper sections of the semiconductor strips 28 (including the multilayer stacks 22') protrude higher than the remaining insulation regions 32 to form the projecting fins 34.

[0027] The dummy dielectric layer 36 is then formed on the protruding fins 34. The corresponding process is described as process 206 in the Fig. The process flow shown in Figure 16 is illustrated in Figure 200. The dummy dielectric layer 36 can, for example, be formed from or comprise silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques.

[0028] A dummy gate layer 38 is formed above the dummy dielectric layer 36. The corresponding process is described as process 208 in the Fig. The process flow shown in Figure 16 illustrates the process flow 200. The dummy gate layer 38 can be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 can be conductive or non-conductive and can be selected from a group that includes amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), or the like. A mask layer 40, which can, for example, consist of silicon nitride, silicon oxynitride, or the like, is formed over the planarized dummy gate layer 38.

[0029] Next, the mask layer 40 can be structured by photolithography and etching processes to form a mask, which is then used to etch and structure the dummy gate layer 38 and possibly the dummy dielectric layer 36. The resulting structure is shown in the Fig. 5A and Fig. 5B shown. The remaining sections of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stacks 42. The corresponding process is shown as process 210 in the Fig. The process flow shown in 16 is illustrated in 200.

[0030] In the following description, the figures with numbers followed by the letter "A" illustrate the vertical cross-sectional views along a cross-section similar to the vertical reference cross-section AA' in Fig. 1, unless otherwise stated. Figures numbered with the letter 'B' illustrate cross-sectional views along a cross-section similar to the vertical reference cross-section BB' in Fig. 1.

[0031] The Fig. 5A and Fig. Figure 5B illustrates an initial structure for forming parts of an SRAM cell according to some embodiments. The illustrated structure has a part in the CFET region 100C and a part in the pseudo-CFET region 100PSC. In CFET region 100C, a CFET is to be formed, including an NFET and a PFET, which can form the pull-up transistor PU-1 or PU-2 and the pull-down transistor PD-1 or PD-2. Fig. 15) In the pseudo-CFET region 100C, an NFET is to be formed as part of a pseudo-CFET, which can form the pass-gate transistor PG-1 or PG-2 ( Fig. 15). The Fig. 5A and Fig. Figure 5B illustrates the vertical cross-sections AA' and BB' accordingly in Fig. 1. The ones in the Fig. 5A and Fig. The structures shown in Figure 5B in the CFET region 100C and the pseudo-CFET region 100PSC can be formed in common processes, as shown in the Fig. 2 to 4 are shown.

[0032] It goes without saying that, although in Fig. 5B The CFET region 100C and the pseudo-CFET region 100PSC are shown to be located in the same plane for better illustration; the structures in the CFET region 100C and the pseudo-CFET region 100PSC are in Fig. 5B may actually be located on different levels.

[0033] In Fig. 5A Gate spacer elements 44 are formed above the multilayer stacks 22' and on exposed sidewalls of the dummy gate stacks 42. The corresponding process is described as process 212 in the Fig. The process flow shown in Figure 16 illustrates the gate spacer elements 44. These elements can be formed by conformal forming of one or more dielectric layers and subsequent anisotropic etching of the dielectric layers. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by a deposition process such as CVD, ALD, or the like. Fig. Figure 5B illustrates the fin spacer elements 45, which are formed from the same dielectric layers as the gate spacer elements 44.

[0034] The source / drain recesses 46 are formed in the semiconductor strips 28 in both the CFET region 100C and the pseudo-CFET region 100PSC. The corresponding process is described as process 214 in the Fig. The process flow 200 shown in Figure 16 is illustrated. The source / drain recesses 46 are formed by etching semiconductor strips 28 and can extend through the multilayer stacks 22' and into the semiconductor strips 20'. The lower surfaces of the source / drain recesses 46 can be located at a level above, below, or at the same level as the upper surfaces of the insulation regions 32 ( Fig. 5B). During the etching processes, the gate spacer elements 44 and the dummy gate stacks 42 mask some sections of the semiconductor strips 28. The source / drain recesses 46 can be formed simultaneously in common processes in the CFET region 100C and the pseudo-CFET region 100PSC.

[0035] The dummy nanostructures 24'A are then recessed laterally, and one or more dielectric materials are filled into the corresponding recesses to form the internal spacer elements 54, which are dielectric spacer elements. The dielectric insulating layers 56 are also formed to replace the dummy nanostructures 24'B.

[0036] With reference to the Fig. 6A and Fig. 6B forms the protective linings 48C and 48PSC. The corresponding process is described as process 216 in the Fig. The process flow shown in Figure 16 illustrates the process flow 200. The protective linings 48C and 48PSC can be formed in common or separate processes. The protective layer layers 48C and 48PSC can be made of or comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, or the like, or combinations thereof. Furthermore, the material of the protective layer layers 48C and 48PSC differs from the materials of the exposed elements, such as the gate spacer elements 44, hard masks 40, internal spacer elements 54, and the like, so that the exposed elements are not damaged during the subsequent removal of the protective layer layers 48C and 48PSC.

[0037] According to some embodiments, the formation of the protective liners 48C and 48PSC may include the deposition of a sacrificial layer (not shown), the filling of the source / drain recesses 46, the planarization of the sacrificial layer, and the back-etching of the sacrificial layer. The upper surface of the remaining sacrificial layer is then at the same level as the lower end of the subsequently formed protective liners 48C and 48PSC. The sacrificial layer may comprise a photoresist or another polymer, which may or may not be photosensitive.

[0038] A protective cover layer is then conformally deposited, followed by an anisotropic etching process to remove the horizontal sections of the protective cover layer, leaving the protective layer layers 48C and 48PSC as illustrated. The remaining sections of the sacrificial layer are then removed. According to some embodiments, the lower ends of the protective liners 48C and 48PSC are lower than the dielectric insulating layers 56 and higher than the lower surface of the lower semiconductor nanostructures 26'L, which lie directly beneath the middle semiconductor nanostructures 26'M.

[0039] In a subsequent process, as in the Fig. 6A and Fig. Figure 6B shows that a hard mask 49 is formed in both the CFET region 100C and the pseudo-CFET region 100PSC. The corresponding process is described as process 218 in the diagram. Fig. The process flow shown in Figure 16 illustrates the formation process. The formation process can include the deposition of a conformal dielectric layer in both the CFET region 100C and the pseudo-CFET region 100PSC. As shown in Figure 16, the process flow can be illustrated in Figure 200. Fig. As shown in Figure 6A, the hard mask 49 masks the exposed sidewalls of the semiconductor nanostructures 26'L and the surfaces of the semiconductor strips 20'.

[0040] The formation process of the hard mask 49 may include a conformal deposition process, such as ALD, CVD, or the like. According to some embodiments, the hard mask 49 is formed from a material different from that of the protective liners 48C and 48PSC. The material of the hard mask 49 may (or may not) be selected from the same group of material candidates used to form the protective liners 48C and 48PSC. The material of the hard mask 49 may, for example, comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, or the like, or combinations thereof.

[0041] With reference to the Fig. 7A and Fig. In 7B, the etching mask 50 is formed and structured. The corresponding process is described as process 220 in the Fig. The process flow shown in Figure 16 illustrates the process flow 200. According to some embodiments, the etch mask 50 can have a structured photoresist and can have a single-layer, two-layer, or three-layer structure. The etch mask 50 is removed from the CFET region 100C, leaving a remaining section in the pseudo-CFET region 100PSC. The etch mask 50 can further fill the source / drain recess 46 in the pseudo-CFET region 100PSC.

[0042] According to some embodiments, the hard mask 49 and the etch mask 50 can be parts of the masks used to mask certain protected circuit regions, such as the test wedges in scribing lines (not shown), so that subsequent epitaxy processes do not result in unwanted growth of semiconductor materials in the protected circuit regions. Accordingly, the formation of the hard mask 49 and the etch mask 50 can adopt the existing process and the existing hard mask and etch mask without requiring additional processes. When the etch mask 50 is removed from the CFET region 100C (while remaining in the pseudo-CFET region 100PSC), the etch mask remains in the protected circuit regions.

[0043] In a subsequent process, the hard mask 49 is structured in an etching process, whereby the exposed sections of the hard mask 49 are removed. The resulting structure is in the Fig. 8A and Fig. 8B is shown. The corresponding process is designated as process 222 in the Fig. The process flow shown in Figure 16 is illustrated in Figure 200. The removal process can be carried out by an isotropic etching process using a wet etching solution or an etching gas that attacks the hard mask 49 but not the protective linings 48C and 48PSC, the internal spacer elements 54 and the semiconductor strips 20'.

[0044] Fig. Figure 8C illustrates a perspective view of the [unclear] in the Fig. 8A and Fig. The structure shown in Figure 8B is shown. The illustrated section reflects the section in the pseudo-CFET region 100PSC. The etch mask 50 is shown schematically. An opening in the etch mask 50 schematically illustrates the CFET region 100C.

[0045] After structuring the hard mask 49, the remaining sections of the etch mask 50 are removed, exposing the underlying hard mask 49, which is located in the pseudo-CFET region 100PSC but not in the CFET region 100C.

[0046] Next, as in the Fig. 9A and Fig. Figure 9B shows the lower source / drain region 62L-C formed in the lower section of the source / drain recess 46 in the CFET region 100C. The corresponding process is shown as process 224 in the figure. Fig. The process flow shown in Figure 16 illustrates the process flow 200. The lower source / drain region 62L-C is in contact with the lower semiconductor nanostructures 26'L and not in contact with the upper semiconductor nanostructures 26'U. The internal spacer elements 54 physically and electrically isolate the lower source / drain regions 62L-C from the dummy nanostructures 24'A, which are replaced by exchange gates in subsequent processes.

[0047] During the formation of the lower source / drain region 62L-C, which is carried out by a selective epitaxy process, the semiconductor material is not grown in the source / drain recesses 46 in the pseudo-CFET region 100PSC due to the masking of the hard mask 49.

[0048] The lower source / drain region 62L-C has a conductivity type suitable for the device type (type p or n) of the lower nanostructure FETs. In the following description, it is assumed that the lower nanostructure FETs are PFETs and the upper nanostructure FETs are NFETs. According to alternative embodiments, the lower nanostructure FETs can be NFETs and the upper nanostructure FETs can be PFETs.

[0049] If the lower source / drain region 62L-C is a p-source / drain region, the corresponding material may consist of silicon or silicon germanium doped with a p-type dopant, such as boron, indium, and / or the like. The lower source / drain region 62L-C may be in-situ doped and may or may not be implanted with the corresponding p- or n-type dopants.

[0050] In a subsequent process, the remaining sections of the hard mask 49 are removed, and the resulting structure is in the Fig. 10A and Fig. 10B is shown. The corresponding process is designated as process 226 in the Fig. The process flow shown in Figure 16 illustrates the removal process. The removal process can be carried out by an isotropic etching process using a wet etching solution or an etching gas that attacks the hard mask 49 but not the protective linings 48C and 48PSC ( Fig. 9A and Fig. 9B), the inner spacer elements 54, the lower source / drain regions 62L-C and the semiconductor strips 20'.

[0051] Next, the protective linings 48C and 48PSC ( Fig. 9A and Fig. 9B). The corresponding process is listed as process 228 in the Fig. The process flow shown in Figure 16 illustrates the removal process. Removal can be achieved by an isotropic etching process, either wet or dry. The etching chemical is selected to avoid etching the inner spacer elements 54, the lower source / drain regions 62L-C, and other exposed materials, such as the gate spacer elements 44 and the hard masks 40. The resulting structures are also shown in the Fig. 10A and Fig. 10B shown.

[0052] With reference to the Fig. 11A and Fig. In 11B, a first contact etch stop layer (CESL) 66 and a first ILD 68 are formed. The corresponding process is described as process 230 in the Fig. The process flow shown in Figure 16 illustrates the formation of the first CESL 66 and the first ILD 68 simultaneously in the CFET region 100C and the pseudo-CFET region 100PSC. The first CESL 66 can be formed from a dielectric material with high etch selectivity from the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which can be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 can be formed from a dielectric material that can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The applicable dielectric material of the first ILD 68 may be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide or the like.

[0053] The formation processes can include the deposition of a conformal CESL layer, the deposition of material for ILD 68 followed by a planarization process such that the deposited material sections have a planar top surface. Subsequently, a back-etching process is performed to recess the deposited material. In some embodiments, the first ILD 68 is etched first, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the sections of the first CESL 66 that are taller than the recessed first ILD 68. After recession, the sidewalls of the upper semiconductor nanostructures 26'U are exposed.

[0054] Due to the planarization and etching processes, the upper surfaces of the first ILD 68 and the first CESL 66 in CFET region 100C and pseudo-CFET region 100PSC may be at the same level or at slightly different levels. Regardless of whether they are at the same level or at different levels, the upper surfaces of the first ILD 68 and the first CESL 66 in CFET region 100C and pseudo-CFET region 100PSC are both higher than the lower surfaces of the inner spacer elements 54 located immediately below the dielectric insulation layers 56, and they are lower than the upper surfaces of the inner spacer elements 54 located immediately above the dielectric insulation layers 56.

[0055] The lower surface of the first CESL 66 in CFET region 10--0C is in contact with the upper surface of the lower source / drain region 62L-C. The lower surface of the first CESL 66 in pseudo-CFET region 100PSC is lower than the lower surface of the first CESL 66 in CFET region 100C. Furthermore, the first CESL 66 in pseudo-CFET region 100PSC is in contact with the upper surface of semiconductor strip 20' in pseudo-CFET region 100C and with the sidewalls of semiconductor nanostructures 26'L.

[0056] Next, with reference to the Fig. 12A and Fig. 12B the upper epitaxial source / drain regions 62U-C and 62U-PSC are formed in the upper sections of the source / drain recesses 46 and correspondingly in the CFET region 100C and the pseudo-CFET region 100PSC. The corresponding process is designated as process 232 in the Fig. The process flow shown in Figure 16 illustrates the process flow 200. The epitaxial source / drain regions 62U-C and 62U-PSC can be formed simultaneously or in separate processes. Accordingly, the upper epitaxial source / drain regions 62U-C can have the same structure and composition as the upper epitaxial source / drain regions 62U-PSC.

[0057] The upper epitaxial source / drain regions 62U-C and 62U-PSC can be doped in situ and / or implanted with an n-type or p-type dopant, depending on the intended conductivity type. For example, if the upper epitaxial source / drain regions 62U-C and 62U-PSC are n-type semiconductor regions, SiP, SiCP, or the like can be used.

[0058] Next, a second CESL 70 and a second ILD 72 are formed. The second CESL 70 and the second ILD 72 can be formed simultaneously in CFET region 100C and pseudo-CFET region 100PSC. The corresponding process is described as process 234 in the Fig. The process flow shown in 16 is illustrated in 200.

[0059] The materials and formation processes for the second CESL 70 and a second ILD 72 may be the same or similar as those used for the first CESL 66 and the first ILD 68, and are not described in detail herein. The formation process may include depositing the layers for the CESL 70 and the ILD 72, as well as performing a planarization process to remove the excess portion of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the spacer elements 44, and the dummy gate stacks 42 are coplanar (within process variations). The planarization process may remove the masks 40 or leave the hard masks 40 intact.

[0060] Next, the dummy gate stacks 42 are removed in one or more etching processes, creating recesses. Each of the recesses exposes and / or lies over sections of the multilayer stacks 22'. The remaining sections of the dummy nanostructures 24'A ( Fig. 12A) are then removed by etching, so that the voids between the semiconductor nanostructures extend 26'U.

[0061] The exchange gate stacks 90 (each comprising gate stacks 90L and 90U) are then formed in the corresponding recesses and can be formed simultaneously in CFET region 100C and pseudo-CFET region 100PSC. The corresponding process is described as process 236 in the Fig. The process flow shown in Figure 16 illustrates the process flow 200. The gate stacks 90L feature the gate dielectric 78 and the gate electrodes 80L. The gate stacks 90U feature the gate spacer elements 78 and the gate electrodes 80U. Each gate dielectric 78 can have an interface layer (such as a silicon oxide layer) and a high-k dielectric layer over the interface layer. The gate dielectrics 78 are formed on the exposed semiconductor nanostructures 26' and have sections at the spacer elements 44. The gate dielectrics 78 envelop all (e.g., four) sides of the semiconductor nanostructures 26'.

[0062] The dielectric hard masks 92 are formed over the gate stacks 90U. The gate electrodes 80L and 80U have conductive materials that can provide suitable work functions for the resulting lower FETs (lower transistors) 10L and upper FETs (upper transistors) 10U. The gate electrodes 80L and 80U can be common gates formed in the same forming process, or they can be electrically decoupled from each other.

[0063] Fig. Figure 14A illustrates a structure which, according to some embodiments, has two CFET regions and one pseudo-CFET region. The CFET region 100C and the pseudo-CFET region 100PSC, as shown in the Fig. 13A and Fig. 13B shown, can be Fig. 14A will be obtained. According to some embodiments, the implementation in Fig. The structure shown in Figure 14A comprises a pull-up transistor PU, a pull-down transistor PD, and a pass-gate transistor PG, where these transistors are also referred to in Fig. 15 are shown. Accordingly, an SRAM cell can have 100, as shown in Fig. 15 is shown, using the in Fig. The structure shown in 14A will be implemented.

[0064] Fig.Figure 14A further illustrates the formation of upper source / drain contact connectors 81T, which, according to some embodiments, connect to the upper source / drain regions 62U-C and 62U-PSC, and of lower source / drain contact connectors 81B, which, according to some embodiments, connect to the lower source / drain regions 62L-C. It is understood that the illustrated connection scheme is merely an example and that other connection schemes may be used. The source / drain silicide layers 83 are also formed. The electrical connection to the lower source / drain regions 62L-C can be made by vertical interconnects, wherein the source / drain contact connector 81T (in the illustrated device region 100C) electrically connects an upper source / drain region 62U-C and a lower upper source / drain region 62L-C.

[0065] It is understood that by applying the embodiments of the present disclosure, it is not necessary to form a lower dummy source / drain region and then perform a structuring process to remove the lower dummy source / drain region for the pseudo-CFET. If the formation and structuring are performed to remove a lower dummy source / drain region, the corresponding photolithography process may suffer from a superimposition displacement problem, which, due to the small distance between adjacent CFETs, results in a small process window. The uniformity of the device wafer may be affected. Furthermore, removing the lower dummy source / drain region may damage gate spacer elements and internal spacer elements.

[0066] The embodiments of the present disclosure have several advantageous features. By adopting the processes of the present disclosure, it is not necessary to form and then etch dummy source / drain regions, and the problem caused by etching the dummy source / drain regions is avoided. The processes according to the embodiments of the present disclosure can use existing masks, and therefore no additional masks and lithography processes are required.

[0067] According to some embodiments of the present disclosure, a method comprises forming a first multilayer stack in a first device region; forming a first gate stack over the first multilayer stack; forming a second multilayer stack in a second device region; forming a second gate stack over the second multilayer stack; etching the first multilayer stack to form a first source / drain recess; etching the second multilayer stack to form a second source / drain recess; forming a hard mask in the second source / drain recess; forming a lower source / drain region in the first source / drain recess; and, after the lower source / drain region has been formed, removing the hard mask from the second source / drain recess.and accordingly the formation of both a first upper source / drain region in the first source / drain recess and a second upper source / drain region in the second source / drain recess.

[0068] In one embodiment, the lower source / drain region is of a first conductivity type, and the first upper source / drain region and the second upper source / drain region are of a second conductivity type opposite to the first conductivity type. In one embodiment, the first conductivity type is type p and the second conductivity type is type n. In another embodiment, the first upper source / drain region, the lower source / drain region, and the second upper source / drain region are configured as parts of a pull-up transistor, a pull-down transistor, and a pass-gate transistor of a static random-access memory (RAM) cell, respectively.

[0069] In one embodiment, the method further comprises, after removal of the hard mask from the second source / drain recess, the formation of a contact etch stop layer and an interlayer dielectric over the contact etch stop layer, wherein portions of the contact etch stop layer and the interlayer dielectric are located in the second source / drain recess and at the same level as the lower source / drain region. In one embodiment, the contact etch stop layer is in contact with semiconductor nanostructures of the second multilayer stack. In one embodiment, the portions of the etch stop layer extend to the underside of the second source / drain recess.

[0070] In one embodiment, forming the hard mask comprises depositing an overlay hard mask layer in the first and second device regions; and removing the overlay hard mask layer from the first device region. In another embodiment, the method further comprises, prior to depositing the overlay hard mask layer, forming a first protective lining and a second protective lining in the upper portions of the first and second source / drain recesses. In another embodiment, the method further comprises replacing the first gate stack with a first replacement gate stack; and replacing the second gate stack with a second replacement gate stack. In another embodiment, the first replacement gate stack and the second replacement gate stack are formed by sharing common processes.

[0071] According to some embodiments of the present disclosure, a method comprises: forming a first source / drain recess in a first device region, wherein the first source / drain recess is located between first two adjacent multilayer stacks, and wherein a first upper surface of a first semiconductor region lies below and is exposed to the first source / drain recess; forming a second source / drain recess in a second device region, wherein the second source / drain recess is located between second two adjacent multilayer stacks, and wherein a second upper surface of a second semiconductor region lies below and is exposed to the second source / drain recess; forming a hard mask in the second source / drain recess and on surfaces of the second two adjacent multilayer stacks; forming a lower source / drain region in the first source / drain recess;the removal of the hard mask; and the formation of a first contact etch stop layer having a first section in the first source / drain recess, wherein the first section contacts a third upper surface of the lower source / drain region; and a second section in the second source / drain recess, wherein the second section contacts the second upper surface of the second semiconductor region.

[0072] In one embodiment, the method further comprises forming a first interlayer dielectric over the first contact etch stop layer, wherein the first interlayer dielectric has corresponding sections in the first source / drain recess and the second source / drain recess. In another embodiment, the method further comprises forming a first upper source / drain region in the first source / drain recess and a second upper source / drain region in the second source / drain recess. In one embodiment, the first source / drain recess and the second source / drain recess are formed in a single process.

[0073] In one embodiment, the method further comprises forming a second contact etch stop layer, which has parts in the first source / drain recess and the second source / drain recess. In one embodiment, the first upper source / drain region, the lower source / drain region, and the second upper source / drain region are formed as parts of a static RAM cell.

[0074] According to some embodiments of the present disclosure, a structure comprises a first device, which first has several semiconductor nanostructures, comprising a first semiconductor nanostructure and a second semiconductor nanostructure overlapping the first semiconductor nanostructure; a lower source / drain region laterally adjacent to the first semiconductor nanostructure; and a first upper source / drain region overlapping the lower source / drain region, the first upper source / drain region contacting the second semiconductor nanostructure; a first dielectric region between the lower source / drain region and the first upper source / drain region; a second device, which second has several semiconductor nanostructures, comprising a third semiconductor nanostructure and a fourth semiconductor nanostructure overlapping the third semiconductor nanostructure;and a second upper source / drain region adjacent laterally to the fourth semiconductor nanostructure; and a second dielectric region below the second upper source / drain region, the second dielectric region adjacent laterally to the third semiconductor nanostructure.

[0075] In one embodiment, the second dielectric region comprises a contact etch stop layer and an intermediate dielectric above the contact etch stop layer. In another embodiment, the structure further comprises a semiconductor strip, wherein the second dielectric region contacts an upper surface of the semiconductor strip.

[0076] The foregoing describes features of several embodiments so that the person skilled in the art may better understand the aspects of the present disclosure. A person skilled in the art should recognize that he can readily use the present disclosure as a basis for the design or modification of other methods and structures to achieve the same purposes and / or to obtain the same advantages as the embodiments presented herein. The person skilled in the art should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure, and that he can make various changes, substitutions, and modifications without deviating from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 699.715

[0001]

Claims

[1] Procedure, encompassing: Forming a first multilayer stack in a first fixture region; Forming an initial gate stack above the first multi-layer stack; Forming a second multilayer stack in a second device region; Forming a second gate stack above the second multi-layer stack; Etching the first multilayer stack to form an initial source / drain recess; Etching the second multilayer stack to form a second source / drain recess; Forming a hard mask in the second source / drain recess; Forming a lower source / drain region in the first source / drain recess; After the lower source / drain region is formed, remove the hard mask from the second source / drain recess; and correspondingly forming both a first upper source / drain region in the first source / drain recess and a second upper source / drain region in the second source / drain recess. [2] Method according to claim 1, wherein the lower source / drain region is of a first conductivity type, and wherein the first upper source / drain region and the second upper source / drain region are of a second conductivity type opposite to the first conductivity type. [3] Method according to claim 2, wherein the first conductivity type is type p and the second conductivity type is type n. [4] Method according to any one of claims 1 to 3, wherein the first upper source / drain region, the lower source / drain region and the second upper source / drain region are formed accordingly as parts of a pull-up transistor, a pull-down transistor and a pass-gate transistor of a static RAM cell. [5] Method according to any one of claims 1 to 4, further comprising, after the hard mask is removed from the second source / drain recess, forming a contact etch stop layer and an interlayer dielectric over the contact etch stop layer, wherein parts of the contact etch stop layer and the interlayer dielectric are located in the second source / drain recess and at the same level as the lower source / drain region. [6] Method according to claim 5, wherein the contact etch stop layer is in contact with semiconductor nanostructures of the second multilayer stack. [7] Method according to claim 5 or 6, wherein the parts of the contact etch stop layer extend to an underside of the second source / drain recess. [8] Method according to any one of claims 1 to 7, wherein forming the hard mask comprises: Deposition of a hard mask overlay layer in the first fixture region and the second fixture region; and Removal of the hard mask overlay layer from the first fixture region. [9] Method according to claim 8, further comprising, before the covering hard mask layer is deposited, forming a first protective lining and a second protective lining in upper parts of the first source / drain recess and the second source / drain recess. [10] Method according to any one of claims 1 to 9, further comprising: Replacing the first gate stack with a first exchange gate stack; and Replacing the second gate stack with a second exchange gate stack. [11] Method according to claim 10, wherein the first exchange gate stack and the second exchange gate stack are formed by sharing common processes. [12] Procedures, including: Forming a first source / drain recess in a first device region, wherein the first source / drain recess is located between first two adjacent multilayer stacks, and wherein a first upper surface of a first semiconductor region lies below and is exposed to the first source / drain recess; Forming a second source / drain recess in a second device region, wherein the second source / drain recess is located between two adjacent multilayer stacks, and wherein a second upper surface of a second semiconductor region lies below and is exposed to the second source / drain recess; Forming a hard mask in the second source / drain recess and on surfaces of the second two adjacent multilayer stacks; Forming a lower source / drain region in the first source / drain recess; Removal of the hard mask; and Formation of a first contact etch stop layer, which exhibits: a first section in the first source / drain recess, wherein the first section contacts a third upper surface of the lower source / drain region; and a second section in the second source / drain recess, wherein the second section contacts the second upper surface of the second semiconductor region. [13] Method according to claim 12, further comprising forming a first interlayer dielectric over the first contact etch stop layer, wherein the first interlayer dielectric has sections in the first source / drain recess and the second source / drain recess. [14] The method of claim 12 or 13 further comprising forming: a first upper source / drain region in the first source / drain recess; and a second upper source / drain region in the second source / drain recess. [15] Method according to any one of claims 12 to 14, wherein the first source / drain recess and the second source / drain recess are formed in a common process. [16] Method according to any one of claims 12 to 15, further comprising: Forming a second contact etch stop layer that includes parts in the first source / drain recess and the second source / drain recess. [17] Method according to any one of claims 12 to 16, wherein the first upper source / drain region, the lower source / drain region and the second upper source / drain region are formed as parts of a static RAM cell. [18] Structure, exhibiting: a first device comprising: first multiple semiconductor nanostructures, which have a first semiconductor nanostructure and a second semiconductor nanostructure that overlaps the first semiconductor nanostructure; a lower source / drain region adjacent laterally to the first semiconductor nanostructure; and a first upper source / drain region that overlaps the lower source / drain region, wherein the first upper source / drain region contacts the second semiconductor nanostructure; a first dielectric region between the lower source / drain region and the first upper source / drain region; a second device comprising: second, several semiconductor nanostructures comprising a third semiconductor nanostructure and a fourth semiconductor nanostructure overlapping the third semiconductor nanostructure; and a second upper source / drain region adjacent laterally to the fourth semiconductor nanostructure; and a second dielectric region below the second upper source / drain region, wherein the second dielectric region is laterally adjacent to the third semiconductor nanostructure. [19] Structure according to claim 18, wherein the second dielectric region comprises a contact etch stop layer and an intermediate dielectric above the contact etch stop layer. [20] Structure according to claim 18 or 19, further comprising a semiconductor strip, wherein the second dielectric region contacts an upper surface of the semiconductor strip.