IMAGE SENSORS WITH DOTED ISOLATION STRUCTURES

Abstract

An image sensor device can include a semiconductor substrate, first and second image sensor pixels in the substrate, and a gradient-doped deep trench isolation (DTI) structure between the first and second image sensor pixels. The gradient-doped DTI structure can include at least two doped regions extending from a back surface of the semiconductor substrate to form a back-side DTI structure. Light scattering structures can be formed on the back surface and can be doped. The at least two doped regions can be etched and doped sequentially during the fabrication of the image sensor device. Alternatively or additionally, a trench can be etched from a front surface of a semiconductor substrate, doped, and further etched into the semiconductor substrate to form a front-side DTI structure.The semiconductor substrate can be etched on the front surface, and the additional etching of the trench can eliminate or reduce pitting corrosion of the semiconductor substrate.

Description

BACKGROUND

[0001] Image sensors are commonly used in electronic devices, such as mobile phones, cameras, computers, and vehicles, to capture images. In a typical configuration, an image sensor comprises an array of image pixels arranged in pixel rows and pixel columns. A circuit arrangement can be coupled to each pixel column to read image signals from the image pixels.

[0002] The embodiments described herein arise in this context. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a diagram of an illustrative electronic device comprising an image sensor according to some embodiments. Fig. Figure 2 is a diagram of an illustrative pixel array and the associated row and column control circuit arrangement for reading image signals from an image sensor according to some embodiments. Fig. 3A and Fig. Figure 3B shows side views of illustrative sections of a pixel array that includes gradient-doped deep-trench isolation structures between pixels according to some embodiments. Fig. Figures 4A to 4E are illustrative schematic diagrams of process steps that can be used to form gradient-doped deep-trench insulation structures in a semiconductor substrate according to some embodiments. Fig. Figures 5A to 5C are illustrative schematic diagrams of process steps that can be used to form gradient-doped deep-trench insulation structures and doped light-scattering structures in a semiconductor substrate according to some embodiments. Fig. Figures 6A to 6E are illustrative schematic diagrams of process steps that can be used to form doped front-side deep-trench insulation structures in a semiconductor substrate according to some embodiments. DETAILED DESCRIPTION

[0003] Embodiments of the present technology relate to image sensors. Those skilled in the art will recognize that the exemplary embodiments presented here can also be implemented in practice without some or all of these specific details. In other cases, already known processes have not been described in detail in order to avoid making the present embodiments unnecessarily opaque.

[0004] Electronic devices, such as digital cameras, computers, mobile phones, and other electronic devices, can include image sensors that capture incident light to create an image. These image sensors can contain arrays of image pixels. The pixels in the image sensors can include photosensitive elements, such as photodiodes, that convert the incident light into image signals. Image sensors can have any number of pixels, such as hundreds, thousands, or more. A typical image sensor, for example, might have hundreds, thousands, or millions of pixels. One million pixels can be referred to as a megapixel. Image sensors can include a control circuit arrangement, such as a circuit arrangement for operating the pixels and a readout circuit arrangement for reading out image signals corresponding to the electrical charge generated by the photosensitive elements.

[0005] Fig. Figure 1 is a diagram of an illustrative imaging and response system that includes an imaging system where an image sensor is used to capture images. A system 8 of Fig. 1 could be, for example, an electronic device such as a camera, mobile phone, video camera or other electronic device that captures digital image data, could be a vehicle safety system (e.g. an active braking system or other vehicle safety system) or could be a surveillance system.

[0006] As in Fig. As shown in Figure 1, the system 8 can include an imaging system such as an imaging system 10 and host subsystems such as a host subsystem 20. The imaging system 10 can include a camera module 12. The camera module 12 can include one or more image sensors 14, as in a circuit integrated in an image sensor array, and one or more lenses. During image acquisition, each lens can focus light onto an associated image sensor 14. The image sensor 14 can include photosensitive elements (e.g., image sensor pixels) that convert the light into analog data. Image sensors can have any number of pixels, such as hundreds, thousands, millions, or more. A typical image sensor, for example, can have millions of pixels (e.g., megapixels).

[0007] Each image sensor in the camera module 12 can be identical, or different image sensor types can be present in a given integrated image sensor array circuit. In some examples, the image sensor 14 can further include a bias circuit arrangement (e.g., source-follower load circuits), a sample-and-hold circuit arrangement, a dual-sampling correlation (CDS) circuit arrangement, an amplifier circuit arrangement, an analog-to-digital converter circuit arrangement, a data output circuit arrangement, a memory (e.g., a buffer memory circuit arrangement), and / or an address circuit arrangement.

[0008] Still image and video image data from the image sensor 14 can be provided to the image processing and data formatting circuitry 16 via a path 28. The image processing and data formatting circuitry 16 can be used to perform image processing functions, such as data formatting, white balance and exposure, implementation of video image stabilization, or face detection. The image processing and data formatting circuitry 16 can additionally or alternatively be used to compress camera raw image files, if desired, such as compressing the camera raw image files to the Joint Photographic Experts Group (JPEG) format.

[0009] In an example arrangement, such as a system-on-a-chip (SoC) arrangement, the image sensor 14 and the image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate, such as a common silicon die of an integrated image sensor circuit. If desired, the image sensor 14 and the image processing and data formatting circuitry 16 can be formed on separate semiconductor substrates. For example, the image sensor 14 and the image processing and data formatting circuitry 16 can be formed on separate substrates that are stacked.

[0010] The imaging system 10 can transmit acquired image data to the host subsystem 20 via a path 18. The host subsystem 20 can include input / output devices 22 and a storage and processing circuit arrangement 24. The host subsystem 20 can include processing software for detecting objects in images, detecting object movement between frames, determining distances to objects in images, or filtering or otherwise processing images provided by the imaging system 10. For example, the image processing and data formatting circuit arrangement 16 of the imaging system 10 can communicate the acquired image data to the storage and processing circuit arrangement 24 of the host subsystem 20.

[0011] If desired, System 8 can provide a user with numerous high-level functions. For example, a user on a computer or mobile phone can be enabled to run user applications. For these functions, the input / output device 22 of the host subsystem 20 can include keypads, input / output ports, buttons or keys, and displays, as well as the storage and processing circuitry 24. The storage and processing circuitry 24 of the host subsystem 20 can include volatile and / or non-volatile memory (e.g., random access memory, flash memory, hard disks, and / or solid-state drives). The storage and processing circuitry 24 can additionally or alternatively include microprocessors, microcontrollers, digital signal processors, and / or application-specific integrated circuits.

[0012] An example of an arrangement of the image sensor 14 of Fig. 1 is in Fig. 2 shown. As in Fig. As shown in Figure 2, the image sensor 14 can include a control and processing circuit arrangement 44. The control and processing circuit arrangement 44 (hereafter sometimes referred to as the control and processing logic) can be part of the image processing and data formatting circuit arrangement 16 in Figure 2. Fig. 1 or may be separate from the image processing and data formatting circuit arrangement 16. The image sensor 14 may include a pixel array such as an array 32 of pixels 34 (hereafter occasionally referred to as image sensor pixels, imaging pixels, or image pixels). Via the control path 27, the control and processing circuit arrangement 44 may be connected to a row control circuit arrangement 40, and via the data path 26, it may be connected to a column control and read circuit arrangement 42.

[0013] The line control circuit arrangement 40 can receive line addresses from the control and processing circuit arrangement 44 and can supply corresponding line control signals to image pixels 34 via one or more control paths 36. The line control signals can include pixel reset control signals, charge transfer control signals, bloom control signals, line selection control signals, double conversion gain control signals, and / or any other desired pixel control signals.

[0014] The column control and readout circuit arrangement 42 can be coupled to one or more of the columns of the pixel array 32 via one or more conductive lines, such as column lines 38. A given column line 38 can be coupled to a column of image pixels 34 in the image pixel array 32 and can be used to read image signals from the image pixels 34 and to supply bias signals (e.g., bias currents or bias voltages) to the image pixels 34. For example, each column of pixels can be coupled to a corresponding column line 38. During image pixel readout operations, a row of pixels in the image pixel array 32 can be selected using the row control circuit arrangement 40, and image data associated with the image pixels 34 of that pixel row can be read out on column lines 38 by the column control and readout circuit arrangement 42.The column control and readout circuit arrangement 42 can include a column circuit arrangement, such as column amplifiers for amplifying signals read from the array 32, a sample-and-hold circuit arrangement for sampling and storing signals read from the array 32, analog-to-digital converter circuits for converting read analog signals into corresponding digital signals, and / or column memory for storing the read signals and any other desired data. The column control and readout circuit arrangement 42 can output digital pixel readout values ​​to the control and processing circuit arrangement 44 via data path 26.

[0015] Array 32 can have any number of rows and columns. Generally, the size of Array 32 and the number of rows and columns in Array 32 depend on the specific implementation of the image sensor 14. While rows and columns are generally described herein as horizontal and vertical, they can refer to any grid-like structure. The features described herein as rows can be arranged vertically, and the features described herein as columns can be arranged horizontally.

[0016] The pixel array 32 can be provided with a color filter array with multiple color filter elements, enabling a single image sensor to capture light of different colors. Image sensor pixels, such as the image pixels in array 32, can, for example, be provided with a color filter array, enabling a single image sensor to sample red, green, and blue (RGB) light using corresponding red, green, and blue image sensor pixels. The red, green, and blue image sensor pixels can be arranged in a Bayer mosaic pattern. The Bayer mosaic pattern consists of a repeating unit cell of image pixels in pairs, with two green image pixels diagonally opposite each other and adjacent to a red pixel diagonally opposite a blue pixel. In another example, broadband image pixels, which include broadband color filter elements (e.g.,Clear color filter elements) can be used instead of green pixels in a Bayer pattern. These examples are for illustrative purposes only, and in general, color filter elements of any desired color (e.g., cyan, yellow, red, green, or blue) and in any desired pattern can be formed over any desired number of image pixels.

[0017] The pixels 34 of array 32 can be separated by deep-trench isolation structures (DTI structures). These DTI structures can be front-facing DTI structures, formed on the front surface of a pixel substrate, or back-facing DTI structures, formed on the back surface of the pixel substrate. The DTI structures can be made of dielectric material, such as silicon dioxide or another suitable dielectric, and / or can enclose a light-absorbing material, such as tungsten.

[0018] The DTI structures can reduce electrical and / or optical crosstalk between adjacent pixels 34 of the array 32. However, since the DTI structures are etched into active silicon (or another pixel substrate material), damage to the silicon during etching can lead to dark current. To prevent or reduce damage to the silicon, the DTI structures can be gradient-doped. Illustrative examples of front-facing DTI structures formed with gradient doping are shown in the Fig. 3A and Fig. 3B shown.

[0019] As in Fig. As shown in Figure 3A, the image sensor 14 can include a substrate such as a p-type (p-doped) semiconductor substrate 102, photosensitive elements such as photodiodes 103 formed in / on a first (front) surface of the semiconductor substrate 102, such as a surface 115, and an interlayer dielectric 116, which can enclose an interlayer stack formed on the front surface 115. Pixel isolation structures, such as deep-trench isolation (DTI) structures 104, can be formed on a second (back) surface 113, which faces the first (front) surface 115 of the substrate 102. DTI structures 104 formed on the back surface 113 are therefore sometimes referred to as back-side DTI structures (BDTI structures) 104. The BDTI structures 104 can help to provide improved electrical insulation between adjacent photodiodes / pixels.The BDTI structures 104 can be formed completely through the substrate 102, as in the example of . Fig. 3A shown, or may only be formed partially through the substrate 102 and extend partially from the rear surface 113 of the substrate 102 towards the front surface 115.

[0020] The BDTI structures 104 include dielectric material 111, which may be silicon dioxide or another suitable dielectric material. The dielectric material 111 may also cover the back surface 113 to form a dielectric back surface layer on the semiconductor substrate 102. An optional additional insert, such as a layer 106, may be formed at the interface between the semiconductor substrate 102 and the dielectric material 111. The layer 106 may be formed from a high-k dielectric material such as aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), tantalum oxide (Ta₂O₅), and / or other dielectric materials to prevent the generation of dark current on the back surface of the semiconductor substrate 102. The layer 106 is therefore sometimes referred to as a high-k dark current reduction insert.

[0021] An array of color filter structures can be formed on the dielectric material 111. In the example of Fig. 3A A first color filter element 110-1 is formed over a first photodiode 103-1, and a second color filter element 110-2 is formed over a second photodiode 103-2. The color filter elements 110-1 and 110-2 can be part of a color filter array (CFA) comprising red, green, blue, cyan, magenta, yellow, black, clear (broadband) color filter elements, a combination of these color filter elements, and / or other color filter elements. The use of a CFA is optional and can be omitted in monochrome image sensors. A monochrome image sensor 14 can have clear (broadband) filter elements 110. A planarization layer, such as a planarization layer 112, can be formed on the color filter array.

[0022] A material lattice 119 can be formed between the dielectric material 111 and the CFA. The material lattice 119 can enclose tungsten or another suitable light-absorbing material. Therefore, the material lattice 119 can prevent scattered light from passing through the BDTI structures 104.

[0023] An array of microlens structures 114 can be formed above the color filter array. Each microlens 114 can be configured to direct incident light towards a corresponding photodiode 103. Each optical stack that includes at least one microlens structure 114, one color filter element 110, and one photodiode 103 can be called an image sensor pixel or image pixel 34. The example of Fig. Figure 3A shows a first image sensor pixel 34-1 and an adjacent second image sensor pixel 34-2. Visible light passing through a pixel 34 can be absorbed by the photodiode 103. Therefore, each image sensor pixel 34 can be configured to capture visible light, allowing the overall image sensor 14 to output a full-resolution color image. Such an image sensor configuration, where light from the back surface 113 enters the semiconductor substrate 102, is sometimes referred to as a back-illuminated image capture device (BSI image capture device).

[0024] If desired, each pixel 34 can optionally include light-scattering structures, such as light-scattering structures 108 formed on the back surface 113 of the semiconductor substrate 102. The light-scattering structures 108 can, for example, be etched into the back surface 113. The light-scattering structures 108 can have oblique or angled edges or vertical (non-oblique) edges relative to the plane of the surface 113, configured to enable near-infrared (NIR) detection by the pixels 34. The light-scattering structures 108 are therefore sometimes referred to as NIR light-scattering structures. In such a configuration, each image sensor pixel 34 can further be configured to detect NIR light, so that the overall image sensor 14 can output a full-resolution near-infrared image. In the illustrative example of Fig. 3A are the light scattering structures 108 pyramidal light scattering structures. In general, however, the light scattering structures 108 can have any suitable shape or shapes.

[0025] An interlayer stack can be formed in the interlayer dielectric 116 on the semiconductor substrate 102. The interlayer stack can include alternating conduction layers and via layers formed within a dielectric material such as silicon dioxide, which forms the interlayer dielectric 116. The interlayer stack can include at least two, at least three, four or more, five to ten, more than ten, or any other number of conductive layers. The interlayer stack can be made of copper, indium tin oxide (ITO), aluminum, tungsten, titanium, gold, silver, nickel, a metal alloy, a combination of metals, and / or other types of conductive material.The metal conductor structures and the metal via structures can form an electrical network to connect various components within the pixel 34 and to couple the image signals received from the pixel 34 with a corresponding image signal processing circuit arrangement or other off-chip components.

[0026] An application-specific integrated circuit arrangement 118 and / or other circuit arrangements can be coupled to the interlayer dielectric 116. The application-specific integrated circuit arrangement 118 and / or other circuit arrangements can receive signals generated by the pixels 34, process the signals, and / or transmit the signals to other circuit arrangements in an image acquisition system.

[0027] To reduce damage to substrate 102 during the formation of the BDTI structures 104, the BDTI structures 104 can be gradient-doped BDTI structures. Specifically, the BDTI structures 104 can include a first doped region 105A, a second doped region 105B, and a third doped region 105C. Each doped region 105 can be formed sequentially. For example, the first doped region 105A can be etched into the substrate 102 from the back surface 113 over a first distance (e.g., distance D1). The distance D1 can be at least 1 micrometer, at least 2 micrometers, between 500 nanometers and 1 micrometer, at least 250 nanometers, or any other suitable distance. Once the first doped area 105A has been etched, the first doped area 105A can be doped, such as with boron doping (B doping) by ion implantation, plasma immersion, epitaxial growth or with boron trichloride (BCl3) as examples.In general, the first doped regions 105A can be doped with any suitable dopant. In this way, the first doped region 105A of the BDTI structures 104 can be formed.

[0028] This process can be continued for each of the second doped area 105B and the third doped area 105C. Although the BDTI structures 104 of Fig. Figure 3A, which shows three doped regions 105, is merely illustrative. In general, the BDTI structures 104 can have any suitable number of doped regions 105, such as at least two doped regions, at least three doped regions, or at least five doped regions.

[0029] In the example of Fig. 3A The BDTI structures 104 extend over the entire height D2 of the substrate 102 from the back surface 113 to the front surface 115. The height D2 can be at least 2 micrometers, at least 4 micrometers, at least 5 micrometers, at least 6 micrometers, less than 10 micrometers, or any other suitable height. This is merely for illustrative purposes. In general, the BDTI structures 104 can extend over any suitable distance through the substrate 102.

[0030] Although Fig. Figure 3A shows that the pixels 34 enclose pyramidal light scattering structures 108; this is merely illustrative. In some embodiments, the pixels 34 may enclose trench light scattering structures. For example, in the illustrative example of Fig. 3B Trench light scattering structures 120 are formed in the substrate 102.

[0031] In some embodiments, the trench light scattering structures 120 can be located in front of the final doped region of the BDTI structures 104 (e.g., third doped regions 105-3 of Fig. 3A) are formed, and the trench light scattering structures 120 can be doped simultaneously with the doping of the final doped region of the BDTI structures 104 with an epitaxial layer. However, this is merely illustrative. The trench light scattering structures 120 can be undoped or, if desired, can be doped after the doping of the BDTI structures 104.

[0032] An illustrative method for forming gradient-doped BDTI structures, such as the BDTI structures 104 of the Fig. 3A and Fig. 3B is in the Fig. 4A to 4E shown.

[0033] As in Fig. As shown in Figure 4A, in step 122, trenches 107 can be etched into the substrate 102. The trenches 107 can be formed using plasma dry etching (e.g., SF6, CF4, C4F8) or any other suitable etching agent. In some embodiments, a hard mask (not shown for clarity) can be used on the substrate 102 when etching the trenches 107.

[0034] After the trenches 107 have been etched into the substrate 102, they can be doped to form the doped regions 105A. Specifically, the trenches 107 can be doped, for example, with boron doping (B-doping) by ion implantation, plasma immersion, epitaxial growth, or with boron trichloride (BCl3) to form the doped regions 105A. In general, however, the trenches 107 can be doped with any suitable dopant. The trenches 107 can be doped at a low temperature, such as less than 500 °C, less than 450 °C, less than 400 °C, or at any other suitable temperature.

[0035] In this way, the doped areas 105A can be formed, while damage to the substrate 102 is reduced and / or repaired.

[0036] The doped regions 105A can extend through the substrate 102 over a distance D1, which can have a height D2. The distance D1 can be at least 1 micrometer, at least 2 micrometers, between 500 nanometers and 1 micrometer, at least 250 nanometers, or any other suitable distance. The height D2 can be at least 2 micrometers, at least 4 micrometers, at least 5 micrometers, at least 6 micrometers, less than 10 micrometers, or any other suitable height. This is merely for illustrative purposes. In general, the doped regions 105A can extend through the substrate 102 over any suitable distance.

[0037] The doped regions 105A can have a width W1 in step 122. The width W1 can be less than 100 nm, between 75 nm and 150 nm, at least 90 nm, or any other suitable width.

[0038] One or more layers 128 comprising the interlayer dielectric 116 and / or the ASIC 118 ( Fig. 3A and Fig. 3B) can be included, may be attached to the front surface of substrate 102.

[0039] In step 124 of Fig. 4B The trenches 109 can be etched from the bottom of the doped regions 105A further into the substrate 102. The trenches 109 can be formed using plasma dry etching or any other suitable etching process. In some embodiments, a hard mask (not shown for clarity) can be used on the substrate 102 when etching the trenches 109.

[0040] After the trenches 109 have been etched into the substrate 102, they can be doped to form the doped regions 105B. Specifically, the trenches 109 can be doped, for example, with boron doping (B-doping) by ion implantation, plasma immersion, epitaxial growth, or with boron trichloride (BCl3) to form the doped regions 105B. In general, however, the trenches 109 can be doped with any suitable dopant. The trenches 109 can be doped at a low temperature, such as less than 500 °C, less than 450 °C, less than 400 °C, or at any other suitable temperature.

[0041] In this way, the doped areas 105B can be formed, while damage to the substrate 102 is reduced and / or repaired.

[0042] The doped regions 105B can extend an additional distance D3 from the base of the first doped regions 105A into the substrate 102. The distance D3 can be at least 1 micrometer, at least 2 micrometers, between 500 nanometers and 1 micrometer, at least 250 nanometers, or any other suitable distance. This is merely for illustrative purposes. In general, the doped regions 105B can extend through the substrate 102 over any suitable distance.

[0043] The doped regions 105A can have a width W2 in step 124. In particular, the width W2 in step 124 can be greater than the width W1 because the doped regions 105A were doped a second time when the doped regions 105B were formed. The width W2 can be greater than 100 nm, between 90 nm and 175 nm, at least 125 nm, or any other suitable width. Consequently, the width of the doped regions 105A, which were doped twice in step 124, can be greater than the width of the doped regions 105B, which were doped once in step 124.

[0044] In step 126 of Fig. 4C Trenches 117 can be etched from the bottom of the doped regions 105B further into the substrate 102. The trenches 117 can be formed using plasma dry etching or any other suitable etching process. In some embodiments, a hard mask (not shown for clarity) can be used on the substrate 102 when etching the trenches 117.

[0045] After the trenches 117 have been etched into the substrate 102, they can be doped to form the doped regions 105C. Specifically, the trenches 117 can be doped, for example, with boron doping (B-doping) by ion implantation, plasma immersion, epitaxial growth, or with boron trichloride (BCl3) to form the doped regions 105C. In general, however, the trenches 117 can be doped with any suitable dopant. The trenches 117 can be doped at a low temperature, such as less than 500 °C, less than 450 °C, less than 400 °C, or at any other suitable temperature.

[0046] In this way, the doped areas 105C can be formed, while damage to the substrate 102 is reduced and / or repaired.

[0047] The doped regions 105C can extend an additional distance D4 from the base of the second doped regions 105B into the substrate 102. The distance D4 can be at least 1 micrometer, at least 2 micrometers, between 500 nanometers and 1 micrometer, at least 250 nanometers, or any other suitable distance. This is merely for illustrative purposes. In general, the doped regions 105C can extend through the substrate 102 over any suitable distance.

[0048] The doped regions 105A can have a width W3 in step 126. In particular, the width W3 can be wider than the width W1 in step 122 and the width W2 in step 124, because the doped regions 105A were doped a third time. The width W3 can be greater than 150 nm, between 125 nm and 200 nm, at least 175 nm, or any other suitable width. Therefore, the width of the doped regions 105A, which were doped three times, can be greater than the width of the doped regions 105B, which were doped twice, and the width of the doped regions 105C, which were doped once.

[0049] Together, the doped regions 105A, 105B, and 105C can form the BDTI structures 104. Since the doped region 105A was doped three times, the doped region 105B was doped twice, and the doped region 105C was doped once, the BDTI structures 104 can be gradient-doped BDTI structures. In the example of Fig. 4. The BDTI structures 104 extend completely through the substrate 102. However, this is merely for illustrative purposes. In some embodiments, the BDTI structures 104 may extend partially through the substrate 102.

[0050] In the examples of Fig. 4. The BDTI structures 104 include three doped regions 105. However, this is merely illustrative. In general, the BDTI structures 104 can include any suitable number of doped regions 105, such as, for example, at least two doped regions, at least three doped regions 105, or at least five doped regions 105.

[0051] One or more layers 128, which include the interlayer dielectric 116 and / or the ASIC 118 ( Fig. 3A and Fig. 3B) can be included and applied to the front surface of the substrate 102 before the formation of the BDTI structures 104. However, this is only for illustrative purposes. If desired, the layers 128 can be applied after the formation of the BDTI structures 104 (e.g., before step 122 of Fig. 4A) are attached to substrate 102.

[0052] In step 130 of Fig. In 4D, the scattering structures 108 can be etched into the back surface of the substrate 102. For example, the scattering structures 108 can be wet-etched into the substrate 102.

[0053] In the example of Fig. In 4D, the scattering structures can be 108 pyramidal (pyramidal) scattering structures. However, this is merely illustrative. In general, the scattering structures can have any suitable shape or shapes, such as trench shapes.

[0054] In step 132 of Fig. 4E The BDTI structures 104 and / or the scattering structures 108 can be filled with layer 106. In other words, layer 106 can be deposited on / in the BDTI structures 104 and / or the scattering structures 108. Layer 106 can be formed from a high-k dielectric material such as aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), tantalum oxide (Ta₂O₅), and / or other dielectric materials to prevent the generation of dark current on the back surface of the semiconductor substrate 102. Layer 106 is therefore sometimes referred to as a high-k dark current reduction layer. The high-k material of layer 106 can passivate the surface of the substrate 102 after etching.

[0055] In step 132, or in a separate step, dielectric material 111 can be deposited on layer 106. In other words, the dielectric material 111 can fill the BDTI structures 104 and / or overlap / cover the scattering structures 108. The dielectric material 111 can be, for example, silicon dioxide or another suitable dielectric.

[0056] After each doping step (e.g., doping trenches 107 to form the first doped regions 105A, doping trenches 109 to form the second doped regions 105B, and doping trenches 117 to form the third doped regions 105C), the doped regions can be annealed, for example, by microwave annealing, laser annealing, or another suitable annealing process, to activate the dopants. Alternatively or additionally, the doped regions 105A to C can be annealed after all doped regions 105A to C have been formed.

[0057] In some embodiments, the scattering structures, such as scattering structures 108, can be doped with the same material used to dope BDTI structures 104. An illustrative example of forming doped scattering structures is shown in the Fig. Shown 5A to 5C.

[0058] As in Fig. As shown in Figure 5A, the trenches 107 can be etched into the substrate 102 in step 134. The trenches 107 can be formed using plasma dry etching or any other suitable etching process. In some embodiments, a hard mask (not shown for clarity) can be used on the substrate 102 when etching the trenches 107.

[0059] After the trenches 107 have been etched into the substrate 102, they can be doped to form the doped regions 105A. Specifically, the trenches 107 can be doped with boron (B-doping) by ion implantation, plasma immersion, epitaxial growth, or with boron trichloride (BCl3) to form the doped regions 105A. In general, however, the trenches 107 can be doped with any suitable dopant. The trenches 107 can be doped at a low temperature, such as less than 500 °C, less than 450 °C, less than 400 °C, or at any other suitable temperature. In this way, the doped regions 105A can be formed while reducing and / or repairing damage to the substrate 102.

[0060] In step 136 of Fig. In 5B, the trenches 109 can be etched further into the substrate 102 from the bottom of the doped regions 105A. The trenches 109 can be formed using plasma dry etching or any other suitable etching process. In some embodiments, a hard mask (not shown for clarity) can be used on the substrate 102 when etching the trenches 109.

[0061] After the trenches 109 have been etched into the substrate 102, they can be doped to form the doped regions 105B. Specifically, the trenches 109 can be doped, for example, with boron doping (B-doping) by ion implantation, plasma immersion, epitaxial growth, or with boron trichloride (BCl3) to form the doped regions 105B. In general, however, the trenches 109 can be doped with any suitable dopant. The trenches 109 can be doped at a low temperature, such as less than 500 °C, less than 450 °C, less than 400 °C, or at any other suitable temperature. In this way, the doped regions 105B can be formed while reducing and / or repairing damage to the substrate 102.

[0062] In step 138 of Fig. In 5C, the trenches 117 can be etched further into the substrate 102 from the bottom of the doped regions 105B. The trenches 117 can be formed using plasma dry etching or any other suitable etching process. In some embodiments, a hard mask (not shown for clarity) can be used on the substrate 102 when etching the trenches 117.

[0063] After the trenches 117 have been etched into the substrate 102, they can be doped to form the doped regions 105C. Specifically, the trenches 117 can be doped, for example, with boron doping (B-doping) by ion implantation, plasma immersion, epitaxial growth, or with boron trichloride (BCl3) to form the doped regions 105C. In general, however, the trenches 117 can be doped with any suitable dopant. The trenches 117 can be doped at a low temperature, such as less than 500 °C, less than 450 °C, less than 400 °C, or at any other suitable temperature. In this way, the doped regions 105C can be formed while reducing and / or repairing damage to the substrate 102.

[0064] After each doping step (e.g., doping trenches 107 to form the first doped regions 105A, doping trenches 109 to form the second doped regions 105B, and doping trenches 117 to form the third doped regions 105C), the doped regions can be annealed, for example, by microwave annealing, laser annealing, or another suitable annealing process, to activate the dopants. Alternatively or additionally, the doped regions 105A to C can be annealed after all doped regions 105A to C have been formed.

[0065] Together, the doped regions 105A, 105B, and 105C can form the BDTI structures 104. Since the doped region 105A was doped three times, the doped region 105B was doped twice, and the doped region 105C was doped once, the BDTI structures 104 can be gradient-doped BDTI structures. In the example of Fig. In Figure 5, the BDTI structures 104 extend completely through the substrate 102. However, this is merely for illustrative purposes. In some embodiments, the BDTI structures 104 may extend partially through the substrate 102.

[0066] In the examples of Fig. 5. The BDTI structures 104 include three doped regions 105. However, this is merely illustrative. In general, the BDTI structures 104 can include any suitable number of doped regions 105, such as at least two doped regions 105, at least three doped regions 105, or at least five doped regions 105.

[0067] One or more layers 128 comprising the interlayer dielectric 116 and / or the ASIC 118 ( Fig. 3A and Fig. 3B) can be included and applied to the front surface of the substrate 102 before the formation of the BDTI structures 104. However, this is only for illustrative purposes. If desired, the layers 128 can be applied after the formation of the BDTI structures 104 (e.g., before step 134 of Fig. 5A) are attached to substrate 102.

[0068] Either before or after etching the trenches 117 and doping the areas 105C, the scattering structures 120 can be etched into the back surface of the substrate 102. For example, the scattering structures 120 can be dry-etched into the substrate 102. In the example of Fig. 5C are the scatter structures 120 trench scatter structures. However, this is only for illustrative purposes. In general, the scatter structures 120 can have any suitable shape, such as pyramid shapes.

[0069] If the scattering structures 120 are etched prior to the etching of the trenches 117, the scattering structures 120 can be doped with the dopant 140 while the areas 105C are being doped (and while areas 105A and 105B are being re-doped). In particular, the scattering structures 120 can be doped, for example, with boron doping (B-doping) by ion implantation, plasma immersion, epitaxial growth, or with boron trichloride (BCl3). In general, however, the scattering structures 120 can be doped with any suitable dopant.

[0070] If the scatter structures 120 are etched after the etching and doping of the trenches 117, the scatter structures 120 can be doped with the dopant 140 in a separate step after the doping of the areas 105C. The dopant 140 can be the same dopant material used to dope the areas 105C, or it can be a different material.

[0071] Regardless of the order in which the scattering structures 120 are doped, they can be doped at a low temperature, such as less than 500 °C, less than 450 °C, less than 400 °C, or any other suitable temperature. In this way, the scattering structures 120 can be formed while reducing and / or repairing damage to the substrate 102.

[0072] Although in Fig. 5 not shown, the high-k dielectric material, such as layer 106 of Fig. 4E, and / or the dielectric material, such as the dielectric material 111 from Fig. 4E, fill and / or cover the BDTI structures 104 and / or the scattering structures 120.

[0073] In the examples of Fig. Figures 3 to 5 show the gradient-doped BDTI structures 104 in a BSI imaging device. In particular, the BDTI structures 104 are formed by partially etching a series of trenches through a semiconductor substrate and doping the trenches. In some embodiments, gradient-doped DTI structures can be formed in a front-side imaging (FSI) device. Alternatively or additionally, partial etching and doping can be used in front-side imaging devices. An illustrative example is shown in the Fig. 6A to 6E shown.

[0074] As in Fig. As shown in Figure 6A, in step 142, trenches 147 can be etched into a front surface 149 of a substrate 145. The substrate 145 can have a first region 143 and a second region 144. The substrate 145 can be a semiconductor substrate, such as a silicon substrate. The first region 143 can be a p-doped region, while the second region 144 can be a p+-doped region. However, this is only for illustrative purposes. In general, the first and second regions 143 and 144 can be formed from any suitable material(s) and have any suitable doping.

[0075] The substrate 145 can have a front surface 149 and a back surface 151. One or more layers can be formed on the front surface 149, such as the dielectric layer 146 and the masking layer 148. The dielectric layer 146 can be, for example, a silicon nitride layer (SiN layer), and the masking layer 148 can be a silicon oxide hard masking layer.

[0076] The grooves 147 can be etched into the front surface 149 using plasma dry etching or another suitable etching process. In some embodiments, a hard mask (not shown for clarity) can be used on the front surface 149 when etching the grooves 147.

[0077] The trenches 147 can have a depth H1 of at least 5 micrometers, between 3 and 8 micrometers, 6 micrometers, or any other suitable depth. The first area 143 can have a height H2 of at least 7 micrometers, between 5 and 12 micrometers, 9 micrometers, or any other suitable depth. In general, the trenches 147 can be partially etched through the first area 143 in step 142.

[0078] In step 150 of Fig. 6B The trenches 147 can be doped, for example with boron doping (B-doping) by ion implantation, plasma immersion, epitaxial growth, or with boron trichloride (BCl3). Alternatively, the trenches 147 can be doped with a dopant 152. The dopant 152 can form a p+-doped region surrounding the trenches 147. After doping the trenches 147, the doped regions can be annealed, for example with microwave annealing, laser annealing, or another suitable annealing process to activate the dopants.

[0079] In step 154 ​​of Fig. 6C The trenches 147 can be etched to obtain additional sections 162 and a total height H3. The height H3 can be at least 6 micrometers, between 4 and 9 micrometers, 7 micrometers, or any other suitable depth. In some embodiments, the height H3 can be, for example, at least one micrometer greater than the height H1, at least two micrometers greater than the height H1, or between one and five micrometers greater than the height H1. However, this is merely illustrative. In general, additional sections 162 of the trenches 147 can be etched over any suitable additional distance.

[0080] The additional sections 162 may be undocked. In other words, the bottom of each trench 147 may be undocked, while the rest of each trench 147 may be doped.

[0081] In step 164 of Fig. In 6D, trenches 147 can be filled with layers 168 and 166. Layer 168 can be a dielectric layer, such as thermal silicon dioxide. Layer 166 can be an additional dielectric layer, such as polycrystalline silicon. However, these dielectric materials are for illustrative purposes only. In general, layers 168 and 166 can be any suitable dielectric materials.

[0082] If desired, the dielectric layer 146 and / or the masking layer 148 can be etched in step 164, leaving a layer 156. The layer 156 can include a portion of the dielectric layer 146, can include the dielectric layer 146 and a portion of the masking layer 148, or can include the dielectric layer 146 and the masking layer 148. Alternatively, the dielectric layer 146 and the masking layer 148 can be completely removed, as by etching, and the layer 156 can be omitted.

[0083] In step 170 of Fig. 6E The layers 172, which can include an interleaved stack and one or more dielectric layers between metal layers of the interleaved stack, can be formed on the front surface 149 of the substrate 145. Subsequently, the substrate 145 and the layer 172 can be connected to an ASIC, such as the ASIC 118 from Fig. 3A and Fig. 3B, to be attached (not shown for clarity).

[0084] Additionally, the second region 144 of the substrate 145 on the back surface is completely etched away, as with a wet etching process, and the first region 143 can be etched to reduce the height of the first region 143 (and therefore of the substrate 145) to height H4, which may be 6 micrometers or less, 10 micrometers or less, between 4 micrometers and 7 micrometers, or any other suitable height. In the example of Fig. In 6E, the substrate 145 was etched to a given height H4 so that the front trench isolation structures (FTI structures) 153 formed from layers 166 and 168 in the doped trenches extend from the front surface 149 to the back surface 155. However, this is merely illustrative. In some embodiments, the substrate 145 can be etched to a given height H4 so that the FTI structures 153 extend partially through the substrate 145.

[0085] By forming the FTI structures 153 using partial etching and doping, followed by additional etching, the dopant 152 may not be exposed to the wet etching process of step 170, and pitting corrosion in the substrate 145 may be reduced or avoided.

[0086] After etching the substrate 145, one or more layers, such as a color filter layer, a planarization layer and / or a microlens layer, can be applied to the back surface 155 (e.g. as in the Fig. 3A and Fig. 3B shown).

[0087] The manufacturing steps of the Fig. Figures 4 to 6 are for illustrative purposes only. In some embodiments, one or more of the described processes may be modified, replaced, or omitted.

[0088] The foregoing is merely illustrative, and numerous modifications can be made to the described embodiments. The preceding embodiments can be implemented individually or in any combination.

Claims

[1] Image sensor, comprising: a semiconductor substrate; a first image sensor pixel that is formed in the semiconductor substrate; a second image sensor pixel formed in the semiconductor substrate next to the first image sensor pixel; and a gradient-doped deep-trench isolation structure between the first image sensor pixel and the second image sensor pixel. [2] Image sensor according to claim 1, wherein the semiconductor substrate comprises a front surface and a back surface and the gradient-doped deep-trench insulation structure comprises at least two doped regions and extends from the back surface. [3] Image sensor according to claim 2, wherein the gradient-doped deep-trench insulation structure extends completely from the back surface to the front surface. [4] Image sensor according to claim 2, further comprising: Light scattering structures in the back surface. [5] Image sensor according to claim 4, wherein the light scattering structures comprise pyramid-shaped light scattering structures. [6] Image sensor according to claim 4, wherein the light scattering structures comprise trench light scattering structures. [7] Image sensor according to claim 6, wherein the trench light scattering structures are doped. [8] Image sensor according to claim 4, further comprising: a high-k dielectric material that fills the gradient-doped deep-trench insulation structure and covers the light scattering structures; and a dielectric material that fills the gradient-doped deep-trench insulation structure and covers the light scattering structures. [9] Image sensor according to claim 2, wherein the at least two doped areas comprise a first doped area with a first width extending from the rear surface and a second doped area with a second width extending from the first doped area, and wherein the first width is greater than the second width. [10] Method for forming an image sensor, the method comprising: Etching a first trench into a semiconductor substrate from a back surface; Endowing the first trench; Etching a second trench into the semiconductor substrate from the first trench; Endowing the first trench and the second trench; and Filling the first and second trenches with dielectric material to form a gradient-doped deep-trench insulation structure. [11] The method of claim 10, further comprising: After doping the first and second trenches, light scattering structures are etched into the back surface of the semiconductor substrate. [12] The method of claim 11, further comprising: Doping of the light scattering structures. [13] The method of claim 11, further comprising: Covering the light scattering structures with the dielectric material. [14] The method of claim 10, further comprising: Prior to doping the first and second trenches, light scattering structures are etched into the back surface of the semiconductor substrate. [15] The method of claim 14, further comprising: Doping of the light scattering structures during the doping of the first and second trenches. [16] The method of claim 10, further comprising: after the first trench and the second trench have been filled, Microwave annealing of the first and second trenches. [17] Method for forming an image sensor, the method comprising: Etching a trench into a semiconductor substrate from a front surface over a first distance; Endowing the trench; Etching the trench over an additional distance into the semiconductor substrate; Filling the trench with dielectric material to form a deep-trench insulation structure; and Etching of the semiconductor substrate on a back surface. [18] Method according to claim 17, wherein the etching of the semiconductor substrate on the back surface comprises etching the semiconductor substrate to a given height, where the deep-trench insulation structure extends completely from the front surface to the back surface. [19] Method according to claim 17, wherein the etching of the semiconductor substrate on the back surface comprises etching the semiconductor substrate to a given height, in which the deep-trench insulation structure extends partially from the front surface into the semiconductor substrate. [20] Method according to claim 17, wherein the etching of the trench over the additional distance into the semiconductor substrate comprises etching the trench at least one micrometer further into the semiconductor substrate from the first distance.

Images