Bus topology of a serial peripheral interface with multiplexed chip-select addressing

DE102025109749A1Undetermined Publication Date: 2026-07-30GM GLOBAL TECHNOLOGY OPERATIONS LLC
View PDF 3 Cites 0 Cited by

Patent Information

Authority / Receiving Office
DE · DE
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-03-14
Publication Date
2026-07-30

Smart Images

  • Figure 00000000_0000_ABST
    Figure 00000000_0000_ABST
Patent Text Reader

Abstract

The examples described here provide a method that includes determining whether a software request is pending at a microcontroller unit (MCU), where the software request consists of reading data from a device with a serial peripheral interface (SPI) or writing data to the SPI device. The method further includes, in response to the determination that the software request is pending, driving a column select signal and a row select signal using the MCU at an SPI device address associated with the SPI device. The method further includes decoding the column select signal and the row select signal using chip-select decoder logic.The procedure further includes performing, via the MCU, an SPI transaction with the SPI device selected from the multitude of SPI devices, wherein the SPI transaction is either a reading of the data from the SPI device or a writing of the data to the SPI device.
Need to check novelty before this filing date? Find Prior Art