Superjunction-MOSFET

Abstract

A superjunction MOSFET is constructed in which a highly doped P-type semiconductor and a highly doped N-type semiconductor are first embedded in an N-type drift layer via ion coupling. An I-type junction is formed at the interface between the P-type and N-type semiconductors. The resulting homogeneous and inhomogeneous quantum state energy levels can absorb the charge carriers generated by irradiation, as well as the tunneling electrons between the P- and N-type semiconductors. The superposition of synchronous quantum states creates a large number of quantum state energy levels, which contribute to charge carrier absorption and thus effectively improve the radiation hardening properties of the device.Furthermore, the PIN diode can be embedded at different positions within the N-type drift layer to achieve different radiation hardening properties and on-resistances depending on the placement, thus optimally meeting the requirements of various applications.

Description

[0001] The present invention relates to a superjunction MOSFET, in particular a superjunction MOSFET in which a PIN diode is embedded by ion coupling to improve the radiation hardening properties.

[0002] With the further development of space technology and the advancement of nuclear energy technology, research into and prevention of damage to semiconductor devices caused by radiation or charged particles are becoming increasingly important. As in Fig. As shown in Figure 1, an ionization reaction occurs when a MOSFET is exposed to an environment with high-intensity radiation R. This reaction leads to the generation of electron-hole pairs (e - / h +), which can easily be trapped by defect structures within the semiconductor. Such defect structures are located, for example, at the interfaces between the semiconductor material and the dielectric, within the dielectric layer itself, or at the grain boundaries of polycrystalline structures. With reference to Fig. Figure 2, which shows a schematic representation of a conventional MOSFET after exposure to radiation, describes the following process: When the N-channel MOSFET is switched to the conducting state by applying a control voltage, the negatively charged electrons (e - ) in the direction of the externally connected high-potential drain terminal (D), which is located in the lower part of the structure. This movement occurs against the direction of the electric field. At the same time, the positively charged holes (h) drift +) towards the low-potential gate terminal (G) or source terminal (S), which are located in the upper region of the structure. This movement occurs along the direction of the electric field. Simultaneously, the positively charged holes (h) drift + ) towards the low-potential gate terminal (G) or source terminal (S), which are located in the upper region of the structure. This drift of the holes occurs in the direction of the electric field. Due to the comparatively lower drift velocity of the holes h + compared to the electrons e -Induced electrical charges (IEC) can accumulate at the gate. The continuous accumulation of this charge can cause the device to become permanently conductive or non-conductive, ultimately leading to device failure. This effect is known as Total Ionizing Dose (TID) and typically occurs with long-term radiation exposure. Short-term radiation exposure, on the other hand, can lead to a Single Event Effect (SEE). In this case, a single high-energy particle (e.g., a heavy ion or proton) striking the oxide layer or semiconductor of an electronic device causes local ionization and the generation of a large number of charge carriers. These charges can be transported through the device and trapped in defect structures, causing local damage.

[0003] To prevent such malfunctions of semiconductor devices in high-radiation environments—for example, to ensure nuclear safety or the functionality of space systems—it is crucial to assess the degradation mechanisms caused by radiation energy as well as the radiation resistance of the devices. In recent years, various radiation hardening (rad-hard) approaches have been developed to reduce the sensitivity of semiconductor devices to radiation damage. These include:

[0004] The integration of cavities into the semiconductor structure through special manufacturing processes to trap the holes created by radiation.

[0005] The introduction of a deeply embedded boron layer (DBL) to bind radiation-induced holes and prevent damage to defect structures.

[0006] However, both methods have significant drawbacks: For example, the fabrication of cavities requires the use of wafer bonding technologies, which can lead to low yields in mass production. On the other hand, DBL technology exhibits lower effectiveness in terms of radiation resistance compared to cavities. Furthermore, both approaches are technologically demanding, and the resulting radiation hardening still requires improvement. Against this background, the challenge lies in developing semiconductor devices that exhibit improved radiation hardening in large-scale production while simultaneously effectively reducing the negative effects of TID and SEE.

[0007] The invention is based on the objective of creating a superjunction MOSFET that has improved radiation hardening efficiency.

[0008] This problem is solved according to the invention by a superjunction MOSFET having the features specified in claim 1. Further advantageous embodiments of the invention will become apparent from the features of the dependent claims.

[0009] According to the invention, the superjunction MOSFET with a PIN structure (or NIP structure) comprises a substrate, an N-type drift layer, multiple P-type pillar regions, multiple gate regions, and multiple PIN diodes. A key aspect of the invention is that a PIN diode with a highly doped N-type semiconductor region and a highly doped P-type semiconductor region is formed in the N-type drift layer by ion coupling. This eliminates the conventional, yield-critical wafer bonding process, while the high doping concentration results in the formation of a thin I-type junction between the N-type and P-type semiconductor regions. This enhances the quantum tunneling effect, enabling more effective trapping of radiation-generated holes and thus improving the radiation-curing properties.Furthermore, depending on its position within the N-type drift layer, the PIN diode can exhibit different radiation hardening efficiencies and on-resistances (RDS(on)), thus flexibly meeting various user requirements.

[0010] The invention and its embodiments are explained in more detail below with reference to the drawing. The drawing shows: Fig. 1 a schematic representation of a conventional MOSFET in a high-energy radiation environment; Fig. 2 a schematic representation of a conventional MOSFET after exposure to radiation; Fig. 3 a schematic representation of the structure according to the invention; Fig. 4 a schematic representation of a first embodiment of the structure according to the invention; Fig. 5 a schematic representation of the first embodiment of the superjunction MOSFET according to the invention when an operating voltage is applied; Fig. 6 experimental measurement data I according to the invention; Fig. 7 experimental measurement data II according to the invention; Fig. 8 a schematic representation of a second embodiment of the structure according to the invention; Fig. 9 a schematic representation of a third embodiment of the structure according to the invention; Fig. 10 a schematic representation of an embodiment of the superjunction MOSFET according to the invention, in which silicon carbide (SiC) is used as the semiconductor material; Fig. 11 a schematic representation of a further embodiment of the superjunction MOSFET according to the invention, in which silicon carbide (SiC) is used as the semiconductor material; Fig. 12 a schematic representation of an embodiment of the superjunction MOSFET according to the invention in a P-channel configuration; and Fig. 13 a schematic representation of a further embodiment of the superjunction MOSFET according to the invention in P-channel configuration.

[0011] With reference to Fig. Figure 3 shows the present invention as a superjunction MOSFET 1 having several vertical PN junction structures. This structure makes it possible to control both the on-resistance R and the breakdown voltage while maintaining a constant on-resistance. DSonas well as reducing the gate charge Qg. This effectively solves the problems of conventional planar MOSFETs, where increasing the breakdown voltage results in a thickening of the drift zone and thus a higher on-resistance. The invention comprises a substrate 101 consisting of a highly doped N-type semiconductor material, which serves as a conductive drain terminal. An N-type drift layer 102 made of a low-doped N-type semiconductor material is formed on the substrate 101 by ion implantation. Several P-type column regions 103 are formed by ion implantation after a lithography process using a low-doped P-type semiconductor material. These column regions are arranged on the substrate 101 and run parallel to the N-type drift layer 102. This arrangement creates multiple PN junctions. On these P-type column areas 103, P-type basin areas 104 made of P-type semiconductor material are implanted.Within the P-type well regions 104 are highly doped N-type source regions 105. Between the P-type well regions 104, gate regions 106 made of N-type semiconductor material are implanted on the N-type drift layer 102. Dielectric layers 107 are formed over the gate regions 106 using processes such as chemical vapor deposition (CVD), on which gate layers 108 are formed, consisting, for example, of polysilicon, but not limited to polysilicon. In addition, I-type regions 109 are embedded in the N-type drift layer 102, which are implanted with at least one doped ion, such as argon (Ar). Since the I-type regions 109 have a multitude of charge carrier states, these states can, when the superjunction MOSFET 1 is exposed to radiation, absorb the holes h generated by the radiation. +absorb. By using the I-type regions 109, the trapping of holes h + This effectively prevents the formation of defects in the transistor. Furthermore, the accumulation of induced electrical charges at the gate is reduced, thus preventing damage to the component.

[0012] With reference to Fig. 4. The aforementioned I-type region 109 can also be replaced by a PIN diode 110 embedded in the N-type drift layer 102. This PIN diode 110 has a P-type semiconductor region 1101 and an N-type semiconductor region 1102. The P-type semiconductor region 1101 is embedded in the N-type drift layer 102 by ion coupling. The N-type semiconductor region 1102 is then formed on the top side of the P-type semiconductor region 1101. Each P-type semiconductor region 1101 and each N-type semiconductor region 1102, together with the intrinsic region between them, form the I-type junction 1103. When a forward voltage is applied to the PIN diode 110, electrons move by quantum tunneling from the N-type semiconductor region 1102 through the I-type junction 1103 into the P-type semiconductor region 1101 to trap the holes generated by radiation.The higher the doping concentration of the P-type semiconductor region 1101 and the N-type semiconductor region 1102, the more quantum states are available between these regions in the I-type junction 1103. This increases the number of charge carriers (electrons or holes) that can enter the conduction band, which in turn allows more electrons to transition into the P-type semiconductor region 1101 via quantum tunneling. Furthermore, the I-type junction 1103 can be formed by using a single dopant via ion implantation. The dopant could, for example, consist of argon ions, which are introduced between the P-type semiconductor region 1101 and the N-type semiconductor region 1102. This further increases the number of available quantum states in the I-type junction 1103.

[0013] Furthermore, the higher the doping concentration of the P-type semiconductor region 1101 and the N-type semiconductor region 1102, the thinner the I-type junction 1103, which is formed between the P-type semiconductor region 1101 and the N-type semiconductor region 1102. The thicknesses of the N-type drift layer 102, the P-type column regions 103, the P-type semiconductor region 1101, and the N-type semiconductor region 1102 can be adjusted according to the desired breakdown voltage of the superjunction MOSFET 1. The P-type semiconductor material can, for example, contain boron ions, indium ions, or gallium ions, while the N-type semiconductor material can consist of, for example, phosphorus ions, arsenic ions, or antimony ions; however, the selection is not limited to these.The N-type semiconductor material, denoted by the symbol "N" in the diagram, and the P-type semiconductor material, denoted by the symbol "P" in the diagram, exhibit opposite electrical properties. The concentration of the semiconductor material is represented by the symbols "+" or "-": "+" indicates a relatively high concentration, while "-" indicates a relatively low concentration. The absence of a "+" or "-" symbol signifies a concentration that lies relatively between these two extremes.

[0014] With reference to Fig. Figure 5 shows the present invention that when irradiated with radiation electrons e - The particles, excited by the radiation, migrate along the direction of the opposite electric field towards substrate 101, which is electrically connected to a drain terminal D. Simultaneously, the resulting holes h move +along the direction of the positive electric field to a gate layer 108, which is electrically connected to a gate terminal G. The holes h + The electrons in the PIN diode 110 are attracted to the I-type junction 1103 and thereby trapped and neutralized. Therefore, the PIN diode 110 can be used to neutralize the holes generated by radiation. + to absorb, effectively preventing holes from being trapped in defect structures of the transistor. At the same time, the accumulation of induced electrical charges at the gate terminal is reduced, thus preventing damage to the device.

[0015] With reference to Fig. 6 in combination with Fig. Figure 5 shows the present invention that the PIN diode 110 can be configured with different doping concentrations [e.g., 10 15 cm -3 , 10 16 cm -3 , 10 17 cm -3 , 10 18 cm -3 , 1019 cm -3 ] can be formed by ion coupling. If the doping concentration of the P-type semiconductor region 1101 and the N-type semiconductor region 1102 at 10 19 cm -3 If the doping concentration is 10, the induced electric field generated by radiation at the gate terminal G can be effectively reduced. This shows that at a doping concentration of 10 19 cm -3 In the PIN diode 110, the coherent and incoherent quantum state energy levels generated by the I-type junction 1103 are able to absorb the tunneling electrons between the P-type semiconductor region 1101 and the N-type semiconductor region 1102. Additionally, the effect of the overlapping synchronous quantum states increases the ability to absorb holes. + significantly improved. The number of absorbed holes h + can be compared to a doping concentration of 10 19 cm -3increased fivefold or more. With reference to Fig. Figure 7 shows the present invention, that the on-resistance R DSon The superjunction MOSFET 1 according to the invention, which is equipped with a PIN diode 110, exhibits different results at different current levels compared to a MOSFET without a PIN diode. In a conventional MOSFET without an embedded PIN diode, the on-resistance is higher at high current (140 A) compared to low current (22 A), resulting in higher power loss at high currents. In contrast, the superjunction MOSFET 1 according to the invention has a lower on-resistance at high current (140 A) compared to low current (22 A). This means that the device exhibits lower power loss at high currents, thereby increasing the energy conversion efficiency.

[0016] With reference to Fig. 8 in combination with Fig. Figure 4 shows that the radiation curing efficiency according to the invention depends on the vertical placement of the PIN diode 110. When the PIN diode 110 is implanted in the upper layer of the N-type drift layer 102 [see Figure 4], the radiation curing efficiency is increased by the vertical placement of the PIN diode 110. Fig. 4] and the gate region 106 is formed on the N-type semiconductor region 1102 of the PIN diode 110, it follows when the circuit is switched on that the holes h + drift towards the gate layer 108. In this position, the PIN diode 110 exhibits the highest efficiency in absorbing the holes h. + , however, the on-resistance R DSon in this case relatively high. However, if the PIN diode 110 is implanted in the middle of the N-type drift layer 102 [see Fig. 8], is the effectiveness of the PIN diode 110 in absorbing the holes h +Although lower than with placement in the upper layer, the on-resistance in this position is relatively low. Fig. Figure 9 shows that the PIN diode 110 is implanted at the lower region of the N-type drift layer 102. When the P-type semiconductor region 1101 is formed on the substrate 101, the effectiveness of the PIN diode 110 in absorbing holes h + This is the lowest of the three positions considered. At the same time, this configuration exhibits the lowest on-resistance R. DSon and thus the lowest power losses. The user can select the position of the PIN diode 110 according to their specific requirements, either to increase the effectiveness in absorbing the holes produced by radiation. + or to optimize the minimization of power losses.

[0017] With reference to Fig. Figure 10 shows that the present invention can also be implemented in an embodiment using silicon carbide (SiC). As shown, the present invention can also be manufactured from silicon carbide (SiC), forming a SiC substrate 201. This substrate is doped with a highly doped N-type semiconductor material and serves as a conductive drain connection. A SiC N-type drift layer 202 is formed on the SiC substrate 201 with a low-doped N-type semiconductor material by ion coupling (ion implantation). Several P-type column regions 103 are formed in the SiC N-type drift layer 202 with a low-doped P-type semiconductor material by ion coupling after a lithography process. These column regions are formed in both the SiC substrate 201 and the SiC-N type drift layer 202 and run parallel to the SiC-N type drift layer 202, resulting in several PN transitions.Several P-type well regions 104 are formed with the P-type semiconductor material on the corresponding P-type column regions 103 by ion coupling. Several N-type source regions 105 are formed with a highly doped N-type semiconductor material within the corresponding P-type well regions 104 by ion coupling. Several SiC gate regions 203 are formed with an N-type semiconductor material on the SiC N-type drift layer 202 between the P-type well regions 104. Several dielectric layers 107 are formed on the SiC gate regions 203 using technologies such as chemical vapor deposition (CVD). Several gate layers 108 are formed on the dielectric layers 107, the material being, for example, polysilicon, but not limited to it. In addition, several I-type regions 109 are embedded in the SiC-N-type drift layer 202.The respective I-type regions 109 are implanted with at least one doped ion, which may, for example, include argon ions. Due to the multitude of quantum states in the I-type regions 109, these can, when the superjunction MOSFET 1 is exposed to radiation, fill in the holes h generated by the radiation. + absorb. By using the I-type areas 109, the trapping of the holes h + This effectively prevents defects in the transistor's structure. Simultaneously, the accumulation of induced electrical charges at the gate terminal is reduced, thus preventing damage to the component.

[0018] With reference to Fig. 11. The aforementioned I-type region 109 can also be replaced by a PIN diode 110. The PIN diode 110 is embedded in the SiC N-type drift layer 202 and comprises a P-type semiconductor region 1101 and an N-type semiconductor region 1102. The P-type semiconductor region 1101 is formed by ion coupling in the SiC N-type drift layer 202, while the N-type semiconductor region 1102 is implanted on the top side of the P-type semiconductor region 1101. Each P-type semiconductor region 1101 and each N-type semiconductor region 1102 form an I-type junction 1103 through their contact. When a forward voltage is applied to the PIN diode 110, electrons move from the N-type semiconductor region 1102 through the I-type junction 1103 into the P-type semiconductor region 1101 via the quantum tunneling effect to capture the holes generated by radiation.The higher the doping concentration of the P-type semiconductor region 1101 and the N-type semiconductor region 1102, the more quantum states are available in the I-type junction 1103 between the P-type semiconductor region 1101 and the N-type semiconductor region 1102. This increases the number of charge carriers that can enter the conduction band, which in turn allows more electrons to enter the P-type semiconductor region 1101 via quantum tunneling. The I-type junction 1103 can also be formed independently by using a single dopant via ion coupling. The dopant can, for example, comprise argon ions implanted between the P-type semiconductor region 1101 and the N-type semiconductor region 1102 to increase the number of available quantum states in the I-type transition 1103.Furthermore, the thickness of the I-type junction 1103 formed by the contact decreases with increasing doping concentration in the P-type semiconductor region 1101 and the N-type semiconductor region 1102. The thicknesses of the SiC N-type drift layer 202, the P-type column regions 103, the P-type semiconductor region 1101, and the N-type semiconductor region 1102 can be adjusted according to the desired breakdown voltage of the superjunction MOSFET 1. The P-type semiconductor material can consist of, for example, boron ions, indium ions, or gallium ions, while the N-type semiconductor material can include, for example, phosphorus ions, arsenic ions, or antimony ions; however, the selection is not limited to these materials. The N-type semiconductor material, labelled “N” in the drawing, and the P-type semiconductor material, labelled “P” in the drawing, have opposite electrical properties.The concentration of semiconductor materials is represented by the symbols "+" and "-": "+" indicates a relatively high concentration, while "-" indicates a relatively low concentration. The absence of a "+" or "-" in the symbol signifies a concentration that lies relatively between these two extremes.

[0019] In the present invention, the PIN diode 110 can be implanted at different vertical positions within the SiC N-type drift layer 202, thereby exhibiting different radiation hardening efficiencies. If the PIN diode 110 is implanted at the upper region of the SiC N-type drift layer 202 and the SiC gate region 203 is formed on the N-type semiconductor region 1102 of the PIN diode 110, the holes drift towards the gate layer 108 after the circuit is switched on. In this configuration, the PIN diode 110 achieves the highest efficiency in absorbing the holes; however, the on-resistance is relatively high in this position. Although the effectiveness in absorbing the holes is lower when the PIN diode 110 is implanted in the middle of the SiC-N-type drift layer 202 than when the PIN diode 110 is placed at the top of the SiC-N-type drift layer 202, the on-resistance in this position is relatively low.When the PIN diode 110 is implanted at the lower region of the SiC N-type drift layer 202, with the P-type semiconductor region 1101 formed on the SiC substrate 201, the hole absorption efficiency of the PIN diode 110 is lowest of the three positions. However, this configuration exhibits the lowest on-resistance, resulting in minimal power losses. The user can select the position of the PIN diode 110 according to their requirements, either to maximize the absorption efficiency of radiation-generated holes or to minimize power losses.

[0020] With reference to Fig. In Section 12, the previously described superjunction MOSFET is explained by way of example in its N-channel MOSFET configuration. However, this configuration can also be replaced by a P-channel MOSFET variant. As shown, the present invention comprises a substrate 301 doped with a highly doped P-type semiconductor material, which serves as a conductive drain terminal. The material of the substrate 301 can be, for example, silicon [Si] or silicon carbide [SiC], but is not limited to these. A P-type drift layer 302, the material of which can be, for example, silicon [Si] or silicon carbide [SiC], but is not limited to these, is formed on the substrate 301 with a low-doped P-type semiconductor material by ion coupling. Several N-type column regions 303 are formed in the P-type drift layer 302 with a low-doped N-type semiconductor material by ion coupling after a lithography process.These regions are located on substrate 301, extend into the P-type drift layer 302, and run parallel to the P-type drift layer 302, thus creating multiple PN junctions. Several N-type well regions 304 are formed with the N-type semiconductor material on the corresponding N-type column regions 303. Several P-type source regions 305 are formed with a highly doped P-type semiconductor material within the N-type well regions 304. Several gate regions 306, whose material can be, for example, silicon [Si] or silicon carbide [SiC], but is not limited to these, are formed with a P-type semiconductor material on the P-type drift layer 302 between the N-type well regions 304. Several dielectric layers 307 are formed on the gate regions 306 using processes such as chemical vapor deposition of silicon [CVD].Several gate layers 308 are formed on the dielectric layers 307, the material being polysilicon, for example, but not limited to it. Furthermore, several I-type regions 309 are embedded in the P-type drift layer 302. The respective I-type regions 309 are implanted with at least one doped ion, for example, argon ions. Due to the multitude of quantum states in the I-type regions 309, these can absorb the holes h generated by the radiation when the superjunction MOSFET 1 is irradiated. By using the I-type regions 309, the trapping of holes h at defect structures of the transistor is effectively prevented, and the accumulation of induced electrical charges at the gate is reduced, thereby avoiding damage to the device.

[0021] With reference to Fig.13. The aforementioned I-type region 309 can also be replaced by a NIP diode 310. The NIP diode 310 is embedded in the P-type drift layer 302 and comprises an N-type semiconductor region 3101 and a P-type semiconductor region 3102. The N-type semiconductor region 3101 is formed by ion coupling into the P-type drift layer 302, while the P-type semiconductor region 3102 is implanted on the top side of the N-type semiconductor region 3101. Each N-type semiconductor region 3101 and each P-type semiconductor region 3102 form an I-type junction 3103 through their contact. When a forward voltage is applied to the NIP diode 310, electrons move by quantum tunneling effect from the P-type semiconductor region 3102 through the I-type junction 3103 into the N-type semiconductor region 3101 to trap the holes h generated by radiation.The higher the doping concentration of the N-type semiconductor region 3101 and the P-type semiconductor region 3102, the more quantum states are available in the I-type junction 3103 between the N-type semiconductor region 3101 and the P-type semiconductor region 3102. This increases the number of charge carriers that can enter the conduction band, allowing more electrons to pass into the N-type semiconductor region 3101 via quantum tunneling. Furthermore, the I-type junction 3103 can also be formed independently by using a single dopant via ion coupling. The dopant can, for example, consist of argon ions implanted between the N-type semiconductor region 3101 and the P-type semiconductor region 3102. This increases the number of available quantum states in the I-type transition 3103.Furthermore, the thickness of the I-type junction 3103 formed by the contact decreases with increasing doping concentration in the N-type semiconductor region 3101 and the P-type semiconductor region 3102. The thicknesses of the P-type drift layer 302, the N-type column regions 303, the N-type semiconductor region 3101, and the P-type semiconductor region 3102 can be adjusted according to the desired breakdown voltage of the superjunction MOSFET 1. The P-type semiconductor material can consist of, for example, boron ions, indium ions, or gallium ions, while the N-type semiconductor material can include, but is not limited to, phosphorus ions, arsenic ions, or antimony ions. The N-type semiconductor material, labelled “N” in the drawing, and the P-type semiconductor material, labelled “P” in the drawing, have opposite electrical properties.The concentration of semiconductor materials is represented by the symbols "+" or "-": the "+" indicates a relatively high concentration, while the "-" indicates a relatively low concentration. The absence of the "+" or "-" in the symbol signifies a concentration between these two extremes.

[0022] In the present invention, the NIP diode 310 can be implanted at different vertical positions within the structure, resulting in different radiation hardening efficiencies. When the NIP diode 310 is implanted at the top of the P-type drift layer 302 and the gate region 303 is formed on the P-type semiconductor region 3102 of the NIP diode 310, the holes drift towards the gate layer 308 after the circuit is switched on. In this position, the NIP diode 310 exhibits the highest hole absorption efficiency, but the on-resistance is relatively high in this configuration. If the NIP diode 310 is implanted in the middle of the P-type drift layer 302, the hole absorption efficiency is lower than when placed at the top of the P-type drift layer 302, but the on-resistance is relatively low in this position.When the NIP diode 310 is implanted at the lower region of the P-type drift layer 302, with the P-type semiconductor region 3101 formed on the substrate 301, the hole absorption efficiency is lowest of the three positions. However, this configuration exhibits the lowest on-resistance and results in the lowest power losses. The user can implant the NIP diode 310 at a suitable position according to their requirements to effectively trap radiation-generated holes while simultaneously reducing power losses.

[0023] As described above, the present invention mainly involves embedding a PIN diode in the N-type drift layer by ion coupling. The PIN diode comprises a P-type semiconductor and an N-type semiconductor, both highly doped to form an I-type junction through their contact. Using the quantum tunneling effect, radiation-generated holes can be efficiently trapped. This not only simplifies the device manufacturing process but also enables effective enhancement of radiation hardening in the mass production of semiconductor devices. This allows for improvements in the effects of Total Ionizing Dose (TID) and Single Event Effect (SEE). Thus, the present invention achieves the objective of providing a superjunction MOSFET capable of effectively enhancing radiation hardening.

[0024] The embodiments described above represent only preferred examples of the present invention and are not intended to limit the scope of protection of the invention. Any equivalent changes or modifications made by those skilled in the art in this field, without departing from the spirit and scope of the invention, shall also be covered by the scope of protection of this invention. Reference symbol list 1 Superjunction MOSFET 101 Substrat 102 N-type drift layer 103 P-type column area 104 P-type tub area 105 N-type source range 106 Gate area 107 dielectric layer 108 Gate layer 109 I-type range 110 PIN diode 1101 P-type semiconductor range 1102 N-type semiconductor range 1103 I-type transition 201 SiC substrate 202 SiC-N type drift layer 203 SiC gate area 301 Substrat 302 P-type drift layer\ 303 N-type column range 304 N-type tub area 305 P-type source range 306 Gate area 307 dielectric layer 308 Gate layer 309 I-type areas 310 NIP diode 3101 N-type semiconductor range 3102 P-type semiconductor range 3103 I-type transition IEC induced electric charge R radiation h hole e electron G Gate connector D Drain connection S Source connection

Claims

Superjunction MOSFET (1) comprising: a substrate (101) doped with a highly doped N-type semiconductor material; an N-type drift layer (102) formed with a low-doped N-type semiconductor material and extending on the substrate (101); several P-type column regions (103), each formed with a low-doped P-type semiconductor material within the N-type drift layer (102); several P-type well regions (104), each formed with the P-type semiconductor material on the respective P-type column regions (103); several N-type source regions (105), each formed with a highly doped N-type semiconductor material within the respective P-type well regions (104); several gate regions (106), each formed with the N-type semiconductor material on the N-type drift layer (102) is formed between the respective P-type trough areas (104);several dielectric layers (107), each formed on the respective gate regions (106); several gate layers (108), each formed on the respective dielectric layers (107); and several I-type regions (109), each embedded in the N-type drift layer (102) and comprising at least one doped ion. Superjunction MOSFET according to claim 1, characterized in that the doped ion of the I-type regions (109) is argon ions. Superjunction MOSFET according to claim 1, characterized in that the material of the substrate (101), the N-type drift layer (102) and the gate regions (106) consists of silicon (Si) or silicon carbide (SiC). Superjunction MOSFET (1) comprising: a substrate (101) doped with a highly doped N-type semiconductor material; an N-type drift layer (102) formed with a low-doped N-type semiconductor material and extending on the substrate (101); several P-type column regions (103), each formed with a low-doped P-type semiconductor material within the N-type drift layer (102); several P-type well regions (104), each formed with the P-type semiconductor material on the respective P-type column regions (103); several N-type source regions (105), each formed with a highly doped N-type semiconductor material within the respective P-type well regions (104); several gate regions (106), each formed with the N-type semiconductor material on the N-type drift layer (102) is formed between the respective P-type trough areas (104);several dielectric layers (107), each formed on the respective gate regions (106); several gate layers (108), each formed on the respective dielectric layers (107); and several PIN diodes (110), each embedded in the N-type drift layer (102), each PIN diode (110) comprising a P-type semiconductor region (1101) and an N-type semiconductor region (1102), the N-type semiconductor region (1102) being formed on the top side of the P-type semiconductor region (1101), and the P-type semiconductor region (1101) and the N-type semiconductor region (1102) forming an I-type junction (1103) through their contact. Superjunction MOSFET according to claim 4, characterized in that each P-type semiconductor region (1101) is formed with a doping concentration of at least 1019cm-3 and each N-type semiconductor region (1102) is formed with a doping concentration of at least 1019cm-3. Superjunction MOSFET according to claim 4, characterized in that the material of the substrate (101), the N-type drift layer (102) and the gate regions (106) is selected from a group consisting of silicon (Si) and silicon carbide (SiC). Superjunction MOSFET according to claim 4, characterized in that the P-type semiconductor material is selected from a group consisting of boron ions, indium ions and gallium ions, and the N-type semiconductor material is selected from a group consisting of phosphorus ions, arsenic ions and antimony ions. Superjunction MOSFET according to claim 4, characterized in that at least one PIN diode (110) is embedded in the middle of the N-type drift layer (102). Superjunction MOSFET according to claim 4, characterized in that at least one PIN diode (110) is embedded in the N-type drift layer (102), wherein the gate region (106) is formed on the N-type semiconductor region (1102) of the PIN diode (110). Superjunction MOSFET according to claim 4, characterized in that at least one PIN diode (110) is embedded in the N-type drift layer (102), wherein the P-type semiconductor region (1101) is formed on the substrate (101). Superjunction MOSFET according to claim 4, characterized in that the I-type junction (1103) is formed independently by the use of a single dopant by means of ion coupling. Superjunction MOSFET according to claim 11, characterized in that the dopant is argon ions. Superjunction MOSFET comprising: a substrate (301) doped with a highly doped P-type semiconductor material; a P-type drift layer (302) formed with a low-doped P-type semiconductor material and extending on the substrate (301); several N-type column regions (303), each formed with a low-doped N-type semiconductor material within the P-type drift layer (302); several N-type well regions (304), each formed with the N-type semiconductor material on the respective N-type column regions (303); several P-type source regions (305), each formed with a highly doped P-type semiconductor material within the respective N-type well regions (304); several gate regions (306), each formed with the P-type semiconductor material on the P-type drift layer (302) is formed between the respective N-type well regions (304); several dielectric layers (307) are formed on the gate regions (306);several gate layers (308) formed on the dielectric layers (307); and several I-type regions (309) each embedded in the P-type drift layer (302) and containing at least one doped ion. Superjunction MOSFET according to claim 13, characterized in that the doped ion of the I-type regions (309) is argon ions. Superjunction MOSFET according to claim 13, characterized in that the material of the substrate (301), the P-type drift layer (302) and the gate regions (306) is selected from a group comprising silicon (Si) and silicon carbide (SiC). Superjunction MOSFET comprising: a substrate (301) doped with a highly doped P-type semiconductor material; a P-type drift layer (302) formed with a low-doped P-type semiconductor material and extending on the substrate (301); several N-type column regions (303), each formed with a low-doped N-type semiconductor material within the P-type drift layer (302); several N-type well regions (304), each formed with the N-type semiconductor material on the respective N-type column regions (303); several P-type source regions (305), each formed with a highly doped P-type semiconductor material within the respective N-type well regions (304); several gate regions (306), each formed with the P-type semiconductor material on the P-type drift layer (302) is formed between the respective N-type well regions (304); several dielectric layers (307) are formed on the gate regions (306);several gate layers (308) each formed on the dielectric layers (307); and several NIP diodes (310) each embedded in the P-type drift layer (302), each NIP diode (310) comprising an N-type semiconductor region (3101) and a P-type semiconductor region (3102), the P-type semiconductor region (3102) being formed on the top side of the N-type semiconductor region (3101), and the N-type semiconductor region (3101) and the P-type semiconductor region (3102) forming an I-type junction (3103) through their contact. Superjunction MOSFET according to claim 16, characterized in that the material of the substrate (301), the P-type drift layer (302) and the gate regions (306) is selected from a group comprising silicon (Si) and silicon carbide (SiC). Superjunction MOSFET according to claim 16, characterized in that the P-type semiconductor material is selected from a group consisting of boron ions, indium ions and gallium ions, and the N-type semiconductor material is selected from a group consisting of phosphorus ions, arsenic ions and antimony ions. Superjunction MOSFET according to claim 16, characterized in that at least one NIP diode (310) is embedded in the middle of the P-type drift layer (302). Superjunction MOSFET according to claim 16, characterized in that at least one NIP diode (310) is embedded in the P-type drift layer (302), wherein the gate region (306) is formed on the P-type semiconductor region (3102) of the NIP diode (310). Superjunction MOSFET according to claim 16, characterized in that at least one NIP diode (310) is embedded in the P-type drift layer (302), wherein the N-type semiconductor region (3101) is formed on the substrate (301). Superjunction MOSFET according to claim 16, characterized in that the I-type junction (3103) is formed independently by the use of a single dopant by means of ion coupling. Superjunction MOSFET according to claim 22, characterized in that the dopant is argon ions.

Images