INPUT OFFSET COMPENSATION FOR A COMPARATOR CIRCUIT

Abstract

A comparator circuit is disclosed. The comparator circuit includes a comparator with a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a chopper circuit configured to alternate the input polarity of an input stage during a first phase and a second phase. The comparator circuit further includes a counter circuit coupled to receive a comparator output signal and a clock signal, the counter circuit being configured to generate a first count during the first phase and a second count during the second phase based on the comparator output signal and the clock signal.The comparator circuit further includes a compensation circuit configured to generate an offset compensation signal based on the first and second count values. The comparator also includes an offset control configured to set the comparator's input offset based on this offset compensation signal.

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