Drain-side full-circle select gate with string zero / one via programming countermeasure

Abstract

A memory device connects drain-side select-gate transistors to couple with a drain side of memory holes of memory cells and is configured to maintain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control device erases and programs the transistor threshold voltage of the drain-side select-gate transistors of one of the strings in one of a plurality of combined erase-program operations. Each of the plurality of combined erase-program operations includes an erase section, a first program section, and a second program section.In response to the fact that one string counter does not match the total number of strings, the control means increments the string counter and erases and programs the transistor threshold voltage of the drain-side select-gate transistors of another of the strings in another of the multitude of combined erase-program operations.

Description

AREA

[0001] This application relates to non-volatile storage devices and the operation of non-volatile storage devices. BACKGROUND

[0002] This section provides background information relating to the technology associated with the present disclosure and therefore does not necessarily represent the state of the art.

[0003] The "Semi-Circle Drain Side Select Gate" (SC-SGD) storage technology offers several advantages, including a reduced die size. SC-SGDs are manufactured using etching technology to cut storage holes, giving them their semi-circular shape and dividing a block or array into different strings. Cutting a storage hole removes at least some sections of the SC-SGD, such as the metal layer that would otherwise shield electrical fields from the channel and / or charge-trapping layer. Therefore, the SC-SGD can be affected by a neighboring electrical field. Consequently, there is a need for improved non-volatile storage devices and operating procedures. SUMMARY

[0004] This section provides a general summary of the present disclosure and does not constitute a comprehensive disclosure of its entire scope or all of its features and benefits.

[0005] One purpose of the present disclosure is to provide a storage device and a method for operating the storage device that address and overcome the aforementioned weaknesses.

[0006] Accordingly, one aspect of the present disclosure consists of providing a memory device that includes drain-side select-gate transistors for coupling to a drain side of each of a plurality of memory holes of memory cells and is configured to maintain a transistor threshold voltage. The plurality of memory holes is arranged in rows, each comprising a plurality of strings. A control means is coupled to the drain-side select-gate transistors of the plurality of memory holes and configured to erase and program the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes associated with one of the plurality of strings in one of a plurality of combined erase-program operations for that one of the plurality of strings.Each of the multitude of combined erase and program operations includes an erase section, a first program section, and a second program section. In response to the fact that a string counter does not correspond to the total set of the multitude of strings, the control means increments the string counter and erases and programs the transistor threshold voltage of the drain-side select-gate transistors of the multitude of memory holes associated with another of the multitude of strings in another of the multitude of combined erase and program operations for the other of the multitude of strings.

[0007] According to another aspect of the disclosure, a controller is also provided that communicates with a memory device. The memory device includes drain-side select-gate transistors for coupling to a drain side of each of a plurality of memory holes of memory cells and is configured to maintain a transistor threshold voltage. The plurality of memory holes is arranged in rows, each comprising a plurality of strings. The controller is configured to instruct the control device to erase and program the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes associated with one of the plurality of strings in one of a plurality of combined erase-program operations for that one of the plurality of strings.Each of the multitude of combined erase and program operations includes an erase section, a first program section, and a second program section. In response to a string counter that does not correspond to the total set of the multitude of strings, the controller is configured to increment the string counter and instruct the memory device to erase and program the transistor threshold voltage of the drain-side select-gate transistors of the multitude of memory holes associated with another of the multitude of strings in another of the multitude of combined erase and program operations for the other of the multitude of strings.

[0008] According to another aspect of the disclosure, a method for operating a memory device is provided. The memory device includes drain-side select-gate transistors for coupling to a drain side of each of a plurality of memory holes of memory cells and is configured to maintain a transistor threshold voltage. The plurality of memory holes is arranged in rows, each comprising a plurality of strings. The method includes the step of erasing and programming the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes associated with one of the plurality of strings in one of a plurality of combined erase-program operations for that one of the plurality of strings. Each of the plurality of combined erase-program operations includes an erase section and a first program section and a second program section.The procedure also includes the step of incrementing the string counter in response to a string counter that does not correspond to a total set of the plurality of strings, and erasing and programming the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes that is assigned to another of the plurality of strings, in another of the plurality of combined erase-programming operations for the other of the plurality of strings.

[0009] Further areas of application will become apparent from the description given here. The description and specific examples in this summary serve only for illustration and are not intended to limit the scope of the present disclosure. DRAWINGS

[0010] The drawings described herein serve only to illustrate selected embodiments and do not represent all possible implementations and are not intended to limit the scope of the present disclosure. Fig. 1A is a block diagram of an exemplary storage device according to aspects of the disclosure; Fig. Figure 1B is a block diagram of an exemplary control circuit, which includes a programming circuit, a counting circuit and a determining circuit according to aspects of the disclosure; Fig. 2 illustrates schematic views of three types of storage architectures that utilize staggered storage strings according to aspects of the revelation; Fig. 3A illustrates a cross-sectional view of exemplary floating-gate memory cells in NAND strings according to aspects of the disclosure; Fig. 3B illustrates a cross-sectional view along a Fig. 3A contact line shown according to aspects of the revelation; Fig. 4A and Fig. 4B illustrate a non-volatile memory in which a charge-capture storage cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner according to aspects of the disclosure; Fig. Figure 5 illustrates an example block diagram of the data capture block of Fig. 1A according to aspects of revelation; Fig. Figure 6A is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of Fig. 1A according to aspects of revelation; Fig. Figure 6B illustrates an exemplary cross-sectional view of a section of one of the blocks of Fig. 6A according to aspects of revelation; Fig. Figure 6C illustrates a diagram of the memory hole diameter in the stack of Fig. 6B according to aspects of revelation; Fig. 6D illustrates a close-up of the stack area. Fig. 6B according to aspects of the revelation; Fig. 7A illustrates a schematic top view of a storage array with a multitude of storage holes according to aspects of the disclosure; Fig. 7B illustrates a cross-sectional view of the storage array according to aspects of the disclosure; Fig. 8A and Fig. 8B illustrates an alternative storage structure without dummy holes according to aspects of the revelation; Fig. 9 presents an example set of threshold voltage distributions according to aspects of the disclosure; Fig. Figure 10 is a diagram illustrating transistor threshold voltage diagrams of full-circle (FC) and semi-circle (SC) drain-side select-gate SGD transistors of a plurality of strings according to aspects of the disclosure; Fig. Figure 11 illustrates steps of a process for erasing and programming drain-side select-gate SGD transistors of a multitude of strings string by string and includes a second string-by-string programming operation after a first programming operation according to aspects of the disclosure; Fig. 12 illustrates diagrams of the transistor threshold voltage of full-circle (FC) and semi-circle (SC) drain-side select-gate SGD transistors of a plurality of strings after they have been erased and programmed string by string using the first programming operation (ERASE-PROG1) and after they have been programmed string by string using the second programming operation (PROG2), according to aspects of the disclosure; Fig. Figure 13 illustrates diagrams of the transistor threshold voltage of full-circle (FC) and semi-circle (SC) drain-side select-gate SGD transistors of a plurality of strings after a pre-pre-programming operation (PREPREPROG), after erasing (EP1), and after string-by-string programming in the second programming operation (PROG2) according to aspects of the disclosure; Fig. Figure 14 illustrates diagrams of the transistor threshold voltage of full-circle (FC) and half-circle (SC) drain-side select-gate SGD transistors of a plurality of strings using the plurality of combined erase-programming operations (ERS-PROG1-PROG2) according to aspects of the disclosure; and Fig. 15 to Fig. 16 illustrate steps of a procedure for operating a storage facility according to aspects of the disclosure.

[0011] To facilitate understanding, identical reference numerals have been used wherever possible to denote identical elements present in all figures. It is assumed that elements disclosed in one embodiment can also be advantageously used in other embodiments without specific mention. DETAILED DESCRIPTION

[0012] The following description provides details intended to aid in understanding the present revelation. In some cases, certain circuits, structures, and techniques have not been described or shown in detail so as not to obscure the revelation.

[0013] In general, this disclosure relates to non-volatile storage devices of a type well suited for use in many applications. The non-volatile storage device and the associated operating methods of this disclosure are described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are provided only to sufficiently clarify the inventive concepts, features, advantages, and objectives so that those skilled in the art can understand and apply the disclosure. In particular, the exemplary embodiments are provided to ensure that this disclosure is comprehensive and fully conveys its scope to those skilled in the art.Numerous specific details are set forth, such as examples of particular components, devices, and methods, to provide a comprehensive understanding of the embodiments of this disclosure. It will be obvious to those skilled in the art that specific details need not be included, that exemplary embodiments can be implemented in many different forms, and that none of this should be interpreted as limiting the scope of the disclosure. In some exemplary embodiments, known processes, known device structures, and known technologies are not described in detail.

[0014] In some storage devices or arrangements, memory cells are interconnected, as in NAND strings within a block or subblock. Each NAND string comprises a number of memory cells connected in series between one or more drain-side select-gate SG transistors (SGD transistors) on the drain side of the NAND string, connected by a bit line, and one or more source-side select-gate SG transistors (SGS transistors) on the source side of the NAND string, connected by a source line. Furthermore, the memory cells may be arranged with a common control gate line (e.g., word line) that acts as a control gate. A set of word lines extends from the source side of a block to the drain side of a block. Memory cells may also be interconnected in other types of strings and in other ways.

[0015] In a 3D memory structure, the memory cells can be arranged in vertical rows in a stack, with the stack consisting of alternating conductive and dielectric layers. The conductive layers act as word lines connected to the memory cells. The memory cells can include data storage cells suitable for storing user data and dummy or non-data storage cells unsuitable for storing user data.

[0016] Before programming certain non-volatile memory devices, the memory cells are typically erased. In some devices, the erasure process removes electrons from the floating gate of the memory cell being erased. Alternatively, the erasure process removes electrons from the charge trap layer.

[0017] Each memory cell can be assigned a data state according to the write data in a programming instruction. Based on its data state, a memory cell either remains in the erased state or is programmed into a programmed data state. For example, in a memory device with three bits per cell, there are eight data states, including the erased state and the programmed state.

[0018] During a programming operation, memory cells are programmed according to a word line programming sequence. For example, programming might begin on the word line on the source side of the block and proceed to the word line on the drain side. In one approach, each word line is fully programmed before the next one is programmed. For example, a first word line, WL0, is programmed with one or more programming pulses until the programming is complete. Next, a second word line, WL1, is programmed with one or more programming pulses until the programming is complete, and so on. A programming pulse might include a set of increasing programming voltages applied to the word line in respective programming loops or programming verification iterations.After each programming voltage, verification operations or stages can be performed to determine whether the programming of the memory cells is complete. If the programming of a memory cell is complete, it can be inhibited from further programming, while the programming of other memory cells continues in subsequent programming loops.

[0019] When creating different rows and strings for a memory structure, a slicing operation (e.g., slit half etch or SHE) can be used. The SHE cut can divide a block (in memory) into multiple strings within the block. While the SHE can form / define the strings, the SHE cut can further divide a string, i.e., bisect the edge memory holes in a string (or roughly cut two equal halves). In this respect, both the SGD and the channel are slit. Slicing a memory hole or string between two adjacent strings is sometimes called on-pitch SGD (OPS). However, because the cells are sliced, the polychannel is exposed to an adjacent SGD electrical field. The channel region near the adjacent SGD can easily be turned on during memory operations (i.e., NAND operations), which can lead to SGD "turn-off," especially after cyclic loading.In particular, semicircular SGDs (SC-SGDs) tend to downshift in cases of cumulative reading difficulties.

[0020] The various aspects of this disclosure may be embodied in the form of a device, a system, a process, or a computer program process. Therefore, aspects of this disclosure may be entirely in the form of a hardware implementation or a software implementation (including, but not limited to, firmware, resident software, microcode, or the like), or they may be a combination of hardware and software components, which may be collectively referred to as a "control device," "circuit," "module," "device," or "system." Furthermore, various aspects of this disclosure may be in the form of a computer program process, embodied, for example, in one or more non-transitory, computer-readable storage media that store computer-readable and / or executable program code.

[0021] Various terms are used herein to describe certain system components. Different companies may refer to the same or a similar component by different names, and this description is not intended to differentiate between components that differ in name but not in function. Where various functional units described in the following disclosure are referred to as "modules," such characterization is not intended to unduly restrict the range of possible implementation mechanisms. For example, a "module" could be implemented as a hardware circuit that includes custom-designed VLSI (Very Large Scale Integration) circuits or gate arrays, or commercially available semiconductors with logic chips, transistors, or other discrete components.In another example, a module can also be implemented in a programmable hardware device such as a user-programmable gate array (FPGA), programmable array logic, programmable logic device, or the like. Furthermore, a module can also be implemented, at least partially, by software executed by various processor types. For example, a module can comprise a segment of executable code representing one or more physical or logical blocks of computer instructions that translate into an object, process, or function. Moreover, it is not necessary for the executable parts of such a module to be physically located together; rather, they can consist of fundamentally different instructions stored in different locations which, when executed together, constitute the specific module and fulfill its stated purpose.The executable code can consist of a single instruction or a set of multiple instructions and can also be distributed across different code segments, different programs, multiple storage devices, etc. In a module implementation as software or partial software, the software components can be stored on one or more computer-readable and / or executable storage media, including, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, devices, or equipment.For the purposes of this disclosure, a computer-readable and / or executable storage medium may generally consist of any tangible and / or non-volatile medium capable of containing and / or storing a program for use by a system, device, processor or apparatus for instruction execution or in connection therewith.

[0022] Likewise, for the purposes of this disclosure, the term "component" can encompass any tangible, physical, and non-volatile device. A component may, for example, take the form of a hardware logic circuit consisting of custom-designed VLSI circuits, gate arrays, or other integrated circuits, or it may consist of commercially available semiconductors including logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic devices. Furthermore, a component could also be implemented as programmable hardware devices such as user-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, and so on.Furthermore, a component can consist of one or more silicon-based integrated circuit devices, such as chips, dies, die layers, and packages, or other discrete electrical components, which are connected to one or more other components in an electrical interconnect configuration via electrical conductors, for example, a printed circuit board (PCB), or the like. Accordingly, a module, as defined above, can in certain embodiments be embodied by a component or implemented as such, and in some cases, the terms module and component can be used synonymously.

[0023] When the term "circuit" is used herein, it includes one or more electrical and / or electronic components that form one or more conductive paths through which electric current can flow. A circuit can exist as a closed-loop configuration or as an open-loop configuration. In a closed-loop configuration, the circuit components may provide a return path for electric current. In contrast, in an open-loop configuration, the circuit components contained within it can still be considered to form a circuit, even though they do not include a return path for electric current. For example, an integrated circuit is referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return path for electric current) or not.In certain exemplary embodiments, a circuit may consist of a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom-designed VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, as well as commercially available semiconductors such as logic chips, transistors, or other discrete components. In another example, a circuit may comprise one or more silicon-based integrated circuit devices, such as chips, dies, die layers, and packages, or other discrete electrical components, connected via electrical conductors, such as a printed circuit board (PCB), to one or more other components in an electrical interconnect configuration.A circuit could also be implemented as a synthesized circuit in relation to a programmable hardware device such as a user-programmable gate array (FPGA), programmable array logic, and / or programmable logic devices, etc. In other exemplary embodiments, a circuit may comprise a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Accordingly, a module, as defined above, may in certain embodiments be embodied by a circuit or implemented as such.

[0024] It is understood that the embodiments disclosed herein may consist of one or more microprocessors and certain stored computer program instructions that control the one or more microprocessors to implement, in conjunction with certain non-processor circuits and other elements, some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions could be implemented by a state machine without any stored program instructions, or as one or more application-specific integrated circuits (ASICs) or free-programmable gate arrays (FPGAs) in which each function, or some combinations of certain functions, is / are implemented as custom logic. A combination of these approaches may also be used.Furthermore, where reference is made below to a “controller”, this shall be understood to include individual circuit components, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), an FPGA and / or a processor with control software, or combinations thereof.

[0025] Furthermore, the terms "program," "software," "software application," and the like, as used herein, refer to a sequence of instructions intended for execution on a computer-implemented system. Accordingly, a "program," "software," "application," "computer program," or "software application" may include a subroutine, a function, a procedure, an object procedure, an object implementation, an executable application, an applet, a servlet, source code, object code, a shared library / dynamic load library, and / or any other sequence of specific instructions intended for execution on a computer system.

[0026] Furthermore, the terms "couple," "coupled," or "coupled," as used herein, shall denote either a direct or an indirect connection. Thus, if a first device couples or is coupled to a second device, this connection may be a direct connection or an indirect connection via other devices (or components) and connections.

[0027] Regarding the use of terms such as "an embodiment," "a configuration," "an exemplary embodiment," "a particular embodiment," or similar terminology herein, these terms are intended to indicate that a particular feature, structure, function, procedure, or property described in connection with the embodiment is found in at least one embodiment of the present disclosure. Therefore, expressions such as "in an embodiment," "in a configuration," "in an exemplary embodiment," etc., may all refer to the same embodiment, but need not; rather, they mean "one or more, but not all, embodiments," unless expressly stated otherwise. Furthermore, the terms "comprehensive," "comprising," "including," and variations thereof are used in a non-exhaustive sense and should therefore be understood as "including, but not limited to, ...“This shall be interpreted as follows unless expressly stated otherwise. Furthermore, an element preceded by “includes ... a” does not, without further limitations, preclude the existence of other identical elements in the process, procedure, system, article, or facility that the element includes.

[0028] Indefinite and definite articles also refer to "one or more" unless expressly stated otherwise. Furthermore, the expression "at least one of A and B," as it may be used herein and / or in the following claims, where A and B are variables specifying a particular object or attribute, refers to a choice of A or B, or both A and B, similar to the expression "and / or." If such an expression contains more than two variables, it is hereby defined as including only one of the variables, any one of the variables, any combination (or subcombination) of any one of the variables, or all of the variables.

[0029] Furthermore, the terms "about" and "approximately," as used herein, apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​(e.g., with the same function or result). In certain cases, these terms may include numerical values ​​rounded to the nearest significant number.

[0030] Furthermore, any enumeration of elements given herein does not imply that some or all of the listed elements are mutually exclusive and / or mutually inclusive, unless expressly stated otherwise. Moreover, the term "set," as used herein, is to be understood as meaning "one or more," and in the case of "sets," according to set theory, this means a multiple (or a multitude) of "one or more," unless expressly stated otherwise.

[0031] The detailed description below refers to the accompanying drawings, which form an integral part thereof. It should be noted that the preceding summary is for illustrative purposes only and is in no way intended to be limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the detailed description below. The description of elements in each figure may refer to elements in the preceding figures. Identical reference numbers may refer to identical elements in the figures, including alternative embodiments of the same elements.

[0032] Fig. Figure 1A is a block diagram of an exemplary storage device. The storage device 100 can include one or more storage dies 108. The storage die 108 includes a memory structure 126 consisting of memory cells, such as an array of memory cells, control logic 110, and read / write circuits 128. The memory structure 126 is addressable via word lines through a row decoder 124 and via bit lines through a column decoder 132. The read / write circuits 128 include several capture blocks SB1, SB2, ... SBp (capture logic) and enable the parallel reading or programming of a side of memory cells. Typically, a controller 122 is included in the same storage device 100 (e.g., a removable memory card) as the one or more storage dies 108.Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0033] The memory structure 126 can be two-dimensional or three-dimensional. The memory structure 126 can comprise one or more arrays of memory cells, including a three-dimensional array. The memory structure 126 can comprise a monolithic three-dimensional memory structure in which multiple memory layers are formed above (and not within) a single substrate, such as a wafer, without intervening substrates. The memory structure 126 can comprise any type of non-volatile memory that is monolithically formed in one or more physical layers of arrays of memory cells and has an active region located above a silicon substrate. The memory structure 126 can be contained within a non-volatile memory device that includes switching logic related to the operation of the memory cells, regardless of whether the associated switching logic is located above or within the substrate.

[0034] The control switching logic 110 works together with the read / write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 enables the control of memory operations at the chip level.

[0035] A memory area 113, for example, can be reserved for programming parameters. These parameters can include a programming voltage, a programming bias, position parameters specifying the positions of memory cells, connector thickness parameters, a verification voltage, and / or similar parameters. The position parameters can specify the position of a memory cell within the entire array of NAND strings, the position of a memory cell within a specific group of NAND strings, the position of a memory cell on a specific layer, and / or similar parameters. The connector thickness parameters can specify the thickness of a connector, the substrate or material from which the connector is made, and / or similar parameters.

[0036] The on-chip address decoder 114 provides an address interface between the address used by the host or a memory controller and the hardware address used by decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word lines, SGS and SGD transistors, and source lines. In one approach, the capture blocks can include bit line drivers. An SGS transistor is a select-gate transistor at the source end of a NAND string, and an SGD transistor is a select-gate transistor at the drain end of a NAND string.

[0037] In some embodiments, some of the components can be combined. In various designs, one or more of the components (alone or in combination), with the exception of the memory structure 126, can be considered as at least one control circuit configured to perform the actions described herein. For example, a control circuit can include any or a combination of the control switching logic 110, the state machine 112, the decoders 114 / 132, the power control module 116, the sensing blocks SBb, SB2, ..., SBp, read / write circuits 128, controller 122, and so on.

[0038] The control circuits can include a programming circuit configured to perform a programming and verification operation for a set of memory cells, wherein: the one set of memory cells comprises memory cells allocated to represent one data state from a plurality of data states, and memory cells allocated to represent another data state from the plurality of data states; wherein the programming and verification operation comprises a plurality of programming and verification iterations, and in each programming and verification iteration, the programming circuit performs a programming operation for the one word line, after which the programming circuit applies a verification signal to the one word line.The control circuits can also include a counting circuit configured to determine a number of memory cells that pass a verification check for one data state. The control circuits can further include a determination circuit configured to determine, based on the amount by which the count exceeds a threshold, a specific programming verification iteration from among the multitude of programming and verification iterations in which a verification check for the other data state is to be performed on the memory cells allocated to represent that other data state.

[0039] For example, Fig. 1B a block diagram of an exemplary control circuit 150, comprising a programming circuit 151, a counting circuit 152 and a determination circuit 153.

[0040] The off-chip controller 122 can include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code engine (ECC engine) 245. The ECC engine can correct a number of read errors caused by the upper bound of a Vth distribution becoming too high. However, in some cases, uncorrectable errors may occur. The techniques provided here reduce the probability of uncorrectable errors.

[0041] The storage device(s) 122a, 122b comprise code, such as a set of instructions, and the processor 122c is operational to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, the processor 122c can access code from a storage device 126a of the memory structure 126, such as a reserved area of ​​memory cells in one or more word lines. For example, the code can be used by the controller 122 to access the memory structure 126, such as for programming, reading, and erasing operations. The code can include boot code and control code (e.g., an instruction set). The boot code is software that initializes the controller 122 during a boot or startup process and enables the controller 122 to access the memory structure 126. The code can be used by the controller 122 to control one or more memory structures 126.After power-on, processor 122c retrieves the boot code from ROM 122a or storage device 126a for execution. The boot code initializes the system components and loads the control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by processor 122c. The control code includes drivers for performing basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0042] In general, the control code may include instructions for performing the functions described herein, including the steps of the flowcharts discussed below, and provide the voltage waveforms, including those discussed below.

[0043] In one embodiment, the host is a data processing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the procedures described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0044] Besides NAND flash memory, other types of non-volatile memory can also be used.

[0045] Semiconductor memory devices include volatile memory devices such as dynamic random-access memory (DRAM) or static random-access memory (SRAM), non-volatile memory devices such as resistive random-access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random-access memory (FRAM), and magnetoresistive random-access memory (MRAM), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0046] The memory devices can be composed of passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching storage element, such as an anti-fuse or a phase-change material, and optionally a control element, such as a diode or a transistor. Furthermore, active semiconductor memory elements, as a non-limiting example, include EEPROM and flash memory device elements, which in some embodiments include elements with a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0047] Multiple memory elements can be configured to be connected in series or so that each element is individually accessible. As a non-restrictive example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of transistors connected in series, comprising memory cells and SG transistors.

[0048] A NAND memory array can be configured to consist of multiple memory strings, where a string comprises several memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. The semiconductor memory elements, located within and / or above a substrate, can be arranged in two or three dimensions, for example, as a two-dimensional memory structure or a three-dimensional memory structure.

[0049] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane.

[0050] In a two-dimensional memory structure, memory elements are typically arranged in a plane (e.g., in a plane in the xy direction) that is essentially parallel to a major surface of a substrate that supports the memory elements. The substrate can be a wafer on top of or within which the layer of memory elements is formed, or it can be a support substrate that is attached to the memory elements after they have been formed. As a non-restrictive example, the substrate can contain a semiconductor such as silicon.

[0051] The memory elements can be arranged in an ordered array within a single storage device level, such as in a multitude of rows and / or columns. However, the memory elements can also be arranged in irregular or non-orthogonal configurations. Each memory element can have two or more electrodes or connecting lines, such as bit lines and word lines.

[0052] A three-dimensional storage array is arranged such that storage elements occupy multiple levels or multiple storage device levels, thereby forming a structure in three dimensions (i.e. in the x, y, and z directions, with the z direction being essentially perpendicular and the x and y directions being essentially parallel to the main surface of the substrate).

[0053] As a non-restrictive example, a three-dimensional storage structure can be arranged vertically as a stack of multiple two-dimensional storage device levels. As another non-restrictive example, a three-dimensional storage array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column containing multiple storage elements. The columns can be arranged in a two-dimensional configuration, e.g., in an xy-plane, resulting in a three-dimensional array of storage elements with elements on multiple vertically stacked storage levels. Other configurations of storage elements in three dimensions can also form a three-dimensional storage array.

[0054] As a non-restrictive example, in a three-dimensional array of NAND strings, the memory elements can be coupled to form a NAND string within a single horizontal (e.g., xy) memory device layer. Alternatively, the memory elements can be coupled to form a vertical NAND string spanning multiple horizontal memory device layers. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory layer, while other strings contain memory elements spanning multiple memory layers. Three-dimensional memory arrays can also be designed in a NOR configuration and in a ReRAM configuration.

[0055] Typically, in a monolithic three-dimensional storage array, one or more storage device levels are formed on top of a single substrate. Optionally, the monolithic three-dimensional storage array can also have one or more storage layers that are at least partially located within the single substrate. As a non-restrictive example, the substrate can contain a semiconductor such as silicon. In a monolithic three-dimensional array, the layers that form each storage device level of the array are usually formed on top of the layers of the storage device levels below them. However, layers of adjacent storage device levels in a monolithic three-dimensional storage array can be shared, or there can be intermediate layers between the storage device levels.

[0056] On the other hand, two-dimensional arrays can be fabricated separately and then bundled together to form a non-monolithic, multi-layered memory device. For example, non-monolithic stacked memories can be constructed by fabricating memory layers on separate substrates and then stacking the memory layers on top of each other. The substrates can be made thinner or removed from the memory device layers before stacking, but because the memory device layers are initially fabricated on separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be fabricated on separate chips and then bundled together to form a stacked-chip memory device.

[0057] Fig. Figure 2 illustrates schematic views of three types of memory architectures that utilize staggered memory strings. For example, reference 201 shows a schematic view of a first exemplary memory architecture, reference 203 shows a schematic view of a second exemplary memory architecture, and reference 205 shows a schematic view of a third exemplary memory architecture. In some embodiments, the memory architecture may include an array of staggered NAND strings, as shown.

[0058] Fig. Figure 2 illustrates blocks 200, 210 of memory cells in an exemplary two-dimensional configuration of memory array 126. Fig. 1A. The memory array 126 can contain many such blocks 200, 210. Each example block 200, 210 includes a number of NAND strings and corresponding bit lines, e.g., BL0, BL1, ..., which are shared among the blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gates of the drain-select gates are connected via a common SGD line. At their other end, the NAND strings are connected to a source-side select gate (SGS), which in turn is connected to a common source line 220. Sixteen word lines, for example, WL0 to WL111, extend between the SGSs and the SGDs. In some cases, dummy word lines containing no user data can be used in the memory array alongside the select-gate transistors. Such dummy word lines can protect the edge data word line from certain edge effects.

[0059] One type of non-volatile memory that can be deployed as a memory array is a floating-gate memory, such as the one described in Fig. 3A and Fig. The type shown in 3B is used. However, other types of non-volatile memory can also be used. As discussed in more detail below, another example, shown in Fig. 4A and Fig. Figure 4B shows a charge-capture memory cell that uses a non-conductive dielectric material instead of a conductive floating gate to store charge non-volatilely. A three-layer dielectric of silicon oxide, silicon nitride, and silicon dioxide (“ONO”) is positioned between a conductive control gate and the surface of a semiconductor substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then modifies the threshold voltage of a portion of the cell channel in a detectable manner. The cell is erased by hot-hole injection into the nitride. A similar cell can be provided in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0060] Another approach uses NROM cells. For example, each NROM cell stores two bits, with a dielectric ONO layer extending across the channel between the source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is achieved by separately reading binary states from the spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0061] Fig. Figure 3A illustrates a cross-sectional view of exemplary floating-gate memory cells 300, 310, and 320 in NAND strings. In this figure, the direction of a bit line or NAND string runs inward, and the direction of a word line runs from left to right. For example, the word line 324 extends across NAND strings that enclose respective channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and the channel region 326. Each memory cell 300, 310, 320 is located in a separate NAND string. An inter-polydielectric (IPD) layer 328 is also illustrated.Control gates 302, 312, and 322 are part of the word line. A cross-sectional view along the connecting line connector 329 is shown in [reference]. Fig. 3B provided.

[0062] The control gate 302, 312, 322 surrounds the floating gate 304, 314, 321, thus increasing the surface contact area between the control gate 302, 312, 322 and the floating gate 304, 314, 321. This results in a higher IPD capacity and therefore a higher coupling ratio, which facilitates programming and erasing. However, when NAND flash memory devices are miniaturized, the distance between adjacent cells 300, 310, 320 decreases, leaving almost no space between two adjacent floating gates 302, 312, 322 for the control gate 302, 312, 322 and the IPD layer 328.

[0063] As an alternative, as in Fig. 4A and Fig. Figure 4B shows the flat or planar memory cell 400, 410, 420 developed, in which the control gate 402, 412, 422 is flat or planar; that is, it does not enclose the floating gate and only makes contact with the charge storage layer 428 from above. In this case, a tall floating gate offers no advantage. Instead, the floating gate is made much thinner. Furthermore, the floating gate can be used to store charge, or a thin charge-trapping layer can be used to trap charge. This approach avoids the problem of ballistic electron transport, in which an electron can migrate through the floating gate after tunneling through the tunnel oxide during programming.

[0064] Fig. Figure 4A shows a cross-sectional view of exemplary charge-trapping memory cells 400, 410, 420 in NAND strings. The view is in the word-direction direction of memory cells 400, 410, 420, which include a flat control gate and charge-trapping regions as a two-dimensional example of memory cells 400, 410, 420 in the memory cell array 126 of Fig. 1A. A charge-capture memory can be used in NOR and NAND flash memory devices. In this technology, an insulator such as a SiN film is used to store electrons, in contrast to floating-gate MOSFET technology, which uses a conductor such as doped polycrystalline silicon to store electrons. For example, a word line 424 extends across NAND strings, enclosing respective channel regions 406, 416, and 426. Sections of the word line provide the control gates 402, 412, and 422. Beneath the word conductor are an IPD layer 428, charge-trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunnel layers 409, 407, 408. Each charge-trapping layer 404, 414, 421 extends uninterrupted within its respective NAND string. The flat configuration of the control gate allows it to be designed thinner than a floating gate.Furthermore, the memory cells can be placed closer together.

[0065] Fig. 4B illustrates a cross-sectional view of the structure of Fig. 4A along the connecting lead connector 429. The NAND string 430 includes an SGS transistor 431, exemplary memory cells 400, 433, ... 435, and an SGD transistor 436. Passages in the IPD layer 428 in the SGS and SGD transistors 431 and 436 allow the control gate layers 402 and the floating gate layers to be interconnected. The control gate layers 402 and the floating gate layers can, for example, be made of polysilicon, and the tunnel oxide layer can be made of silicon oxide. The IPD layer 428 can be a stack of nitrides (N) and oxides (O), as in a NONON configuration.

[0066] The NAND string can be formed on a substrate comprising a p-type substrate region 455, an n-type well 456, and a p-type well 457. Within the p-type well are n-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7. A channel voltage Vch can be applied directly to the channel region of the substrate. Fig. Figure 5 illustrates an example block diagram of the data acquisition block SB1 from Fig. 1A. In one approach, an acquisition block comprises multiple acquisition circuits. Each acquisition circuit is associated with data latches. For example, the sample acquisition circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In this approach, different subsets of bit lines can be acquired using different respective acquisition blocks. This allows the processing load associated with the acquisition circuits to be distributed and handled by a separate processor in each acquisition block. For example, an acquisition circuit controller 560 in SB1 can communicate with the set of acquisition circuits and latches. The acquisition circuit controller 560 can include a preload circuit 561, which provides a voltage for setting a preload voltage for each acquisition circuit.In one possible approach, the voltage is provided independently for each acquisition circuit, for example, via the data bus and a local bus. In another possible approach, a common voltage is applied to each acquisition circuit simultaneously. The acquisition circuit controller 560 can also include a preload circuit 561, a memory 562, and a processor 563. The memory 562 can store code that can be executed by the processor to perform the functions described herein. These functions can include reading the latches 550b, 551b, 552b, and 553b associated with the acquisition circuits 550a, 551a, 552a, and 553a, setting bit values ​​in the latches, and providing voltages to set preload levels in measurement nodes of the acquisition circuits 550a, 551a, 552a, and 553a.Further exemplary details of the 560 detection circuit controller and the 550a, 551a, 552a, 553a detection circuits are provided below.

[0067] In some embodiments, a memory cell may include a flag register, which in turn includes a set of latches that store flag bits. In some embodiments, a number of flag registers may correspond to a number of data states. In some embodiments, one or more flag registers may be used to control some type of verification technique used in verifying memory cells. In some embodiments, the output of a flag bit may modify the associated logic of the device, such as the address decoding switching logic, to select a specific block of cells. A bulk operation (such as an erase operation) may be performed using the flags set in the flag register, or a combination of the flag register and address register, as in implicit addressing, or alternatively, by direct addressing using only the address register.

[0068] Fig. Figure 6A is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126. Fig. 1A. The substrate contains exemplary blocks BLK0, BLK1, BLK2, BLK3 consisting of memory cells (memory elements) and a peripheral area 604 containing switching logic for use by blocks BLK0, BLK1, BLK2, BLK3. For example, the switching logic can include voltage drivers 605 that can be connected to control gate layers of blocks BLK0, BLK1, BLK2, BLK3. In one approach, control gate layers at a common level in blocks BLK0, BLK1, BLK2, BLK3 are jointly controlled. The substrate 601 can also carry switching logic beneath blocks BLK0, BLK1, BLK2, BLK3, along with one or more lower metal layers structured in conductor tracks to transmit signals from the switching logic. Blocks BLK0, BLK1, BLK2, BLK3 are formed in an intermediate area 602 of the memory device.In an upper region 603 of the memory device, one or more upper metal layers are structured in conductive traces to transmit switching logic signals. Each block BLK0, BLK1, BLK2, BLK3 comprises a stacked region of memory cells, with alternating levels of the stack representing word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has stepped opposite sides from which vertical terminals extend upward to an upper metal layer to form connections to conductive traces. Although four blocks BLK0, BLK1, BLK2, BLK3 are illustrated as an example, two or more blocks extending in the x and / or y direction can be used.

[0069] In one possible approach, the length of the plane in the x-direction represents a direction in which signal paths extend to word lines in the one or more upper metal layers (a word line or SGD line direction), and the width of the plane in the y-direction represents a direction in which signal paths extend to bit lines in the one or more upper metal layers (a bit line direction). The z-direction represents a height of the storage device.

[0070] Fig. Figure 6B illustrates an exemplary cross-sectional view of a section of one of the blocks BLK0, BLK1, BLK2, BLK3 of Fig. 6A. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers comprise two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1, in addition to the data word line layers (word lines) WLL0 to WLL10. The dielectric layers are labeled DL0 to DL19. Furthermore, regions of the stack 610 are illustrated that contain the NAND strings NS1 and NS2. Each NAND string encloses a memory hole 618, 619, which is filled with materials that form memory cells adjacent to the word lines. A region 622 of the stack 610 is shown in Fig. 6D is shown in more detail and will be discussed in more detail below.

[0071] The stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a section of a source line SL. NS1 has a source end 613 on the bottom 614 of the stack and a drain end 615 on the top 616 of the stack 610. Connecting line connectors (e.g., slots, such as metal-filled slots) 617, 620 can be provided at regular intervals on the stack 610 as interconnects extending through the stack 610 to connect the source line to a specific connecting line above the stack 610. The connecting line connectors 617, 620 can be used during the formation of the word lines and subsequently filled with metal. A section of a bit line BL0 is also illustrated. A conductive via 621 connects the drain end 615 to BL0.

[0072] Fig. Figure 6C illustrates a graph of the memory hole diameter in the stack of Fig. 6B. The vertical axis is on the stack of Fig. 6B is aligned and illustrates a width (wMH), e.g., the diameter, of memory holes 618 and 619. The word line layers WLL0 to WLL10 of Fig. 6A are again used as an example and are located in the stack at the respective heights z0 to z10. In such a storage device, the storage holes etched through the stack have a very high aspect ratio. A depth-to-diameter ratio of approximately 25 to 30 is typical. The storage holes can have a circular cross-section. Due to the etching process, the width of the storage hole can vary along its length. As a rule, the diameter decreases from top to bottom within the storage hole. That is, the storage holes are conical and narrow at the bottom of the stack. In some cases, there is a slight constriction at the top of the hole near the selector gate, so that the diameter becomes somewhat larger before decreasing from top to bottom within the storage hole.

[0073] Due to the uneven width of the memory hole, the programming speed, including the programming slope and erase speed of the memory cells, can vary based on their position along the memory hole, e.g., their height in the stack. For a memory hole with a smaller diameter, the electric field across the tunnel oxide is relatively stronger, resulting in relatively higher programming and erase speeds. One approach is to define groups of adjacent word lines with similar memory hole diameters, e.g., within a defined diameter range, and to apply an optimized verification scheme to each word line in a group. Different groups can have different optimized verification schemes.

[0074] Fig. 6D shows a close-up of area 622 of stack 610 of Fig. 6B. Memory cells are formed at the different levels of the stack at the interface of a word line layer and a memory hole. In this example, the SGD transistors 680, 681 are provided above the dummy memory cells 682, 683 and a data memory cell MC. A number of layers may be deposited along the side wall (SW) of the memory hole 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., the column formed by the materials within a memory hole 630) may include a charge-trapping layer or film 663 such as SiN or another nitride, a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. A word conduction layer can include a high k-value barrier oxide / block material 660, a metal barrier 661, and a conductive metal 662 such as tungsten as a control gate.For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are located in memory hole 630. In other approaches, some of the layers may be located in the control gate layer. Similarly, additional columns are formed in the various memory holes. A column can form a columnar active region (AA) of a NAND string.

[0075] When a data storage cell MC is programmed, electrons are stored in a section of the charge-trapping layer 663 that is assigned to the memory cell MC. These electrons are drawn from the channel 665 through the tunneling layer 664 into the charge-trapping layer 663. The Vth of a memory cell MC increases proportionally to the amount of stored charge. During an erase operation, the electrons return to the channel 665.

[0076] Each of the storage holes 630 can be filled with a variety of annular layers, comprising a barrier oxide layer, a charge-trapping layer 663, a tunnel layer 664, and a channel layer 665. A core region of each storage hole 630 is filled with a body material, and the variety of annular layers are located between the core region and the word line in each of the storage holes 630.

[0077] The NAND string can be considered to have a floating-body channel 665, since the length of the channel 665 is not formed on a substrate. Furthermore, the NAND string is provided by a multitude of word line layers arranged in a stack and separated from each other by dielectric layers.

[0078] Fig. Figure 7A shows a schematic top view of a memory array 700 with a plurality of memory holes 722, which may be vertical memory cell strings as described herein, and a plurality of dummy holes 705, which need not be a complete memory structure. A shallow trench etch or shallow etch feature (SHE) 710 extends through a plurality of word lines (for example, five), but not completely through the chip, to electrically isolate adjacent strings from one another. SHE extends directly through a group of aligned dummy holes 705, thereby preventing these dummy holes 705 from storing data or otherwise being functional memory cells.

[0079] With reference to Fig. 8A and Fig. There are no dummy holes in 8B. Unlike the 700 memory architecture of Fig. 7A and Fig. 7B SHE 810 is located in a gap between two adjacent rows of memory cells 825 and overlaps with the memory holes 825, creating a working strand into which a trench is etched on at least one side of the SGD switch at the top of the working memory strand, shown here as memory holes 825. This configuration significantly improves the yield of functional memory holes and the memory density, since all memory holes 822, 825 are functional, i.e., fewer memory holes are wasted.

[0080] Unlike the fully circular memory holes 822, the memory holes 825 and the SGD switches, which are partially intersected by SHE 810, have a semicircular shape, which can be either a full semicircle or more or less than a semicircle. In some cases, the memory holes 825 and SGD switches may be less than semicircles on one side of SHE 810 and more than semicircles on the other side of SHE 810.

[0081] Memory holes 822 and 825 are connected to a multitude of bit lines 830 (in Fig. 8A (labeled as bit lines 0-7). For simplicity, only eight bit lines 830 are shown. The bit lines 830 extend across the memory holes and are connected to selected memory holes via connection points. The memory holes in each string region are also connected at one end to an SGD switch and at the other end to an SGS switch. The SHE trench 810 may be etched into a section of the SGD switch. The rows of memory holes 822, 825 between each SHE 810 may each contain a plurality of strings. Starting from the left side of Fig. For example, in 8A, the rows of memory holes 822 and 825 to the left of the leftmost SHE 810 can contain a first string STR0, the rows of memory holes 822 and 825 to the right of the leftmost SHE 810 and to the left of the middle SHE 810 can contain a second string STR1, the rows of memory holes 822 and 825 to the right of the middle SHE 810 and to the left of the rightmost SHE 810 can contain a third string STR2, and the rows of memory holes 822 and 825 to the right of the rightmost SHE 810 can contain a fourth string STR3. It is understood that other arrangements and groupings of memory holes 822 and 825 are also possible for forming strings, and that memory devices can contain any number of strings.

[0082] At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Fig. Figure 9 shows exemplary distributions of the threshold voltage Vt that correspond to the data states for the memory cell array when each memory cell stores three data bits. However, other embodiments may use more or fewer than three data bits per memory cell. Fig. Figure 9 shows eight threshold voltage distributions Vt, corresponding to an extinguishing state and the programmed states AG. In one embodiment, the threshold voltages in the extinguishing state are negative and the threshold voltages in the programmed states AG are positive.

[0083] However, the threshold voltages in one or more of the programmed states AG can be negative. Therefore, in one embodiment, at least VrA is negative. Other voltages such as VvA, VrB, VvB, etc., can also be negative.

[0084] Between the individual data states lie read reference voltages, which are used to read data from memory cells. For example, Fig. 9. The read reference voltage VrA is between the erase state and the A-state, and VrB is between the A-state and the B-state. By testing whether the threshold voltage of a specific memory cell is above or below the respective read reference voltages, the system can determine the state of a memory cell.

[0085] Test reference voltages are located at or near the lower edge of each programmed state. For example, Fig. 9 VvA for state A and VvB for state B. When programming memory cells to a specific state, the system checks whether these memory cells have a threshold voltage greater than or equal to the test reference voltage.

[0086] As explained above, semicircular SGDs (SC-SGDs) tend to downshift when faced with cumulative read errors. The SC-SGD is also susceptible to neighboring string interference (NSI). The downshifting and NSI cause both program glitches and read noise. Fig. Figure 10 is a diagram illustrating the transistor threshold voltage graphs of full-circle (FC) and half-circle (SC) drain-side select-gate SGD transistors of a variety of strings. As shown, full-circle (FC) SGD overprogramming (op) can occur due to the SC-SGD configuration. Fig. Figure 11 illustrates the steps of a process for erasing and programming drain-side select-gate SGD transistors of a large number of strings string by string and includes a second string-by-string programming operation (specified as PROG2) following a first programming operation (specified as PROG1). Such a second string-by-string programming operation, PROG2, after erasing / programming the drain-side select-gate transistors (SGDs) in a first programming operation (unselected SGDs biased to a steady-state voltage VSS), can be used to refresh the transistor threshold voltage of the drain-side select-gate SGD transistors (SGD refresh). During PROG2, the unselected SGDs are biased to a supply voltage VDD. This makes the transistor threshold voltage Vt of the SC-SGD appear low under NSI and is therefore intentionally programmed higher.SGD PROG2 can also be used as a system maintenance feature to ensure that the SGD maintains the correct transistor threshold voltage Vt after extended program / erase (PE) and read cycles. However, PROG2 causes another problem: String 0 / 1 full circuit (FC) SGD over program (OP), as shown in [reference]. Fig. 10.

[0087] Fig. Figure 12 illustrates diagrams of the transistor threshold voltage of full-circle (FC) and half-circle (SC) drain-side select-gate SGD transistors of a large number of strings after they have been erased and programmed string by string using the first programming operation (ERASE-PROG1) and after they have been programmed string by string using the second programming operation (PROG2). After ERASE-PROG1, the SC-SGD includes cells with a relatively low transistor threshold voltage (SC-Low-VT cell). During the PROG2 check of string-0, string-0 is biased to a control-gate reference voltage VCGRV (approximately 2.2 V), and strings 2 and 3 are biased to a supply voltage VDD. The SC-Low-VT cell in strings 2 and 3 is partially turned on below NSI, causing leakage currents.The transistor threshold voltage of string-0 in rows that share the same bit line with string 2 / 3 SC-SGD appears low due to the leakage current through string 2 / 3; therefore, these memory cells receive more programming loops and cause op-amps, and the behavior for string-1 is similar. By the time string 2 / 3 / 4 reaches PROG2, the adjacent string has already passed through PROG2 and reached the lower threshold voltage of the SC-SGD transistor (in ). Fig. 12 (indicated as LLT) is pushed upwards, therefore no leakage current and no operation.

[0088] Fig. Figure 13 illustrates diagrams of the transistor threshold voltage of full-circle (FC) and half-circle (SC) drain-side select-gate SGD transistors for a multitude of strings after a pre-pre-programming operation (PREPREPROG), after erasing (EP1), and after string-by-string programming in the second programming operation (PROG2). To ensure that no leakage current flows from unselected strings during PROG2, the transistor threshold voltage of the SC-SGD must be sufficiently high. During the SGD refresh, the transistor threshold voltage of the drain-side select-gate SGD transistors is high after the pre-pre-programming operation and PROG2, thus allowing the unselected string to be sufficiently clipped.

[0089] Consequently, a storage device (e.g., storage device 100) is included here. Fig. 1A) described, the drain-side select-gate SGD transistors for coupling to a drain side of each of a plurality of memory holes (e.g. memory holes 618 and 619 from Fig. 6B or memory slots 822, 825 from Fig. 8A) of memory cells (e.g. data memory cell MC and dummy memory cells 682, 683 from Fig. 6D). The drain-side select-gate SGD transistors are configured to maintain a transistor threshold voltage. The multitude of memory holes is arranged in rows (e.g., vertical rows of memory holes 822, 825 of Fig. 8A), each comprising a multitude of strings (e.g., STR0, STR1, STR2, STR3, like the rows of memory holes 822, 825 to the left of the far left SHE 810 of Fig. 8A). The storage device also includes a control device (e.g., one or any combination of control switching logic 110, decoders 114 / 132, power control module 116, acquisition blocks SBb, SB2..., SBp, read / write circuits 128, controller 122 of Fig. 1A, control circuit 150 of Fig. 1B and / or reading circuit controller 560 from Fig. 5 etc.), which is coupled to the drain-side select-gate SGD transistors of the plurality of memory holes. The control means is configured to erase and program the transistor threshold voltage of the drain-side select-gate SGD transistors of the plurality of memory holes, which is associated with one of the plurality of strings, in one of a plurality of combined erase-program operations (ERS-PROG1-PROG2) for that one of the plurality of strings (i.e., until the transistor threshold voltage of the drain-side select-gate SGD transistors exceeds a drain-side select-gate test level). Each of the plurality of combined erase-program operations includes an erase section (ERS), a first program section (PROG1), and a second program section (PROG2).In response to the fact that a string counter does not correspond to the total of the multitude of strings, the control means increments the string counter and erases and programs the transistor threshold voltage of the drain-side select-gate SGD transistors of the multitude of memory holes associated with another of the multitude of strings in another of the multitude of combined erase-program operations for that other of the multitude of strings. In other words, the combined erase-program operations are performed string by string (i.e., string by string ERS-PROG1-PROG2) and replace the separate first programming operation ERS-PROG1 and the second programming operation PROG2 of . Fig. 11.

[0090] More precisely, and according to one aspect, the control means is further configured to erase the drain-side select-gate SGD transistors of each of the plurality of memory holes assigned to each of the plurality of strings in the erase section of each of the plurality of combined erase programming operations, by applying an erase bias to the drain-side select-gate SGD transistors of selected of the plurality of memory holes, while simultaneously applying an unselected erase bias to the drain-side select-gate SGD transistors of unselected of the plurality of memory holes.In addition to programming the transistor threshold voltage of the drain-side select-gate SGD transistors of the multitude of memory holes, which is assigned to each of the multitude of strings in the first programming section of each of the multitude of combined erase programming operations, the control means is configured by applying a multitude of programming pulses of increasing strength to the drain-side select-gate SGD transistors of the selected of the multitude of memory holes, while simultaneously applying an initial unselected voltage to the drain-side select-gate SGD transistors of the unselected of the multitude of memory holes during each of the multitude of loops of the first programming section.The control mechanism is also configured to program the transistor threshold voltage of the drain-side select-gate SGD transistors of the multitude of memory holes, which is assigned to each of the multitude of strings in the second programming section of each of the multitude of combined erase programming operations, by applying the multitude of programming pulses of increasing strength to the drain-side select-gate SGD transistors of the selected of the multitude of memory holes, while simultaneously applying a second, non-selected voltage to the drain-side select-gate SGD transistors of the non-selected of the multitude of memory holes during each of the multitude of loops of the second programming section. The second non-selected voltage is greater than the first non-selected voltage. More precisely, and according to another aspect, the first non-selected voltage is a steady-state voltage VSS (e.g.,approximately 0 volts) and the second unselected voltage is a supply voltage VDD.

[0091] As explained above, the array of memory holes includes semicircular arrays, comprising the array of memory holes partially cut out by a slotted half-etch, and full-circle arrays, comprising the array of memory holes that are not cut out. In an additional aspect, the control mechanism is further configured to intentionally program the transistor threshold voltage of the drain-side select-gate SGD transistors of the memory holes in the semicircular arrays to be higher than the transistor threshold voltage of the drain-side select-gate SGD transistors of the memory holes in the full-circle arrays during the second programming section of each of the array's combined erase programming operations.

[0092] Here too, the memory cells are each connected to one of a multitude of word lines. According to further aspects, the control unit is configured, in addition to applying a memory cell programming pulse to the memory cells connected to all of the word lines and all of the multitude of strings prior to the multitude of combined erase programming operations, in order to program the memory cells to an initial memory cell voltage in a preconditioning process. Additionally, the control unit applies a select-gate programming pulse to the drain-side select-gate SGD transistors of one of the multitude of strings in a pre-preprogramming process for that one of the multitude of strings with an initial select-gate voltage.In response to the fact that a pre-pre-programming string counter does not correspond to the total set of the plurality of strings, the control means increments the pre-pre-programming string counter and applies the select-gate programming pulse to the drain-side select-gate SGD transistors of an additional string from the plurality to program the drain-side select-gate SGD transistors of the additional string from the plurality in a further pre-pre-programming operation for the additional string from the plurality with an initial select-gate voltage.

[0093] As explained above, the programming of the drain-side select-gate SGD transistors can be performed as part of a refresh. According to another aspect, the control device is further configured to perform a multitude of combined erase-program operations on at least one of the multitude of strings on a recurring basis to refresh the transistor threshold voltage of the drain-side select-gate SGD transistors. More precisely, and according to other aspects, the control device is further configured to determine whether a predetermined number of erase-program cycles have occurred for the memory cells. The control device is also configured to perform a multitude of combined erase-program operations on at least one of the multitude of strings in response to determining that the predetermined number of erase-program cycles has occurred for the memory cells.

[0094] Fig. Figure 14 illustrates transistor threshold voltage diagrams of full-circle (FC) and half-circle (SC) drain-side select-gate SGD transistors of a multitude of strings using the multitude of combined erase-program operations (ERS-PROG1-PROG2). As shown, the upper border is cleaned up. Thus, the use of the multitude of combined erase-program operations described herein helps to reduce op-amps that can cause programming / reading errors. This reduces the yield and the number of grown faulty blocks (GBB).

[0095] Fig. 15 to Fig. Figure 16 illustrates the steps of a procedure for operating a storage device. As discussed above, the storage device (e.g., storage device 100) excludes Fig. 1A) the drain-side select-gate SGD transistors for coupling to a drain side of each of a plurality of memory holes (e.g. memory holes 618 and 619 from Fig. 6B or memory slots 822, 825 from Fig. 8A) of memory cells (e.g. data memory cell MC and dummy memory cells 682, 683 from Fig. 6D). The drain-side select-gate SGD transistors are configured to maintain a transistor threshold voltage. The multitude of memory holes is arranged in rows (e.g., vertical rows of memory holes 822, 825 of Fig. 8A), each comprising a multitude of strings (e.g., STR0, STR1, STR2, STR3, like the rows of memory holes 822, 825 to the left of the far left SHE 810 of Fig. 8A). Initially referring to Fig. The procedure includes step 1500, which erases and programs the transistor threshold voltage of the drain-side select-gate SGD transistors of the plurality of memory holes associated with one of the plurality of strings in one of a plurality of combined erase-program operations for that one of the plurality of strings. Each of the plurality of combined erase-program operations includes an erase section, a first program section, and a second program section.The procedure also includes step 1502, in response to a string counter that does not correspond to a total set of the plurality of strings, incrementing the string counter and erasing and programming the transistor threshold voltage of the drain-side select-gate SGD transistors of the plurality of memory holes that is assigned to another of the plurality of strings, in another of the plurality of combined erase-programming operations for the other of the plurality of strings.

[0096] More precisely, and according to one aspect, the procedure further includes the step of erasing the drain-side select-gate SGD transistors of each of the plurality of memory holes assigned to each of the plurality of strings in the erase section of each of the plurality of combined erase programming operations by applying an erase bias to the drain-side select-gate SGD transistors of selected of the plurality of memory holes, while simultaneously applying an unselected erase bias to the drain-side select-gate SGD transistors of unselected of the plurality of memory holes.Then, programming the transistor threshold voltage of the drain-side select-gate SGD transistors of the plurality of memory holes, which is assigned to each of the plurality of strings in the first programming section of each of the plurality of combined erase programming operations, by applying a plurality of programming pulses of increasing strength to the drain-side select-gate SGD transistors of the selected of the plurality of memory holes, while simultaneously applying an initial unselected voltage to the drain-side select-gate SGD transistors of the unselected of the plurality of memory holes during each of the plurality of loops of the first programming section.The method also includes the step of programming the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes, which is assigned to each of the plurality of strings in the second programming section of each of the plurality of combined erase-programming operations, by applying the plurality of programming pulses of increasing strength to the drain-side select-gate transistors of the selected of the plurality of memory holes, while simultaneously applying a second unselected voltage to the drain-side select-gate transistors of the unselected of the plurality of memory holes during each of the plurality of loops of the second programming section, the second unselected voltage having a greater strength than the first unselected voltage. Again, according to another aspect, the first unselected voltage is a steady-state voltage VSS (e.g.,approximately 0 volts) and the second unselected voltage is a supply voltage VDD.

[0097] As explained above, the array of memory holes includes semicircular arrays, comprising the array of memory holes partially cut out by a slotted half-etching, and full-circle arrays, comprising the array of memory holes that are not cut out. Therefore, according to an additional aspect, the method further includes the step of intentionally programming the transistor threshold voltage of the drain-side select-gate SGD transistors of the memory holes in the semicircular arrays to a higher value than the transistor threshold voltage of the drain-side select-gate SGD transistors of the memory holes in the full-circle arrays in the second programming section of each of the array's combined erase programming operations.

[0098] Again, each memory cell is connected to one of a multitude of word lines. With particular reference to Fig. 16 and according to other aspects, prior to the multitude of combined erase-programming operations, the procedure includes step 1504 of applying a memory cell programming pulse to the memory cells connected to all of the multitude of word lines and all of the multitude of strings to program the memory cells to an initial memory cell voltage in a preconditioning operation. The procedure proceeds to step 1506 of applying a select-gate programming pulse to the drain-side select-gate SGD transistors of one of the multitude of strings to program the drain-side select-gate SGD transistors of that one of the multitude of strings to an initial select-gate voltage in a pre-preprogramming operation for that one of the multitude of strings. Next, at step 1508, it is determined whether a pre-preprogramming string counter corresponds to a total set of the multitude of strings.The procedure additionally includes step 1510, in response to the fact that a pre-pre-programming string counter does not correspond to the total set of the plurality of strings, incrementing the pre-pre-programming string counter and applying the select-gate programming pulse to the drain-side select-gate SGD transistors of an additional string from the plurality of strings, in order to program the drain-side select-gate SGD transistors of the additional string from the plurality of strings in a further pre-pre-programming operation for the additional string from the plurality of strings with an initial select-gate voltage.

[0099] The process then continues with a multitude of combined deletion and programming operations. More precisely, the process begins with Fig.16 to step 1500 of erasing and programming the transistor threshold voltage of the drain-side select-gate SGD transistors of the plurality of memory holes associated with one of the plurality of strings, in one of a plurality of combined erase-programming operations for that one of the plurality of strings, each of the plurality of combined erase-programming operations including an erase section and a first programming section and a second programming section. Next, at 1512, it is determined whether a string counter corresponds to a total set of the plurality of strings.The procedure also includes step 1502, in response to a string counter that does not correspond to a total set of the plurality of strings, incrementing the string counter and erasing and programming the transistor threshold voltage of the drain-side select-gate SGD transistors of the plurality of memory holes that is assigned to another of the plurality of strings, in another of the plurality of combined erase-programming operations for the other of the plurality of strings.

[0100] As above, the programming of the drain-side select-gate SGD transistors can again be performed as part of a transistor threshold voltage refresh. Therefore, according to another aspect, the method further includes the step of performing the plurality of combined erase-program operations on at least one of the plurality of strings on a recurring basis to refresh the transistor threshold voltage of the drain-side select-gate SGD transistors. According to other aspects, the method further includes the step of determining whether a predetermined number of erase-program cycles has occurred for the memory cells. The method also includes the step of performing the plurality of combined erase-program operations on at least one of the plurality of strings in response to determining that the predetermined number of erase-program cycles has occurred for the memory cells.

[0101] Obviously, modifications can be made to what is described and illustrated herein without departing from the scope of protection defined in the appended claims. The foregoing description of the embodiments serves for illustration and description purposes. It makes no claim to completeness and is not intended to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable and may be used in a selected embodiment, even if they are not specifically shown or described. These can also be varied in many ways. Such variations are not to be considered a deviation from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

Claims

[1] Storage device, comprising: Drain-side select-gate transistors for coupling to a drain side of each of a plurality of memory holes of memory cells and configured to maintain a transistor threshold voltage, the plurality of memory holes being arranged in rows, each comprising a plurality of strings; and a control device coupled to the drain-side select-gate transistors of the multitude of memory holes and configured to: Erasing and programming the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes associated with one of the plurality of strings, in one of a plurality of combined erase-programming operations for one of the plurality of strings, each of the plurality of combined erase-programming operations including an erase section and a first programming section and a second programming section, and in response to a string counter that does not correspond to the total quantity of the multitude of strings, incrementing the string counter and erasing and programming the transistor threshold voltage of the drain-side select-gate transistors of the multitude of memory holes that is assigned to another of the multitude of strings, in another of the multitude of combined erase-programming operations for the other of the multitude of strings. [2] Storage device according to claim 1, wherein the control means is further configured to: Erasing the drain-side select-gate transistors of each of the plurality of memory holes assigned to each of the plurality of strings in the erase section of each of the plurality of combined erase programming operations, by applying an erase bias to the drain-side select-gate transistors of selected of the plurality of memory holes, while simultaneously applying an unselected erase bias to the drain-side select-gate transistors of unselected of the plurality of memory holes; Programming the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes, which is assigned to each of the plurality of strings in the first programming section of each of the plurality of combined erase-programming operations, by applying a plurality of programming pulses of increasing strength to the drain-side select-gate transistors of the selected of the plurality of memory holes, simultaneously applying an initial unselected voltage to the drain-side select-gate transistors of the unselected of the plurality of memory holes during each of the plurality of loops of the first programming section; and Programming the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes, which is assigned to each of the plurality of strings in the second programming section of each of the plurality of combined erase programming operations, by applying the plurality of programming pulses of increasing strength to the drain-side select-gate transistors of the selected of the plurality of memory holes, simultaneously applying a second unselected voltage to the drain-side select-gate transistors of the unselected of the plurality of memory holes during each of the plurality of loops of the second programming section, wherein the second unselected voltage has a greater strength than the first unselected voltage. [3] Storage device according to claim 2, wherein the first unselected voltage is a constant voltage and the second unselected voltage is a supply voltage. [4] Memory device according to claim 1, wherein the rows of the plurality of memory holes include semicircular rows comprising the plurality of memory holes that are partially cut by a slot half-etching, and full circular rows comprising the plurality of memory holes that are not cut, and wherein the control means is further configured to intentionally program the transistor threshold voltage of the drain-side select-gate transistors of the memory holes of the semicircular rows higher than the transistor threshold voltage of the drain-side select-gate transistors of the memory holes of the full circular rows in the second programming section of each of the plurality of combined erase programming operations. [5] Storage device according to claim 1, wherein the memory cells are each connected to one of a plurality of word lines and the control means is further configured before the plurality of combined erase programming operations to: Applying a memory cell programming pulse to the memory cells connected to all of the word lines and all of the multitude of strings, in order to program the memory cells to an initial memory cell voltage in a preconditioning process; Applying a select-gate programming pulse to the drain-side select-gate transistors of one of the plurality of strings to program the drain-side select-gate transistors of that one of the plurality of strings in a pre-pre-programming operation for that one of the plurality of strings with an initial select-gate voltage; and In response to the fact that a pre-pre-programming string counter does not correspond to the total set of the multitude of strings, the pre-pre-programming string counter is incremented and the select-gate programming pulse is applied to the drain-side select-gate transistors of an additional string from the multitude in order to program the drain-side select-gate transistors of the additional string from the multitude in a further pre-pre-programming operation for the additional string from the multitude with an initial select-gate voltage. [6] Storage device according to claim 1, wherein the control means is further configured to perform the plurality of combined erase programming operations for at least one of the plurality of strings on a recurring basis in order to refresh the transistor threshold voltage of the drain-side select-gate transistors. [7] Storage device according to claim 6, wherein the control means is further configured to: Determine whether a predetermined number of erase and program cycles have taken place for the memory cells; and Performing the multitude of combined erase-programming operations for at least one of the multitude of strings in response to determining that the predetermined number of erase-programming cycles has taken place for the memory cells. [8] Controller in communication with a memory device which includes drain-side select-gate transistors for coupling to a drain side of each of a plurality of memory holes of memory cells and is configured to maintain a transistor threshold voltage, wherein the plurality of memory holes are arranged in rows, each comprising a plurality of strings, wherein the controller is configured to: Instructing the memory device to erase and program the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes associated with one of the plurality of strings, in one of a plurality of combined erase-programming operations for one of the plurality of strings, each of the plurality of combined erase-programming operations comprising an erase section and a first programming section and a second programming section; and in response to a string counter that does not correspond to the total quantity of the multitude of strings, incrementing the string counter and instructing the memory device to erase and program the transistor threshold voltage of the drain-side select-gate transistors of the multitude of memory holes that is assigned to another of the multitude of strings, in another of the multitude of combined erase-programming operations for the other of the multitude of strings. [9] Controller according to claim 8, wherein the controller is further configured to: Instructing the memory device to erase the drain-side select-gate transistors of each of the plurality of memory holes assigned to each of the plurality of strings in the erase section of each of the plurality of combined erase programming operations, by applying an erase bias to the drain-side select-gate transistors of selected of the plurality of memory holes, while simultaneously applying an unselected erase bias to the drain-side select-gate transistors of unselected of the plurality of memory holes; Instructing the memory device to program the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes, which is assigned to each of the plurality of strings in the first programming section of each of the plurality of combined erase-programming operations, by applying a plurality of programming pulses of increasing intensity to the drain-side select-gate transistors of the selected of the plurality of memory holes, simultaneously applying an initial unselected voltage to the drain-side select-gate transistors of the unselected of the plurality of memory holes during each of the plurality of loops of the first programming section; and Instructing the memory device to program the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes, which is assigned to each of the plurality of strings in the second programming section of each of the plurality of combined erase programming operations, by applying the plurality of programming pulses of increasing strength to the drain-side select-gate transistors of the selected of the plurality of memory holes, simultaneously applying a second unselected voltage to the drain-side select-gate transistors of the unselected of the plurality of memory holes during each of the plurality of loops of the second programming section, the second unselected voltage having a greater strength than the first unselected voltage. [10] Controller according to claim 9, wherein the first unselected voltage is a constant voltage and the second unselected voltage is a supply voltage. [11] Controller according to claim 8, wherein the rows of the plurality of memory holes include semicircular rows comprising the plurality of memory holes that are partially cut by a slot half-etching, and full circular rows comprising the plurality of memory holes that are not cut, and wherein the controller is further configured to intentionally program the transistor threshold voltage of the drain-side select-gate transistors of the memory holes of the semicircular rows higher than the transistor threshold voltage of the drain-side select-gate transistors of the memory holes of the full circular rows in the second programming section of each of the plurality of combined erase programming operations. [12] Controller according to claim 8, wherein the memory cells are each connected to one of a plurality of word lines and the controller is further configured before the plurality of combined erase programming operations to: Instructing the memory device to apply a memory cell programming pulse to the memory cells connected to all of the word lines and all of the plurality of strings in order to program the memory cells to an initial memory cell voltage in a preconditioning process; Instructing the memory device to apply a select-gate programming pulse to the drain-side select-gate transistors of one of the plurality of strings in order to program the drain-side select-gate transistors of that one of the plurality of strings with an initial select-gate voltage in a pre-pre-programming operation for that one of the plurality of strings; and In response to the fact that a pre-pre-programming string counter does not correspond to the total set of the plurality of strings, increment the pre-pre-programming string counter and instruct the memory device to apply the select-gate programming pulse to the drain-side select-gate transistors of an additional string from the plurality of strings in order to program the drain-side select-gate transistors of the additional string from the plurality of strings in a further pre-pre-programming operation for the additional string from the plurality of strings with an initial select-gate voltage. [13] Controller according to claim 8, wherein the controller is further configured to perform the plurality of combined erase programming operations for at least one of the plurality of strings on a recurring basis in order to refresh the transistor threshold voltage of the drain-side select-gate transistors. [14] Method for operating a memory device which includes drain-side select-gate transistors for coupling to a drain side of each of a plurality of memory holes of memory cells and is configured to maintain a transistor threshold voltage, wherein the plurality of memory holes are arranged in rows, each comprising a plurality of strings, the method comprising the following steps: Erasing and programming the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes associated with one of the plurality of strings, in one of a plurality of combined erase-programming operations for one of the plurality of strings, each of the plurality of combined erase-programming operations comprising an erase section and a first programming section and a second programming section; and in response to a string counter that does not correspond to the total quantity of the multitude of strings, incrementing the string counter and erasing and programming the transistor threshold voltage of the drain-side select-gate transistors of the multitude of memory holes that is assigned to another of the multitude of strings, in another of the multitude of combined erase-programming operations for the other of the multitude of strings. [15] The method of claim 14, further comprising the following steps: Erasing the drain-side select-gate transistors of each of the plurality of memory holes assigned to each of the plurality of strings in the erase section of each of the plurality of combined erase programming operations, by applying an erase bias to the drain-side select-gate transistors of selected of the plurality of memory holes, while simultaneously applying an unselected erase bias to the drain-side select-gate transistors of unselected of the plurality of memory holes; Programming the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes, which is assigned to each of the plurality of strings in the first programming section of each of the plurality of combined erase-programming operations, by applying a plurality of programming pulses of increasing strength to the drain-side select-gate transistors of the selected of the plurality of memory holes, simultaneously applying an initial unselected voltage to the drain-side select-gate transistors of the unselected of the plurality of memory holes during each of the plurality of loops of the first programming section; and Programming the transistor threshold voltage of the drain-side select-gate transistors of the plurality of memory holes, which is assigned to each of the plurality of strings in the second programming section of each of the plurality of combined erase programming operations, by applying the plurality of programming pulses of increasing strength to the drain-side select-gate transistors of the selected of the plurality of memory holes, simultaneously applying a second unselected voltage to the drain-side select-gate transistors of the unselected of the plurality of memory holes during each of the plurality of loops of the second programming section, wherein the second unselected voltage has a greater strength than the first unselected voltage. [16] Method according to claim 15, wherein the first unselected voltage is a permanent voltage and the second unselected voltage is a supply voltage. [17] Method according to claim 14, wherein the rows of the plurality of memory holes include semicircular rows comprising the plurality of memory holes that are partially cut by a slot half-etching, and full circular rows comprising the plurality of memory holes that are not cut, and wherein the method further includes the step of intentionally programming the transistor threshold voltage of the drain-side select-gate transistors of the memory holes of the semicircular rows higher than the transistor threshold voltage of the drain-side select-gate transistors of the memory holes of the full circular rows in the second programming section of each of the plurality of combined erase programming operations. [18] Method according to claim 14, wherein the memory cells are each connected to one of a plurality of word lines and the method includes the following steps prior to the plurality of combined erase programming operations: Applying a memory cell programming pulse to the memory cells connected to all of the word lines and all of the multitude of strings, in order to program the memory cells to an initial memory cell voltage in a preconditioning process; Applying a select-gate programming pulse to the drain-side select-gate transistors of one of the plurality of strings to program the drain-side select-gate transistors of that one of the plurality of strings in a pre-pre-programming operation for that one of the plurality of strings with an initial select-gate voltage; and In response to the fact that a pre-pre-programming string counter does not correspond to the total set of the multitude of strings, the pre-pre-programming string counter is incremented and the select-gate programming pulse is applied to the drain-side select-gate transistors of an additional string from the multitude in order to program the drain-side select-gate transistors of the additional string from the multitude in a further pre-pre-programming operation for the additional string from the multitude with an initial select-gate voltage. [19] Method according to claim 14, further comprising the step of performing the plurality of combined erase programming operations for at least one of the plurality of strings on a recurring basis to refresh the transistor threshold voltage of the drain-side select-gate transistors. [20] The method of claim 19, further comprising the following steps: Determine whether a predetermined number of erase and program cycles have taken place for the memory cells; and Performing the multitude of combined erase-programming operations for at least one of the multitude of strings in response to determining that the predetermined number of erase-programming cycles has taken place for the memory cells.

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