Semiconductor device

Abstract

A semiconductor device according to the present disclosure comprises: a semiconductor substrate; a first trench provided in the semiconductor substrate such that it penetrates a fourth semiconductor layer, a third semiconductor layer, and a second semiconductor layer and reaches a first semiconductor layer; an intermediate insulating layer provided such that it covers the first trench;and a second trench provided in the semiconductor substrate such that it penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer, the first trench having a lower electrode provided on the side of the second main surface and an upper electrode provided on the side of the first main surface with respect to the lower electrode, the second trench having a dummy electrode electrically connected to the first main electrode, and a maximum width of the dummy electrode being equal to or greater than a maximum width of the lower electrode.

Description

Background of the invention; Field of the invention

[0001] The present disclosure relates to a semiconductor device whose conduction is controlled by a gate signal. Description of the state of the art

[0002] A conventionally disclosed semiconductor device has a trench with an upper electrode and a lower electrode (see, for example, Japanese Patent Application Disclosure No. 2014-60362, Japanese Patent Application Disclosure No. 2019-12813, Japanese Patent Application Disclosure No. 2017-147431, and Japanese Patent Application Disclosure No. 2021-72418).

[0003] If a high dl / dt (recovery current of antiparallel diodes) is applied to the semiconductor device in an OFF state in a conventional semiconductor device, there is a possibility that a gate potential of the semiconductor device will increase due to a faulty turn-on.

[0004] This describes a mechanism in which the gate potential of a semiconductor device increases due to faulty turn-on. The device consists of an upper electrode connected to a gate potential and a lower electrode connected to an emitter potential in a gate-electrode subdivision structure. When a voltage is applied between the collector and emitter of the semiconductor device, holes accumulate around the lower electrode in a trench, and a displacement current flows from the collector to the lower electrode. Because the lower electrode has a small cross-sectional area and high resistance, its potential increases. When the potential of the lower electrode is greater than the potential of the upper electrode, a displacement current flows from the lower electrode to the upper electrode.If the potential of the upper electrode exceeds a threshold voltage, the semiconductor device is switched on incorrectly. If the semiconductor device, which forms an inverter or the like, is switched on incorrectly, a short circuit of one arm occurs. Summary

[0005] The present disclosure was made to solve such a problem, and one of its purposes is to provide a semiconductor device capable of preventing the occurrence of faulty switching on.

[0006] A semiconductor device according to the present disclosure comprises: a semiconductor substrate having a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of the first conductivity type, which is selectively provided in an upper part of the third semiconductor layer; a first main electrode provided on one side of a first main surface of the semiconductor substrate such that it is in contact with the fourth semiconductor layer; a second main electrode provided on one side of a second main surface which faces the first main surface of the semiconductor substrate;a first trench provided in the semiconductor substrate such that it penetrates the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer and reaches the first semiconductor layer; an intermediate insulating layer provided such that it covers the first trench;and a second trench provided in the semiconductor substrate such that it penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer, wherein the first trench has a lower electrode provided on the side of the second main surface and an upper electrode provided on the first main surface in relation to the lower electrode, wherein the second trench has a dummy electrode electrically connected to the first main electrode, and wherein a maximum width of the dummy electrode is equal to or greater than a maximum width of the lower electrode.

[0007] According to the present disclosure, it is possible to prevent the faulty switching on.

[0008] These and other tasks, features, aspects and advantages of the present revelation will become clearer based on the following detailed description of the present revelation in conjunction with the accompanying figures. Brief description of the characters Fig. Figure 1 is a cross-sectional view of a semiconductor device according to a first preferred embodiment; Fig. Figure 2 is a cross-sectional view of a semiconductor device according to a second modification of the first preferred embodiment; Fig. Figure 3 is a cross-sectional view of a semiconductor device according to a fourth modification of the first preferred embodiment; Fig. Figure 4 is a cross-sectional view of a semiconductor device according to a fifth modification of the first preferred embodiment; Fig. Figure 5 is a cross-sectional view of a semiconductor device according to a sixth modification of the first preferred embodiment; Fig. Figure 6 is a cross-sectional view of a semiconductor device according to a seventh modification of the first preferred embodiment; Fig. Figure 7 is a cross-sectional view of a semiconductor device according to a ninth modification of the first preferred embodiment; Fig. Figure 8 is a cross-sectional view of a semiconductor device according to an eleventh modification of the first preferred embodiment; Fig. Figure 9 is a cross-sectional view of a semiconductor device according to a twelfth modification of the first preferred embodiment; and Fig. Figure 10 is a top view of a semiconductor device according to a thirteenth modification of the first preferred embodiment. Description of preferred embodiments<Erste bevorzugte Ausführungsform>

[0009] Semiconductor devices according to preferred embodiments are described below with reference to the figures. The semiconductor device is, for example, an insulated-gate bipolar transistor (IGBT). It should be noted that identical or corresponding components are identified by the same reference numerals, and repetition of the description may be omitted. In the following description, N and P represent conductivity types of a semiconductor. In the present disclosure, a first conductivity type is described as an N type, and a second conductivity type is described as a P type. These conductivity types may be inversely related.

[0010] Fig. Figure 1 is a cross-sectional view of a semiconductor device according to a first preferred embodiment. Fig. 1. A semiconductor substrate extends from an N+ emitter 4 and a P+ contact 5 to a P collector layer 7. In Fig. In the figure, the upper ends of the N+ emitter 4 and the P+ contact 5 are referred to as a first principal surface of the semiconductor substrate, and a lower end of the P collector layer 7 in the figure is referred to as a second principal surface of the semiconductor substrate. The first principal surface and the second principal surface face each other.

[0011] As in Fig. As illustrated in Figure 1, a charge carrier accumulation layer 2 of type N is provided on the side of the first principal surface of an N-drift layer 1 of type N (on the N-drift layer 1). The N-drift layer 1 corresponds to a first semiconductor layer, and the charge carrier accumulation layer 2 corresponds to a second semiconductor layer.

[0012] A P-type base layer 3 is provided on the side of the first main surface of the charge carrier accumulation layer 2. The N-type N+ emitter 4 and the P-type P+ contact 5 are selectively provided in an upper layer portion (a layer portion on the side of the first main surface) of the P-type base layer 3. The P-type base layer 3 corresponds to a third semiconductor layer, and the N+ emitter 4 corresponds to a fourth semiconductor layer.

[0013] The semiconductor substrate is provided with a first trench 8, which penetrates the N+ emitter 4, the P base layer 3, and the charge carrier accumulation layer 2, reaching the N- drift layer 1. The first trench 8 has a lower electrode 9, which is provided on the side of the second main surface, and an upper electrode 10, which is provided on the side of the first main surface with respect to the lower electrode 9. Furthermore, the first trench 8 has an insulating layer 11, which is provided on a side wall and a bottom of the first trench 8, so that the lower electrode 9 and the upper electrode 10 are covered.In the insulating layer 11, a portion provided on the side wall and bottom of the first trench 8, covering the lower electrode 9, is referred to as the lower insulating layer, and a portion provided on the side wall of the first trench 8, covering the upper electrode 10, is referred to as the upper insulating layer. Furthermore, a portion enclosed between the lower electrode 9 and the upper electrode 10 is referred to as the boundary insulating layer. It should be noted that the first trench 8 may have a tapered shape, tapering from the first main surface towards the second main surface. In this case, the lower electrode 9 and the upper electrode 10 also have a tapered shape.

[0014] The semiconductor substrate is provided with a second trench 12, which penetrates the P+ contact 5, the P base layer 3, and the charge carrier accumulation layer 2, reaching the N- drift layer 1. The second trench 12 has a dummy electrode 13, which is electrically connected to an emitter electrode 16. Furthermore, the second trench 12 has a dummy insulating layer 14, which is provided on a side wall and a bottom of the second trench 12, so that it covers the dummy electrode 13. The thickness of the dummy insulating layer 14 can be constant.

[0015] The dummy electrode 13 has a side surface that is provided in a straight line along the side wall of the second trench 12. Here, the straight line refers to a continuous shape without a step. The second trench 12 may have a tapered shape, tapering from the first main surface towards the second main surface. In this case, the dummy electrode 13 also has a tapered shape.

[0016] The maximum width of the dummy electrode 13 is equal to or greater than the maximum width of the lower electrode 9. For example, the maximum width of the dummy electrode 13 is 1.1 times or more than the maximum width of the lower electrode 9. Here, the width of the dummy electrode 13 refers to a length of the dummy electrode 13 in a direction perpendicular to a direction connecting the first principal surface and the second principal surface. The same applies to the width of the lower electrode 9.

[0017] On the first main surface of the semiconductor substrate, an intermediate insulating layer 15 is provided such that it covers both the first trench 8 and the second trench 12. The emitter electrode 16 is provided such that it covers the first main surface (the N+ emitter 4 and the P+ contact 5) of the semiconductor substrate and the intermediate insulating layer 15. The emitter electrode 16 corresponds to a first main electrode.

[0018] An N-type buffer 6 is provided on the side of the second main surface of the N-drift layer 1. The P-collector layer 7 is provided on the side of the second main surface of the N-buffer 6. A collector electrode 17 is provided such that it covers the second main surface (P-collector layer 7) of the semiconductor substrate. The collector electrode 17 corresponds to a second main electrode.

[0019] In the first preferred embodiment, the second trench 12 is provided adjacent to the first trench 8 with a space between them, and the dummy electrode 13 of the second trench 12 has a larger cross-sectional area and thus lower resistance. When a high dl / dt (recovery current of antiparallel diodes) is applied to the semiconductor device in an OFF state, holes are likely to flow to the dummy electrode 13 of the second trench 12. As a result, it is less likely that the potential of the lower electrode 9 will increase, and faulty turn-on of the semiconductor device can be prevented. <Erste Modifikation>

[0020] In a semiconductor device according to a first modification, the thickness of a lower insulating layer provided on the bottom of the first trench 8 and the thickness of a dummy insulating layer provided on the bottom of the second trench 12 are thinner than the thickness of a dummy insulating layer provided on the side wall of the second trench 12. Here, the thickness of the lower insulating layer provided on the bottom of the first trench 8 refers to a length of the lower insulating layer in the direction connecting the first main surface and the second main surface.

[0021] An insulating layer exhibits low resistance at a location where its thickness is thin. Therefore, it is likely that holes will pass, particularly from the bottom of the second trench 12, which can help prevent the faulty activation of the semiconductor device. <Zweite Modifikation>

[0022] Fig. Figure 2 is a cross-sectional view of a semiconductor device according to a second modification. As in Fig. As illustrated in Figure 2, the dummy electrode 13 is covered by the emitter electrode 16. Specifically, the intermediate insulating layer 15 is not provided on the second trench 12, and the dummy electrode 13 is in contact with the emitter electrode 16.

[0023] Since the interlayer insulating layer 15 is not provided on the second trench 12, the wiring resistance from the dummy electrode 13 to the emitter electrode 16 is extremely low, and holes flow directly to the emitter electrode 16 through the dummy electrode 13. Therefore, it is possible to contribute to preventing the faulty switching on of the semiconductor device. <Dritte Modifikation>

[0024] In a semiconductor device according to a third modification, the thickness of the dummy insulating layer 14 is thinner than the thickness of the lower insulating layer provided on the side wall and bottom of the first trench 8, so that the lower electrode 9 is covered.

[0025] Since the cross-sectional area of ​​the dummy electrode 13 is increased by increasing the thickness of the dummy insulating layer 14, the wiring resistance from the dummy electrode 13 to the emitter electrode 16 can be reduced. Furthermore, since a parasitic capacitance between the emitter and the collector, formed by the dummy insulating layer 14, is increased by decreasing the thickness of the dummy insulating layer 14, the impedance of the parasitic capacitance between the emitter and the collector can be reduced, and it is likely that leakage current will flow to the dummy electrode 13 of the second trench 12. <Vierte Modifikation>

[0026] Fig. Figure 3 is a cross-sectional view of a semiconductor device according to a fourth modification. As in Fig. As illustrated in Figure 3, the lower electrode 9 and the upper electrode 10 are connected to a gate potential (gate electrode, which is not illustrated).

[0027] The combined cross-sectional area of ​​the two electrodes, the lower electrode 9 and the upper electrode 10, can be smaller than the cross-sectional area when the lower electrode 9 and the upper electrode 10 are connected to form a single electrode. When the cross-sectional area is reduced in this way, the wiring resistance from the lower electrode 9 and the upper electrode 10 to the gate electrode increases. Therefore, it is likely that holes will flow in the direction of the second trench 12. <Fünfte Modifikation>

[0028] Fig. Figure 4 is a cross-sectional view of a semiconductor device according to a fifth modification. As in Fig. As illustrated in Figure 4, the lower electrode 9 is connected to the gate potential, and the upper electrode 10 is connected to the emitter electrode 16.

[0029] Since only the lower electrode 9 is connected to the gate potential, the cross-sectional area of ​​the electrode connected to the gate potential decreases, and the wiring resistance to the gate electrode increases compared to the semiconductor device according to the fourth modification. Therefore, it is likely that holes will flow to the second trench 12 as in the semiconductor device according to the fourth modification.

[0030] It should be noted that a conventional structure and structures described in the first preferred embodiment and the first to fifth modifications can be combined into a single element, or a variety of structures from those described in the first preferred embodiment and the first to fifth modifications can be combined into a single element. This can further prevent the occurrence of faulty switching on. <Sechste Modifikation>

[0031] Fig. Figure 5 is a cross-sectional view of a semiconductor device according to a sixth modification. As in Fig. Figure 5 illustrates that the lower electrode 9 is connected to the emitter electrode 16, and the upper electrode 10 is connected to the gate potential.

[0032] Since the lower electrode 9 is not connected to the gate potential, an increase in the potential of the upper electrode 10 can be prevented even if holes have accumulated in the lower electrode 9. Therefore, it is possible to prevent the faulty switching on of the semiconductor device. <Siebte Modifikation>

[0033] Fig. Figure 6 is a cross-sectional view of a semiconductor device according to a seventh modification. As in Fig. As illustrated in Figure 6, the second trench 12 has a lower dummy electrode 18, which is provided on the side of the second main surface, and an upper dummy electrode 19, which is provided on the side of the first main surface with respect to the lower dummy electrode 18. The lower dummy electrode 18 and the upper dummy electrode 19 are electrically connected to the emitter electrode 16. The width of the upper dummy electrode 19 is greater than the width of the lower dummy electrode 18.

[0034] Although one case serves as an example in Fig. 6 is described in which a configuration of the first trench 8 is the same as that in Fig. 5, the configuration of the first trench 8 can be the same as that in Fig. 3 or Fig. 4.

[0035] Since the width of the upper dummy electrode 19 is greater than the width of the lower dummy electrode 18, the combined cross-sectional area of ​​the lower dummy electrode 18 and the upper dummy electrode 19 is increased, making it likely that holes will flow towards the second trench 12. Furthermore, since the thickness of part of the dummy insulating layer 14, which is provided on the side wall of the second trench 12 and covers the upper dummy electrode 19, is thin, the parasitic capacitance between the emitter and the collector increases, and the impedance of the parasitic capacitance between the emitter and the collector can be reduced. Consequently, it is likely that holes will flow towards the side of the second trench 12, and the increase in the potential of the upper electrode 10 can be prevented. <Achte Modifikation>

[0036] In a semiconductor device according to an eighth modification, the second trench 12 is arranged on at least one of the left and right sides of the first trench 8 with a distance between them.

[0037] Although the second trench 12 is on the right side of the first trench 8 in the example of Fig. The present disclosure is not limited to the arrangement described in Figure 1. The second trench 12 may be arranged on the left side of the first trench 8, or it may be arranged on the right and left sides of the first trench 8 respectively. Furthermore, the first trench 8 and the second trench 12 may be arranged alternately; the first trench 8, the first trench 8, and the second trench 12 may be arranged in this order from the left; or the second trench 12, the first trench 8, the first trench 8, and the second trench 12 may be arranged in this order from the left. In this way, the first trench 8 and the second trench 12 may be arranged in any manner required.

[0038] Since the second trench 12 is arranged on at least one of the left and right sides of the first trench 8 with a distance between them, it is likely that holes flow in the direction of the second trench 12. <Neunte Modifikation>

[0039] Fig. Figure 7 is a cross-sectional view of a semiconductor device according to a ninth modification. Fig. Figure 7 focuses primarily on the first trench 8, while the second trench 12, the intermediate insulating layer 15, the emitter electrode 16, and the collector electrode 17 are not illustrated. As in Fig. Figure 7 illustrates that an interface between the charge carrier accumulation layer 2 and the P base layer 3 is curved in the direction of the second main surface.

[0040] Although one case serves as an example in Fig. 7 is described in which a configuration of the first trench 8 is the same as that in Fig. 5, the configuration of the first trench 8 can be the same as that in Fig. 3 or Fig. 4. The second trench 12 can be, as in Fig. Figure 1 illustrates, in addition to having the dummy electrode 13, and it can, as in Fig. Figure 6 illustrates the lower dummy electrode 18 and the upper dummy electrode 19.

[0041] Since the interface between the charge carrier accumulation layer 2 and the P base layer 3 is curved in the direction of the second main surface, holes can be prevented from flowing into the upper electrode 10. <Zehnte Modifikation>

[0042] In a semiconductor device according to a tenth modification, the materials of the lower electrode 9, the upper electrode 10, and the dummy electrode 13 are a metal. This metal is, for example, aluminum, tungsten, or the like.

[0043] Since the materials of the lower electrode 9, the upper electrode 10, and the dummy electrode 13 are a metal, the resistance of each electrode can be reduced.

[0044] If the second trench 12 connects the lower electrode 18 and the upper electrode 19, as in Fig. Figure 6 illustrates that the materials of the lower dummy electrode 18 and the upper dummy electrode 19 can be a metal. <Elfte Modifikation>

[0045] Fig. Figure 8 is a cross-sectional view of a semiconductor device according to an eleventh modification. As in Fig. As illustrated in Figure 8, a surface of the dummy insulating layer 14 on the side of the first main surface has a recessed shape. Specifically, a surface of the dummy insulating layer 14 that is in contact with the intermediate insulating layer 15 has a recessed shape.

[0046] Since the area of ​​the dummy insulating layer 14 on the side of the first main surface is formed in the recessed shape, the area of ​​the dummy electrode 13 that is in contact with the emitter electrode 16 increases, and the resistance of the dummy electrode 13 can be reduced.

[0047] It should be noted that a configuration of the first trench 8 may be the same as in one of the Fig. 3, Fig. 4, and Fig. 5. The second trench 12 can be like in Fig. 1 illustrated dummy electrode 13, and can have the lower dummy electrode 18 and the upper dummy electrode 19 as in Fig. 6 illustrates this. <Zwölfte Modifikation>

[0048] Fig. Figure 9 is a cross-sectional view of a semiconductor device according to a twelfth modification. As in Fig. As illustrated in Figure 9, a surface of the lower electrode 9, which faces the upper electrode 10 (the surface on the side of the first main surface), has a protruding shape. A surface of the upper electrode 10, which faces the lower electrode 9 (the surface on the side of the second main surface), has a recessed shape. That is, the protruding shape of the lower electrode 9 and the recessed shape of the upper electrode 10 face each other.

[0049] Since the surface of the lower electrode 9, which faces the upper electrode 10 (the surface on the side of the first main surface), is formed in the protruding form and the surface of the upper electrode 10, which faces the lower electrode 9 (the surface on the side of the second main surface), is formed in the recessed form, the resistance of the entry of holes into the upper electrode 10 increases, and the increase with respect to the potential of the upper electrode 10 can be prevented.

[0050] It should be noted that a configuration of the first trench 8 can be the same as any from the Fig. 3, Fig. 4, and Fig. 5, as long as forms of the lower electrode 9 and the upper electrode 10 that are in Fig. The nine illustrated forms are shown. The second trench, 12, can be found in Fig. 1 illustrated dummy electrode 13, and he can have the lower dummy electrode 18 and the upper dummy electrode 19 as in Fig. 6 illustrates this. <Dreizehnte Modifikation>

[0051] Fig. Figure 10 is a top view of a semiconductor device according to a thirteenth modification. Fig. Figure 10 does not illustrate the N+ emitter 4, the P+ contact 5, or the emitter electrode 16.

[0052] As in Fig. As illustrated in Figure 10, in the semiconductor device according to the thirteenth modification, contact holes 20, which are openings in the interlayer insulating layer 15, are provided at equal intervals along one direction of extension of the second trench 12 in a top view. The dummy electrode 13 is connected to the emitter electrode 16 through the contact holes 20.

[0053] In a case where the intermediate insulating layer 15 is not provided on the second trench 12 (see for example Fig. 2) A hole discharge effect is high, a conductivity modulation effect in the semiconductor device at the time of conduction is reduced, and an on-voltage (Vce(sat)) increases. As in the semiconductor device according to the thirteenth modification, if the contact holes 20 are provided at equal intervals (that is, the intermediate insulating layer 15 is provided on a portion of the second trench 12) along the extension direction of the second trench 12 in a top view, the increase with respect to the on-voltage can be suppressed. <Vierzehnte Modifikation>

[0054] In a semiconductor device according to a fourteenth modification, contact holes, which are openings in the interlayer insulating layer 15, are provided at both ends of the second trench 12 along the direction of extension of the second trench 12 in a top view. The dummy electrode 13 is connected to the emitter electrode 16 through the contact holes.

[0055] The same effects as those of the thirteenth modification can also be achieved in the configuration of the semiconductor device according to the fourteenth modification.

[0056] It should be noted that the preferred embodiment may be appropriately modified or omitted within the scope of protection of the present disclosure. <appendizes>

[0057] The following sections describe different aspects of the Revelation together as appendices. (Appendix 1)

[0058] comprising a semiconductor device: a semiconductor substrate comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of the first conductivity type selectively provided in an upper part of the third semiconductor layer; a first main electrode which is provided on one side of a first main surface of the semiconductor substrate, so that it is in contact with the fourth semiconductor layer; a second main electrode, which is provided on one side of a second main surface, which faces the first main surface of the semiconductor substrate; a first trench which is provided in the semiconductor substrate, so that it penetrates the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer and reaches the first semiconductor layer; an intermediate insulating layer, which is provided in such a way that it covers the first trench; and a second trench which is provided in the semiconductor substrate, so that it penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer, wherein the first trench has a lower electrode, which is provided on the side of the second main surface, and an upper electrode, which is provided on the first main surface in relation to the lower electrode, the second trench has a dummy electrode which is electrically connected to the first main electrode, and a maximum width of the dummy electrode is equal to or greater than a maximum width of the lower electrode. (Appendix 2)

[0059] Semiconductor device according to Appendix 1, wherein the dummy electrode has a side surface which is formed in a straight shape along a side wall of the second trench. (Appendix 3)

[0060] Semiconductor device according to Appendix 1 or 2, wherein the maximum width of the dummy electrode is 1.1 times the maximum width or more of the lower electrode. (Appendix 4)

[0061] Semiconductor device according to one of Appendices 1 to 3, wherein the first trench and the second trench each have a tapered shape, tapering from the first main surface towards the second main surface. (Appendix 5)

[0062] Semiconductor device according to one of Appendices 1 to 4, wherein the first trench has a lower insulating layer which is provided on a side wall and a floor of the first trench to cover the lower electrode, the second trench has a dummy insulating layer provided on a side wall and floor of the second trench to cover the dummy electrode, and The thickness of the lower insulating layer provided on the bottom of the first trench and the thickness of the dummy insulating layer provided on the bottom of the second trench are thinner than the thickness of the dummy insulating layer provided on the side wall of the second trench. (Appendix 6)

[0063] Semiconductor device according to one of the appendices 1 to 5, wherein the dummy electrode is covered by the first main electrode. (Appendix 7)

[0064] Semiconductor device according to one of Appendices 1 to 4 and 6, wherein the first trench has a lower insulating layer which is provided on a side wall and a floor of the first trench to cover the lower electrode, the second trench has a dummy insulating layer provided on a side wall and floor of the second trench to cover the dummy electrode, and The thickness of the dummy insulating layer is thinner than the thickness of the lower insulating layer. (Appendix 8)

[0065] Semiconductor device according to one of Appendices 1 to 7, wherein the lower electrode and the upper electrode are connected to a gate potential. (Appendix 9)

[0066] Semiconductor device according to one of the appendices 1 to 7, wherein the upper electrode is electrically connected to the first main electrode. (Appendix 10)

[0067] Semiconductor device according to one of the appendices 1 to 7, wherein the lower electrode is electrically connected to the first main electrode. (Appendix 11)

[0068] Semiconductor device according to one of Appendices 1 to 10, wherein the dummy electrode has a lower dummy electrode, which is provided on the side of the second main surface, and an upper dummy electrode, which is provided on the side of the first main surface in relation to the lower dummy electrode. the lower dummy electrode and the upper dummy electrode are electrically connected to the first main electrode, and The width of the upper dummy electrode is greater than the width of the lower dummy electrode. (Appendix 12)

[0069] Semiconductor device according to one of Appendices 1 to 11, wherein the second trench is arranged on at least one of the left and right sides of the first trench with a distance between the first trench and the second trench. (Appendix 13)

[0070] Semiconductor device according to any of Appendices 1 to 12, wherein an interface between the second semiconductor layer and the third semiconductor layer is curved in the direction of the second principal surface. (Appendix 14)

[0071] Semiconductor device according to any of Appendices 1 to 13, wherein the materials of the lower electrode, the upper electrode, and the dummy electrode are a metal. (Appendix 15)

[0072] Semiconductor device according to any one of Appendices 1 to 14, wherein the second trench has a dummy insulating layer provided on a side wall and floor of the second trench to cover the dummy electrode, and one area of ​​the dummy insulating layer on the side of the first main surface has a recessed shape. (Appendix 16)

[0073] Semiconductor device according to any one of Appendices 1 to 15, wherein a surface of the lower electrode, which faces the upper electrode, has a prominent shape, and A surface of the upper electrode, which faces the lower electrode, has a recessed shape. (Appendix 17)

[0074] Semiconductor device according to any one of Appendices 1 to 16, wherein the intermediate insulating layer is provided in such a way that it covers the second trench, contact holes, which are openings in the intermediate insulating layer, are provided at equal intervals along an extension direction of the second trench in a top view, and The dummy electrode is connected to the first main electrode through the contact holes. (Appendix 18)

[0075] Semiconductor device according to any one of Appendices 1 to 16, wherein the intermediate insulating layer is provided in such a way that it covers the second trench, Contact holes, which are openings in the intermediate insulating layer, are provided at both ends of the second trench along one extension direction of the second trench in a top view, and The dummy electrode is connected to the first main electrode through the contact holes.

[0076] While the revelation has been shown and described in detail, the preceding description is illustrative in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be conceived. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2014-60362

[0002] JP 2019-12813

[0002] JP 2017-147431

[0002] JP 2021-72418

[0002] < / appendizes>

Claims

[1] comprising a semiconductor device: • a semiconductor substrate comprising a first semiconductor layer (1) of a first conductivity type, a second semiconductor layer (2) of the first conductivity type provided on the first semiconductor layer (1), a third semiconductor layer (3) of a second conductivity type provided on the second semiconductor layer (2), and a fourth semiconductor layer (4) of the first conductivity type, which is selectively provided in an upper part of the third semiconductor layer (3); • a first main electrode (16) which is provided on one side of a first main surface of the semiconductor substrate, so that it is in contact with the fourth semiconductor layer (4); • a second main electrode (17) which is provided on one side of a second main surface which faces the first main surface of the semiconductor substrate; • a first trench (8) provided in the semiconductor substrate, such that it penetrates the fourth semiconductor layer (4), the third semiconductor layer (3), and the second semiconductor layer (2) and reaches the first semiconductor layer (1); • an intermediate insulating layer (15) provided in such a way that it covers the first trench (8); and • a second trench (12) which is provided in the semiconductor substrate in such a way that it penetrates the third semiconductor layer (3) and the second semiconductor layer (2) and reaches the first semiconductor layer (1), wherein • the first trench (8) has a lower electrode (9) which is provided on the side of the second main surface and an upper electrode (10) which is provided on the side of the first main surface in relation to the lower electrode (9), • the second trench (12) has a dummy electrode (13) which is electrically connected to the first main electrode (16), and • a maximum width of the dummy electrode (13) is equal to or greater than a maximum width of the lower electrode (9). [2] Semiconductor device according to claim 1, wherein the dummy electrode (13) has a side surface which is formed in a straight shape along a side wall of the second trench (12). [3] Semiconductor device according to claim 1 or 2, wherein the maximum width of the dummy electrode (13) is 1.1 times or more the maximum width of the lower electrode (9). [4] Semiconductor device according to one of claims 1 to 3, wherein the first trench (8) and the second trench (12) each have a tapered shape which tapers from the first main surface towards the second main surface. [5] Semiconductor device according to any one of claims 1 to 4, wherein • the first trench (8) has a lower insulating layer which is provided on a side wall and a bottom of the first trench (8) to cover the lower electrode (9), • the second trench (12) has a dummy insulating layer (14) which is provided on a side wall and a bottom of the second trench (12) to cover the dummy electrode (13), and • the thickness of the lower insulating layer provided on the bottom of the first trench (8) and the thickness of the dummy insulating layer (14) provided on the bottom of the second trench (12) are thinner than the thickness of the dummy insulating layer (14) provided on the side wall of the second trench (12). [6] Semiconductor device according to any one of claims 1 to 5, wherein the dummy electrode (13) is covered by the first main electrode (16). [7] Semiconductor device according to one of claims 1 to 4 or 6, wherein • the first trench (8) has a lower insulating layer which is provided on a side wall and a bottom of the first trench (8) to cover the lower electrode (9), • the second trench (12) has a dummy insulating layer (14) which is provided on a side wall and a bottom of the second trench (12) to cover the dummy electrode (13), and • the thickness of the dummy insulating layer (14) is thinner than the thickness of the lower insulating layer. [8] Semiconductor device according to any one of claims 1 to 7, wherein the lower electrode (9) and the upper electrode (10) are connected to a gate potential. [9] Semiconductor device according to any one of claims 1 to 7, wherein the upper electrode (10) is electrically connected to the first main electrode (16). [10] Semiconductor device according to any one of claims 1 to 7, wherein the lower electrode (9) is electrically connected to the first main electrode (16). [11] Semiconductor device according to any one of claims 1 to 10, wherein • the dummy electrode (13) has a lower dummy electrode (18) which is provided on the side of the second main surface and an upper dummy electrode (19) which is provided on the side of the first main surface with respect to the lower dummy electrode (18), • the lower dummy electrode (18) and the upper dummy electrode (19) are electrically connected to the first main electrode (16), and • the width of the upper dummy electrode (19) is greater than the width of the lower dummy electrode (18). [12] Semiconductor device according to any one of claims 1 to 11, wherein the second trench (12) is arranged at least on one of the left and right sides of the first trench (8) with a distance between the first trench (8) and the second trench (12). [13] Semiconductor device according to one of claims 1 to 12, wherein an interface between the second semiconductor layer (2) and the third semiconductor layer (3) is curved in the direction of the second main surface. [14] Semiconductor device according to any one of claims 1 to 13, wherein the materials of the lower electrode (9), the upper electrode (10) and the dummy electrode (13) are a metal. [15] Semiconductor device according to any one of claims 1 to 14, wherein • the second trench (12) has a dummy insulating layer (14) which is provided on a side wall and a bottom of the second trench (12) to cover the dummy electrode (13), and • one area of ​​the dummy insulating layer (14) on the side of the first main surface has a recessed shape. [16] Semiconductor device according to any one of claims 1 to 15, wherein • a surface of the lower electrode (9), which faces the upper electrode (10), has a prominent shape, and • a surface of the upper electrode (10), which faces the lower electrode (9), has a recessed shape. [17] Semiconductor device according to any one of claims 1 to 16, wherein • the intermediate insulating layer (15) is provided to cover the second trench (12), • Contact holes (20), which are openings in the intermediate insulating layer (15), are provided at equal intervals along an extension direction of the second trench (12) in a top view, and • the dummy electrode (13) is connected to the first main electrode (16) through the contact holes (20). [18] Semiconductor device according to any one of claims 1 to 16, wherein • the intermediate insulating layer (15) is provided to cover the second trench (12), • Contact holes (20), which are openings in the intermediate insulating layer (15), are provided at both ends of the second trench (12) along a direction of extension of the second trench (12) in a top view, and • the dummy electrode (13) is connected to the first main electrode (16) through the contact holes (20).

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