Power semiconductor module with external contact surfaces, and methods for its manufacture

Abstract

A power semiconductor module is presented, comprising a substrate with a substrate carrier, a plurality of conductor tracks arranged thereon, and a power semiconductor device arranged on one of these conductor tracks and internally connected in accordance with the circuit, with an electrically conductive, planar intermediate element, the first surface of which facing the substrate is electrically connected to a contact surface of the substrate, with a contact element for external connection of the substrate, wherein the contact element is arranged completely within the substrate and its first surface facing the substrate is electrically connected to the second surface opposite the first of the intermediate element, wherein the contact element laterally overlaps the associated intermediate element on one side, with a potting compound.which covers the substrate and leaves a section of the second surface of the contact element free, opposite the first. A corresponding manufacturing process for this power semiconductor module is also presented.

Description

[0001] The invention describes a power semiconductor module comprising a substrate, a substrate carrier, a plurality of conductive traces arranged thereon, and a power semiconductor device arranged on one of these conductive traces and internally connected in a circuit-compliant manner, with an electrically conductive, planar contact element as the external load connection of the power semiconductor module. The invention further describes a manufacturing method for such a power semiconductor module.

[0002] DE 10 2005 061 772 A1 discloses a power semiconductor module with at least one carrier plate having, on a first side, a first metal layer facing outwards and forming part of the outside of the power semiconductor module, and on a second side, a second metal layer facing inwards to which at least one power semiconductor device is attached, and with a plastic body made of a thermosetting plastic that encloses the carrier plate except for the first metal layer or at least part thereof. The aim is to ensure satisfactory cooling of the semiconductor devices and a sufficient service life. For this purpose, the plastic is designed to have a coefficient of thermal expansion that corresponds to that of the carrier plate.

[0003] DE 10 2009 035 920 A1 discloses a semiconductor device comprising: a support with a vertical column, wherein the support includes a leadframe and the vertical column includes a drain electrode integrally formed with the leadframe; a chip coupled to the support, wherein the chip includes a first surface with a first contact spaced apart from a second contact, wherein the upper surface of the vertical column is essentially coplanar with the first and the second contact;a dielectric layer arranged above the substrate and the chip, comprising a photoinitiator designed for the selective opening of the dielectric layer, wherein the dielectric layer is formed as a monolithic film covering the substrate and the chip, and wherein the dielectric layer is structured to project beyond an upper surface of the vertical column and to have openings above the first and second contacts and above the vertical column; and a first conductive element connected to the first contact, a second conductive element connected to the second contact, and a third conductive element connected to the vertical column of the substrate.

[0004] US Patent 2012 / 0211767A1 discloses a power converter comprising a power converter main unit and a wiring substrate, wherein the power converter main unit comprises multiple power conversion semiconductor devices with electrodes, an electrode connecting conductor configured to electrically connect the electrodes of the multiple power conversion semiconductor devices, the multiple electrodes having the same potential and also having a generally flat top surface for electrical connection to an outer section in a higher position than the multiple power conversion semiconductor devices, and a sealing material of a resin covering the power conversion semiconductor devices; wherein the generally flat top surface of the electrode connecting conductor is configured to be exposed above the top surface of the sealing material;and wherein a wiring substrate is electrically connected to the generally flat top surface of the electrode connection conductor, which is exposed from the top surface of the sealing material.

[0005] With knowledge of the prior art, the invention is based on the objective of providing an encapsulated power semiconductor module and a method for its manufacture which allows a compact design, in particular with a small footprint.

[0006] This problem is solved according to the invention by a power semiconductor module, preferably without a frame-like or other housing, in particular a plastic housing, with a substrate comprising a substrate carrier, a plurality of conductor tracks arranged thereon, and a power semiconductor device arranged on one of these conductor tracks and internally connected in a circuit-compliant manner, with an electrically conductive, planar intermediate element, with a first surface, wherein this first surface facing the substrate is electrically conductively connected to a contact surface of a conductor track or a load connection surface of the power semiconductor device, with a contact element for external connection of the substrate, wherein the contact element is arranged completely within the substrate and has a first surface.wherein this first surface facing the substrate is electrically connected to a second surface opposite the first of the intermediate element, wherein the contact element laterally overlaps the associated intermediate element on one side, with a potting compound, in particular made of a thermosetting plastic, also referred to as transfermold compound, which covers the substrate and leaves a section of the second surface opposite the first of the contact element exposed.

[0007] The phrase "that the contact element is completely within the substrate" means that the arrangement area of ​​the contact element is limited to the area of ​​the substrate, and that the contact element is therefore not arranged to project laterally beyond the substrate surface when viewed in the direction of view.

[0008] It can be advantageous if the substrate's contact surface is configured as a load connection surface for the power semiconductor device. Likewise, it can be advantageous if the substrate's contact surface is configured as a section of a conductor track.

[0009] It may be preferable if the area of ​​the second surface of the intermediate element is smaller than the area of ​​the first surface of the contact element.

[0010] It can be advantageous if the thickness of the intermediate element is greater than the thickness of the contact element. In particular, the thicknesses of multiple intermediate elements can vary.

[0011] It may still be preferred if a contact element is electrically connected to a plurality of intermediate elements.

[0012] The problem is further solved by a method for manufacturing a power semiconductor module according to one of the preceding claims comprising the following steps: a) Providing a substrate carrier with a plurality of conductor tracks arranged on it; b) Arranging and metallurgically bonding a power semiconductor device on a conductor track; c) Arranging and materially bonding an intermediate element on a conductor track or on a load connection surface of the power semiconductor device; d) Arranging and materially bonding the contact element on the intermediate element, wherein the contact element laterally overlaps the associated intermediate element on one side; e) Encapsulating the substrate in such a way that a section of the second surface of the contact element remains free and thus accessible from the outside.

[0013] It can be advantageous if steps b) and c) are carried out simultaneously and the intermediate element is placed on a conductor track.

[0014] It may be preferred if, in step c), the material-bonded connection of the intermediate element with the conductor track is carried out as an adhesive, soldered, welded or sintered connection.

[0015] It may also be preferred if, in step c), the material-bonded connection of the intermediate element with a load connection surface of the power semiconductor device is carried out as an adhesive, solder or sintered connection.

[0016] It may be advantageous if, in step d), the material-bonded connection of the contact element with the intermediate element is carried out as an adhesive, soldered, welded or sintered connection.

[0017] In principle, it can be advantageous if, prior to process step d), an internal module connection device is arranged or formed to create the circuit-compliant connection of the power semiconductor component.

[0018] Of course, unless explicitly or per se excluded or contrary to the idea of ​​the invention, the features mentioned in the singular, such as the intermediate element and the contact element, can also be present multiple times in the power semiconductor device according to the invention or implemented in the manufacturing process.

[0019] It is understood that the various embodiments of the invention can be implemented individually or in any combination, regardless of whether they are within the scope of the power semiconductor module or the manufacturing process, in order to achieve improvements. In particular, the features mentioned and explained above and below can be used not only in the combinations specified, but also in other combinations or individually, without departing from the scope of the present invention.

[0020] Further explanations of the invention, advantageous details and features will become apparent from the following description of the invention contained in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9 to Fig. 10 schematically illustrated embodiments of the invention or of respective parts thereof. Fig. 1, Fig. 3 and Fig. Figure 5 shows different stages of the inventive method for producing a first embodiment of a power semiconductor module according to the invention in a top view. Fig. 2, Fig. 4 and Fig. Figure 6 shows the different stages in a side view. Fig. 7 and Fig. Figure 8 shows a second embodiment of a power semiconductor module according to the invention as an alternative to the Fig. 5 and Fig. 6. Fig. 9 and Fig. Figure 10 shows a third embodiment of a power semiconductor module according to the invention as an alternative to Fig. 3.

[0021] Fig. 1, Fig. 3 and Fig. Figure 5 shows various stages of the inventive method for producing a first embodiment of a power semiconductor module 1 according to the invention in a top view. Fig. 2, Fig. 4 and Fig. Figure 6 shows the respective different stages in a side view. In the Fig. 1 and Fig. Figure 2 shows a power semiconductor module 1 according to process step c). At this point, it has a substrate 2 with a substrate support 20, purely by way of example designed as a conventional ceramic substrate support. A plurality of conductor tracks 22, 24, here designed as copper conductor tracks, are arranged on this substrate support 20.

[0022] On two of these conductor tracks 24, a plurality of power semiconductor devices 26 are arranged, each forming a switch of a power electronic circuit arrangement, here a half-bridge arrangement. On the side of the power semiconductor device 26 facing away from the substrate carrier 20, it has a contact surface 260 which, in this embodiment, is not connected to an intermediate element.

[0023] Here, by way of example, contact surfaces 220 are formed on three conductor tracks 22, 24, which are intended to be electrically connected to an intermediate element by means of a material-bonded connection using a standard design. The intermediate elements 3 arranged on these contact surfaces are themselves designed as planar metal bodies, for example made of copper, and in this configuration have a thickness that corresponds to 2 to 5 times the thickness of a power semiconductor device 26.

[0024] Fig. 3 and Fig. Figure 4 shows the power semiconductor module 1 after process step d). Here, an associated contact element 4 is arranged on each of the intermediate elements 3 and electrically connected to it by means of a standard design. The respective contact element 4 is located completely within the substrate 2. The contact element 4 therefore does not project laterally beyond the edge regions of the substrate 2, shown here as a dashed line. A first surface 400 of the contact element 4 facing the substrate 2 is partially electrically connected, namely in the overlap area with the intermediate element 3, to the second surface 320 of the intermediate element 3 opposite the first.

[0025] In this embodiment, these contact elements 4 have a thickness that is 30% to 60% greater than the thickness of the associated intermediate element. Independently of this, it is particularly preferred if the thickness of the contact element 4 is several times, in particular three to five times, the thickness of the conductor track 22, 24. Crucially, each contact element 4 overlaps the associated intermediate element 3 laterally on at least one side, i.e., parallel to the substrate carrier 20, in the direction of view of it.

[0026] Fig. 5 and Fig. Figure 6 shows the power semiconductor module 1 after process step e). In this process step, the substrate 2 was encapsulated using a transfer molding process. In this configuration, the contact elements 4 partially protrude from the surface of the encapsulating compound 5, which is parallel to the substrate carrier 20. Thus, the entire second surface 420 of the contact elements 4 is accessible from the outside and can be connected to external terminals. Here too, the contact elements 4 are completely within the substrate 2, as indicated by the dashed line, and are located above the conductor tracks. This connection can be implemented, in particular, as is customary in the field, by adhesive bonding, soldering, welding, or sintering.

[0027] Fig. 7 and Fig. Figure 8 shows a second embodiment of a power semiconductor module 1 according to the invention as an alternative to the Fig. 5 and Fig. 6, wherein the surface of the potting compound parallel to the substrate carrier 20 extends above the respective second surface 420 of the contact elements 4 in height, however, a respective section 422 of this second surface 420 remains free for an external connection and is thus accessible.

[0028] An advantage of both of the aforementioned embodiments of the power semiconductor modules 1 is, on the one hand, that the externally accessible section 422, regardless of whether it corresponds to the entire second surface 420 or only a part thereof, has an area that is larger than the associated area of ​​the contact surface 220,260 of the substrate 2. On the other hand, it is advantageous that the significantly greater thickness of the contact element 4, compared to the conductor track with its contact surface 220 or to the power semiconductor component with its contact surface 260, makes the contact element 4 more robust against mechanical stresses during the connection process of an external connection element.

[0029] Fig. 9 and Fig. Figure 10 shows a third embodiment of a power semiconductor module 1 according to the invention as an alternative to the embodiment according to Fig. 3. Fig. Figure 9 shows a partial magnification of substrate 2 analogous to Fig. 1, however with only one arranged intermediate element 3. Fig. Figure 10 shows a contact element 4 within the substrate 2, which is connected to two intermediate elements 3.

Claims

[1] Power semiconductor module (1) with a substrate (2), comprising a substrate carrier (20), a plurality of conductor tracks (22, 24) arranged thereon, and a power semiconductor device (26) arranged on one of these conductor tracks (22, 24) and internally connected in a circuit-oriented manner, with an electrically conductive planar intermediate element (3), with a first surface (300), wherein this first surface (300) facing the substrate (2) is electrically conductively connected to a contact surface (220, 260) of a conductor track (22, 24) or a load connection surface of the power semiconductor device (26), with a contact element (4) for external connection of the substrate (2), wherein the contact element (4) is arranged completely within the substrate (2) and has a first surface (400),wherein this first surface (400) facing the substrate (2) is electrically connected to a second surface (320) opposite the first of the intermediate element (3), wherein the contact element (4) overlaps the associated intermediate element (3) laterally on one side, with a potting compound (5) that covers the substrate (2) and leaves a section (422) of the second surface (420) opposite the first of the contact element (4) exposed. [2] Power semiconductor module according to claim 1, wherein the contact surface (260) of the substrate (2) is designed as a load connection surface of the power semiconductor device (26). [3] Power semiconductor module according to claim 1 or 2, wherein the contact surface (220) of the substrate (2) is formed as a section of a conductor track (22). [4] Power semiconductor module according to one of the preceding claims, wherein the area of ​​the second surface (320) of the intermediate element (3) is smaller than the area of ​​the first surface (400) of the contact element (4). [5] Power semiconductor module according to one of the preceding claims, wherein the thickness of the intermediate element (3) is greater than the thickness of the contact element (4). [6] Power semiconductor module according to one of the preceding claims, wherein a contact element (4) is electrically connected to a plurality of intermediate elements (3). [7] Method for manufacturing a power semiconductor module (1) according to any one of the preceding claims comprising the following steps: a) Providing a substrate carrier (20) with a plurality of conductor tracks (22,24) arranged thereon; b) Arranging and metallurgically connecting a power semiconductor device (26) on a conductor track (24); c) Arranging and materially bonding an intermediate element (3) on a conductor track (22,24) or on a load connection surface of the power semiconductor device (26); d) Arranging and joining the contact element (4) on the intermediate element (3) in a material-bonded manner, wherein the contact element (4) laterally overlaps the associated intermediate element (3) on one side; e) Encapsulating the substrate (2) such that a section (422) of the second surface (420) of the contact element (4) remains free and thus accessible from the outside. [8] Method according to claim 7, wherein steps b) and c) are carried out simultaneously and the intermediate element (3) is arranged on a conductor track (22). [9] Method according to claim 7 or 8, wherein in step c) the material-bonded connection of the intermediate element (3) with the conductor track (22,24) is carried out as an adhesive, soldering, welding or sintering connection. [10] Method according to claim 7 or 8, wherein in step c) the material-bonded connection of the intermediate element (3) with a load connection surface of the power semiconductor device (26) is carried out as an adhesive, solder or sintered connection. [11] Method according to any one of claims 7 to 10, wherein in step d) the materially bonded connection of the contact element (4) with the intermediate element (3) is carried out as an adhesive, soldering, welding or sintering connection. [12] Method according to one of claims 7 to 11, wherein prior to method step d) a module-internal connection device is arranged or formed to form the circuit-compliant connection of the power semiconductor device (26).

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