Glass cores including protruding glass vias and related processes

Abstract

Glass cores incorporating protruding glass vias and associated methods are disclosed herein. An exemplary substrate disclosed herein comprises a glass core including a surface and a copper-to-glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.

Description

BACKGROUND

[0001] Integrated circuit (IC) chips and / or semiconductor dies are routinely connected to larger printed circuit boards, such as motherboards and other types of printed circuit boards (PCBs), via a package substrate. As IC chips and / or dies decrease in size and interconnect densities increase, alternatives to conventional substrate layers are being developed to provide stable transmission of high-frequency data signals between different circuit configurations and / or increased power delivery. One option being pursued is the implementation of package substrates with glass cores. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional side view of an exemplary integrated circuit (IC) package constructed according to the teachings disclosed herein. Fig. Figure 2 illustrates a previous substrate core where a Seware error occurred. Fig. Figure 3 is a cross-sectional side view of an exemplary first housing substrate, which, in conjunction with the integrated circuit package made of Fig. 1 can be used. Fig. 4A, Fig. 4B, Fig. 4C and Fig. 4D illustrates different intermediate stages in an exemplary manufacturing process for producing the substrate core. Fig. 3. Fig. Figure 5 is a flowchart representing an exemplary procedure that can be carried out to extract the first substrate nucleus from Fig. 3 via the intermediate stages Fig. To manufacture 4A-4D. Fig. Figure 6 is a cross-sectional side view of an exemplary second housing substrate, which is used in conjunction with the integrated circuit housing made of Fig. 1 can be used. Fig. 7A, Fig. 7B, Fig. 7C and Fig. 7D illustrates different intermediate stages in an exemplary manufacturing process for producing the substrate core. Fig. 6. Fig. Figure 8 is a flowchart representing an exemplary procedure that can be carried out to extract the second substrate core from Fig. 6 about the intermediate stages from Fig. 7A-7D to manufacture. Fig. Figure 9 is a top view of a wafer containing dies that may be contained in an IC package constructed according to the teachings disclosed herein. Fig. Figure 10 is a cross-sectional side view of an IC device that may be contained in an IC package constructed according to the teachings disclosed herein. Fig. Figure 11 is a cross-sectional side view of an IC device assembly which may include an IC package constructed according to teachings disclosed herein. Fig. Figure 12 is a block diagram of an exemplary electrical device which may include an IC package constructed according to the teachings disclosed herein.

[0002] Generally, the same reference numbers are used in the drawing(s) and the accompanying written description to refer to the same or similar parts. The figures are not necessarily to scale. Instead, the thickness of the layers or areas in the drawings may be enlarged. Although the figures show layers and areas with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, blended, and / or irregular. DETAILED DESCRIPTION

[0003] Fig. Figure 1 illustrates an exemplary integrated circuit package 100 constructed according to the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to an underlying substrate 102 via an array of contacts 104 on a mounting surface 106 (e.g., a bottom surface, an external surface) of the package. In some examples, the substrate 102 may be implemented by a package substrate or a printed circuit board (PCB). In the illustrated example, the contacts 104 are represented as spheres. However, in some examples, the IC package 100 may include pads, contact spots, and / or any other type of contact in addition to or instead of the pads or contact spots shown to enable the electrical coupling of the IC package 100 to the substrate 102. In this example, the IC package 100 contains two dies 108, 110 (e.g.Silicon dies, semiconductor dies, etc.), sometimes also referred to as chips or chiplets, are mounted on a package substrate 112 and enclosed by a package cover 114 (e.g., a potting compound, an integrated heat spreader (IHS)). Accordingly, the package substrate 112 is an exemplary means of supporting a semiconductor die. Although the exemplary IC package 100 is made of... Fig. In one example, the IC package 100 contains two dies 108 and 110, while in other examples it may contain only one die or more than two dies. In some examples, one of the dies 108 and 110 (or a separate die) is embedded in the package substrate 112. The dies 108 and 110 can provide any suitable type of functionality (e.g., data processing, memory, etc.). In some examples, one or both of the dies 108 and 110 are implemented by a die package containing multiple dies arranged in a stacked formation. For example, the second die 110 may contain a stack of a Dynamic Random Access Memory (DRAM) die arranged on top of a memory controller die to form a memory die stack.

[0004] As shown in the illustrated example, each of the dies 108, 110 is electrically and mechanically coupled to the housing substrate 112 via corresponding arrays of intermediate connections 116. Fig. In Figure 1, the interconnects are shown as contact bumps. The interconnects 116 can include solder joints, micro-contact bumps, combinations of metallic (e.g., copper) pillars and solder, etc. In other examples, the interconnects 116 can include directly bonded or "hybrid bonded" metallic interconnects. In other examples, however, the interconnects 116 can be any other type of electrical connection in addition to or instead of the contact bumps shown (e.g., balls, pins, pads, wire bonds, etc.). The electrical connections between the dies 108, 110 and the package substrate 112 (e.g., the interconnects 116) are sometimes referred to as first-level interconnects. In contrast, the electrical connections between the IC package 100 and the substrate 102 (e.g., the contacts 104) are sometimes referred to as second-level interconnects.In some examples, one or both of the dies 108, 110 may be stacked on one or more other dies and / or an interposer. In such examples, the dies 108, 110 are coupled to the underlying die and / or interposer by a first set of level 1 connections, and the underlying die and / or interposer may be connected to the housing substrate 112 via a separate set of level 1 connections associated with the underlying die and / or interposer. Thus, as used here, level 1 connections refer to intermediate connections (e.g., spheres, contact bumps, pins, pads, wire bonds, etc.) between a die and a housing substrate or between a die and an underlying die and / or interposer.

[0005] As in Fig. As shown in Figure 1, the first-level interconnects 116 comprise two different types of contact mounds, corresponding to core contact mounds 118 and bridge contact mounds 120. As used here, the core contact mounds 118 are contact mounds on the dies 108, 110 through which electrical signals pass between the dies 108, 110 and components outside the IC package 100. In particular, as shown in the illustrated example, the core contact mounds 118 are physically connected and electrically coupled to contact pads 124 on a mounting surface 126 (e.g., a top surface, a top-side surface, etc.) of the package substrate 112 when the dies 108, 110 are mounted to the package substrate 112. The contact pads 124 on the mounting surface 126 of the housing substrate 112 are electrically connected to the contacts 104 on the housing mounting surface 106 via internal intermediate connections 128 within the housing substrate 112 (e.g.the lower, external surface) of the package substrate 112 (e.g., a surface opposite the die mounting surface 126). As a result, a continuous electrical signal path exists between the core contact mounds 118 of the dies 108, 110 and the contacts 104 mounted on the substrate 102, passing through the contact pads 124 and the intermediate connections 128 provided between them. As shown, the package mounting surface 106 and the die mounting surface 126 define opposite outer surfaces of the package substrate 112. Although both surfaces are outer surfaces of the package substrate, the die mounting surface 126 is sometimes referred to here as an internal or inner surface relative to the IC package 100. In contrast, in this example, the package mounting surface 106 is an outer or external surface of the IC package 100.

[0006] As used here, bridge contact hills 120 are contact hills on dies 108 and 110 through which electrical signals between different dies 108 and 110 pass within the IC package 100. Accordingly, as shown in the illustrated example, the bridge contact hills 120 of the first die 108 are electrically coupled to the bridge contact hills 120 of the second die 110 via an interconnect bridge 130 (e.g., a silicon-based interconnect bridge, an interconnect die, or an embedded interconnect bridge (EMIB)) embedded in the package substrate 112. As shown in Fig. In the representation 1, the core contact hills 118 are typically larger than the bridge contact hills 120. In some examples, the intermediate connecting bridge 130 and the associated bridge contact hills 120 are omitted.

[0007] In some examples, the IC package includes 100 additional passive components, such as surface-mounted resistors, capacitors and / or inductors, which are arranged on the package mounting surface 106 of the package substrate 112 and / or the die mounting surface 126 of the package substrate 112.

[0008] In Fig. 1. The package substrate 112 of the exemplary IC package 100 includes a glass core 132 (e.g., a glass substrate, a glass layer, etc.) between two separate build areas 134, 136 (here also referred to as build layers, etc.). In some examples, the glass core 132 includes at least one of the following: aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide, and / or quartz glass. In some examples, the glass core 132 includes one or more additives, including: Aluminum oxide (Al₂O₃), boron trioxide (B₂O₃), magnesium oxide (MgO), calcium oxide (CaO), stoichiometric silicon dioxide (SiO₂), barium oxide (BaO), tin oxide (SnO₂), a nickel alloy (Na₂O), potassium oxide (K₂O), phosphorus trioxide (P₂O₃), zirconium dioxide (ZrO₂), lithium oxide (Li₂O), titanium (Ti), and / or zinc (Zn). In some examples, the Glass Core 132 contains silicon and oxygen. In some examples, the Glass Core 132 contains silicon, oxygen, and / or one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In some examples, the Glass Core 132 contains at least 23% by weight of silicon and at least 26% by weight of oxygen. In some examples, the Glass Core is a layer of glass containing silicon, oxygen, and aluminum.In some examples, the glass core 132 contains at least 23% by weight silicon, at least 26% by weight oxygen and at least 5% by weight aluminium.

[0009] In some examples, the glass core 132 is an amorphous solid glass layer. In some examples, the glass core 132 is a layer of glass that contains no organic adhesive or organic material. In some examples, the glass core 132 is a solid layer of glass with a rectangular shape in a top view. In some examples, the glass core 132, as a glass substrate, contains at least one glass layer and contains no epoxy or glass fibers (e.g., it does not contain an epoxy-based prepreg layer with glass fabric). In some examples, the glass core 132 is a single piece of glass extending over the full height / thickness of the core. In other examples, the glass core 132 can be silicon, a dielectric material, and / or one or more other materials.

[0010] In some examples, the glass core 132 has a rectangular shape that, in a top view, is substantially congruent (e.g., within 10%) with the layers above and below the core. In some examples, the glass core 132 has a thickness ranging from about 50 micrometers (µm) to about 1.4 millimeters (mm). In some examples, the glass core 132 may be a multilayered glass substrate (e.g., a coreless substrate), with each glass layer having a thickness ranging from about 25 µm to about 50 µm. In some examples, the glass core 132 may have dimensions ranging from about 10 mm on one side to about 250 mm on one side (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some embodiments, the glass core 132 corresponds to a rectangular prism volume with sections (e.g. vias) that have been removed and filled with other materials (e.g. metal, etc.).Among other things, glass cores are advantageous compared to epoxy-based cores because glass is stiffer and therefore provides greater mechanical support or strength for the housing substrate. Thus, the glass core 132 is an exemplary means of reinforcing the housing substrate.

[0011] Development areas 134 and 136 are in Fig. 1 represented as masses / blocks, with the internal intermediate connections 128 extending in straight lines through the build-up areas 134, 136 (and the glass core 132). However, Fig. 1 For clarity and explanatory purposes, the diagram has been simplified. In practice, the intermediate connections are not necessarily straight. In particular, in some examples, the build-up regions 134, 136 are defined by alternating layers of dielectric material and layers of conductive material (e.g., a metal such as copper). The conductive (metal) layers serve as the basis for the internal intermediate connections 128, which are represented in a simplified form by straight lines, as shown in Fig. Figure 1 shows that in some examples the metal layers are structured to define electrical routing or conductor paths that are electrically coupled between different metal layers by conductive (e.g., metal) vias extending through intervening dielectric layers.

[0012] The use of glass as a starting core material (e.g., the glass core 132 from Fig. 1) offers a mechanical advantage (e.g. reduced deflection, smaller thickness variation), an electrical advantage and a design flexibility advantage (e.g. closer through-hole spacing, finer core routing) compared to the use of conventional organic core materials (e.g. epoxy-based prepreg). For example, the glass core 132 can support multi-chip encapsulation (e.g., embedded multi-die interposer bridge (EMIB), heterogeneous 2.5D / 3D integration, hyperchip stacking (silicon(Si) interposer), etc.), reduced first-level interposer (FLI) contact bump grid dimensions (e.g., less than 30 micrometers (µm)), reduced fine-line spacing (FLS) (e.g., 2 / 2 µm), higher-density interposers, higher input / output (I / O) density structuring, increasing form factors, and decreasing case thicknesses compared to conventional organic core materials.To further enhance these advantages, the glass core 132 can include through-glass vias (TGVs) (e.g., copper-clad vias) that extend through the glass core 132 to electrically couple the build area 134 to the build area 136. Although the examples described here refer to the glass core 132, it is understood that the teachings of this disclosure are not limited to it. For example, the teachings of this disclosure are also applicable to organic cores.

[0013] A common type of failure in known glass cores is called a Seware defect. Seware defects result in the separation of a glass core along a crack that propagates from an edge of the core along its length and width between the outer principal surfaces (e.g., top and bottom surfaces, front and back surfaces) of the core. That is, Seware defects are characterized by a glass core being split into two separate glass plates along a line that generally extends parallel to the principal plane of the core.

[0014] Factors contributing to Seware defects include mismatches in the coefficient of thermal expansion (CTE) between different components of a glass core and features mounted on it. For example, the glass of the core (e.g., Glass Core 132, etc.), the metal (e.g., copper, etc.) of the TGVs extending through it, and the organic dielectric material of the buildup layers (e.g., Buildup Layers 130, etc.) deposited on it can all exhibit a CTE. Generally, the material in the buildup areas has a higher CTE than the glass, and the TGV material has a higher CTE than the buildup area material.As a result, the material in the superstructure areas and the material of the TGVs expands and contracts more in response to thermal fluctuations than the glass core, causing thermal internal stress within the glass core that can promote crack propagation.

[0015] Fig. Figure 2 illustrates a cross-sectional side view of a previous housing substrate 200 undergoing a Seware failure. Fig. The housing substrate 200 comprises a glass core 202, several through-holes 204, several TGVs 206 deposited in the through-holes 204, and a build-up material 208. A source of CTE-induced thermal stress is associated with the plating of the metal on the TGVs 206. During electroplating of the TGVs 206, metal is electroplated into the through-holes 204 of the glass core 202 and the first surface 209 thereof. After electroplating the TGVs 206, a first surface 209 of the glass core 202 is etched to remove the deposited metal. However, etching the metal on the glass core 202 can also remove metal at the entrance of the through-holes 204.When the build-up material 208 is subsequently deposited on the first surface 209 of the glass core 202, some of the build-up material 208 enters the openings in the through-holes 204 formed by the etching of the copper on the first surface 209. The resulting lateral stacks 210 of metal, organic dielectric material, and glass in the through-hole of the TGV are stress concentration sites (e.g., a weak point, etc.) and can cause acute concentrations of thermal stresses at the entrance of the through-holes 204. That is, the layering of materials in the lateral stacks 210 can cause high amounts of thermally induced stress if the housing substrate is subject to temperature fluctuations, such as those associated with the manufacture and / or operation of the housing substrate 200. Fig. 2 has caused the stress concentration associated with the lateral stacks 210 to form Seware cracks 212 in the glass core 202 between the TGVs 206.

[0016] Examples disclosed herein reduce (e.g., minimize, etc.) the concern regarding Seware defects in the glass cores of housing substrates. Examples disclosed herein include glass cores with TGVs protruding from the top and bottom surfaces of the glass core. One exemplary manufacturing process disclosed herein involves a multi-operation etching process that includes applying a copper wet etching, a plasma dry etching, and a sulfuric acid wet etching to the outer surfaces of the glass core. In some examples disclosed herein, glass cores include multiple curved surfaces extending between the TGVs. Another exemplary manufacturing process disclosed herein involves a two-operation polishing process that includes chemical-mechanical copper polishing and chemical-mechanical silicon polishing.Examples revealed here prevent the deposition of buffer material within the through-holes of TGVs, which reduces the thermally induced stress to which the glass cores of housing substrates are subjected and improves their service life.

[0017] Fig. Figure 3 is a cross-sectional side view of an exemplary first housing substrate 300, which is the housing substrate 112 made of Fig. 1 can be implemented. In the illustrated example from Fig. Figure 3 includes the first housing substrate 300, an exemplary first glass core 302, several exemplary TGVs 304 in corresponding several exemplary openings 306, an exemplary first buffer layer 307A, an exemplary second buffer layer 307B, an exemplary first build-up layer 308A, and an exemplary second build-up layer 308B. In the illustrated example from Fig. 3 The first glass core 302 includes several exemplary areas 309 arranged between the TGVs 304. In the illustrated example from Fig. 3 The buildup layers 308A, 308B include several exemplary intermediate connections 310 that extend through them. In the illustrated example from Fig. 3 The first glass core 302 includes an exemplary first surface 312A and an exemplary second surface 312B. In the illustrated example from Fig. 3 include the TGVs 304 exemplary projections 314 extending from the first glass core 302. An exemplary first process for manufacturing the first housing substrate 300 from Fig. 3. Etching and the associated intermediate stages of production are discussed below in connection with Fig. 4A-5 described.

[0018] The first glass core 302 corresponds to the glass core 132 from Fig. 1. In the illustrated example from Fig. 3 The first glass core 302 supports the buffer layers 307A, 307B and the buildup layers 308A, 308B and is arranged between them. The buildup layers 308A, 308B correspond to the buildup areas 134, 136 from Fig. 1. In the illustrated example from Fig. 3 include the build-up layers 308A, 308B and intermediate connections 310, which are electrically coupled to the multiple TGVs 304. In some examples, the build-up layers 308A, 308B can be redistribution layers. In some examples, the intermediate connections 310 are electrically coupled to components mounted on the housing substrate 300 (e.g., the dies 108, 110 from Fig. 1 etc.), and electrically couple the TGVs 304 to them.

[0019] In the illustrated example from Fig. In Figure 3, the buffer layers 307A and 307B are arranged on the first surface 312A and the second surface 312B, respectively. In the illustrated example from Fig. In section 3, the buffer layers 307A and 307B are located between the build-up layers 308A and 308B, respectively, and the glass core 302. In the illustrated example from Fig. 3. The buffer layers 307A, 307B contain (e.g., include, consist of, etc.) a dielectric material (e.g., an organic epoxy, an Ajinomoto buildup film (ABF), etc.). In some examples, the buffer layers 307A, 307B promote the adhesion of the buildup layers 308A, 308B to the first glass core 302 due to the poor adhesion of the metal of the intermediates 310 to the first glass core 302. In some examples, the buffer layers 307A, 307B promote the distribution of stress (e.g., buffer stress, etc.) between the glass core 302, the TGVs 304, and the buildup layers 308A, 308B. In the illustrated example from Fig. 3 surround (e.g., span, enclose, partially enclose, enclose, etc.) the buffer layers 307A, 307B the projections 314 of the TGVs 304 at least partially (e.g., the first buffer layer 307A surrounds the projections 314 extending from the first surface 312A, the second buffer 307B surrounds the projections 314 extending from the second surface 312B, etc.). In the illustrated example from Fig. 3. The buffer layers 307A, 307B surround the sides of the projections 314. Additionally or alternatively, the buffer layers 307A, 307B surround the outer surfaces of the projections 314. In some examples, the buffer layers 307A, 307B are missing. In some such examples, the superstructure layers 308A, 308B surround and / or enclose the projections 314 of the TGVs 304.

[0020] The multiple regions 309 of the first glass core 302 are the parts of the glass core 202 that extend between individual TGVs 304. In the illustrated example from Fig. 3. The first glass core 302 exhibits a concave curvature in the several regions 309 (e.g., it shows a deflection towards the interior of the first glass core 302, etc.). That is, each of the several regions 309 has a curved shape. It is understood that the first glass core 302 is a 3-dimensional component that extends into the side of Fig. 3 into and out of this. In some such examples, the multiple regions 309 include one or more curves extending into the side from Fig. 3 extend into and out of this. In some such examples, each of the multiple regions 309 is generally shaped like a meniscus. In some examples, the curvature of the multiple regions 309 is formed by the wet set of the first glass core 302 during its manufacture. The curvature of multiple regions 309 and its formation are related to Fig. 4D described in more detail.

[0021] In the illustrated example from Fig. In the multiple regions 309, the thickness of the first glass core 302 is proportional to its distance from each of the TGVs 304 (e.g., the first glass core 302 has a comparatively greater thickness adjacent to the TGVs 304 and a comparatively smaller thickness distal to the TGVs 304, etc.). In the illustrated example from Fig. 3. The TGVs 304 abut the first glass core 302 at the surfaces 312A, 312B and / or the multiple regions 309 (e.g., are in contact with them, contact them directly, etc.). That is, in each of the multiple regions 309, the first glass core 302 is thicker in areas adjacent to the TGVs 304 and thinner in areas distal to the TGVs 304.

[0022] In the illustrated example from Fig. 3 are the projections 314 the ends of the TGVs 304. In the illustrated example from Fig. 3 The projections 314 of the TGVs 304 extend from the surfaces 312A, 312B of the first glass core 302. That is, the projections 314 are not flush with the surfaces 312A, 312B and are instead displaced outwards from corresponding areas 309 of the first glass core 302. In the illustrated example from Fig. 3. The TGVs 304 project from both the first surface 312A and the second surface 312B (e.g., some of the projections 314 extend above the first surface 312A, some of the projections 314 extend below the second surface 312B, etc.). In other examples, the TGVs 304 project from either the first surface 312A or the second surface 312B (e.g., one of the surfaces 312A, 312B is flush with the ends of the TGVs, etc.).

[0023] In the illustrated example from Fig. 3. Each of the projections 314 is integral (e.g., monolithic with, etc.) and continuous (e.g., non-discrete, etc.) with the corresponding TGVs 304. For example, the projections 314 and the other parts of the TGVs 304 are deposited during the same process (e.g., electroplating the TGVs 304 into the openings 306, etc.) and accordingly form one or more unitary pieces. In some examples, the projections 314 are formed by removing material from adjacent parts of the first glass core 302 (e.g., the projections 314 are formed during etching of the first glass core 302, causing the ends of the TGVs 304 to protrude from the first glass core 302, etc.). In some examples, the projections 314 protrude from the surfaces 312A, 312B with a thickness between 5% and 20% of the total thickness of the first glass core 302.In some examples, the projections 314 have a length above the surface of the first glass core 302 of approximately 5 to approximately 20 micrometers. The projections 314 of the TGVs 304 prevent material from the buffer layers 307A, 307B and / or the buildup layers 308A, 308B from entering the openings 306 during their deposition, thus preventing the formation of a lateral stack of materials with different CTEs (e.g., a lateral stack similar to the lateral stack 210 made of ). Fig. 2 etc.) and prevents the associated increased risk of a Seware failure.

[0024] In the illustrated example from Fig. 3. Buffer layers 307A and 307B include an exemplary first buffer layer surface 316A and an exemplary second buffer layer surface 316B, respectively. In the illustrated example from Fig. 3. The buffer layer surfaces 316A, 316B abut the outer surfaces 312A, 312B (e.g., they are in direct contact, etc.) and are complementary to them. The buffer layer surfaces 316A, 316B have a curvature that is complementary to the curvature of the outer surfaces 312A, 312B.

[0025] Fig. 4A, Fig. 4B, Fig. 4C and Fig. 4D illustrates different intermediate stages in an exemplary first process for manufacturing the first glass core 302 from Fig. 3. Exemplary operations for producing the first glass core 302 from Fig. 3 excludes some or all of the intermediate stages Fig. 4A-4D and are subsequently in conjunction with Fig. 5 described. In some examples, 400 are taken before the exemplary first intermediate stage. Fig. 4A The openings 306 are created in the first glass core 302. For example, the openings 306 in the first glass core 302 can be formed via a LIDE (Laser-Induced Deep Etching) process. In other examples, the openings 306 can be formed via a mechanical process, such as drilling.

[0026] Fig. 4A is a schematic cross-sectional view of an exemplary first intermediate stage 400 of the assembly / production of the first glass core 302 made of Fig. 3. During the first intermediate stage 400, the TGVs 304 can be used. Fig. 3. The TGVs 304 can be deposited in the openings 306 by electroplating. For example, the TGVs 304 can be electroplated into the openings 306 via a preliminary nucleation layer deposited on exemplary inner surfaces 402 of the openings 306. In some examples, the preliminary nucleation layer can be deposited by an electrolysis process. In other examples, the preliminary nucleation layer can be deposited by another process (e.g., lithography, a thin-film deposition process, etc.). In other examples, the TGVs 304 can be electroplated from one of the top or bottom surfaces of the first glass core 302. Additionally or alternatively, the TGVs 304 can be deposited by another suitable method (e.g., lithography, etc.).

[0027] In the illustrated example from Fig. 4A causes the electroplating of the TGVs 304 to deposit an exemplary first overhang 404A and an exemplary second overhang 404B on the surfaces 312A and 312B, respectively. The overhangs 404A and 404B are conductive layers associated with the deposition of excess material during the formation of the TGVs 304. In the illustrated example from Fig. In 4A, the overhangs 404A and 404B are integral with the TGVs 304 and extend from them. In some examples, one of the overhangs 404A or 404B is missing (e.g., the TGVs 304 are flush with the first surface 312A or the second surface 312B, etc.). In the illustrated example from Fig. The overhangs 404A and 404B are electrically coupled to each of the TGVs 304 and materially integrated into them. In the illustrated example from Fig. 4A includes overhangs 404A, 404B, an exemplary first outer overhang surface 405A and an exemplary second outer overhang surface 405B, respectively.

[0028] Fig. 4B is a schematic cross-sectional view of an exemplary second intermediate stage 406 of the assembly / manufacture of the first glass core 302 made of Fig. 3. In some examples, the second intermediate stage 406 can follow the first intermediate stage 400. Fig. 4A. During the second intermediate stage 406, the overhangs 404A, 404B on surfaces 312A, 312B are etched using wet etching. For example, surfaces 312A, 312B are wet etched to remove the overhangs 404A, 404B. For example, an etching solution (e.g., a solution of nitric acid, a solution of ferric chloride, a solution of hydrogen peroxide and sulfuric acid, a solution of copper chloride, etc.) can be applied to the outer overhang surfaces 405A, 405B. Fig. 4A can be applied. In some examples, the etching solution is selected so that it does not react with the glass of the first glass core 302. In the illustrated example from Fig. 4B causes the copper to etch on the surfaces 312A, 312B forming exemplary depressions 408 in the openings 306. Fig. 3. That is, in the illustrated example from Fig. In 4B, the TGVs 304 are thinner than the first glass core 302. In the illustrated example from 4B, the recesses 408 cause the TGVs 304 to not be flush with the surfaces 312A, 312B.

[0029] Fig. 4C is a schematic cross-sectional view of an exemplary third intermediate stage 410 of the assembly / manufacture of the first glass core 302 made of Fig. 3. In some examples, the third intermediate stage 410 can follow the first intermediate stage 400. Fig. 4A. During the third intermediate stage 410, the surfaces 312A, 312B of the first glass core 302 are dry-etched. For example, the surfaces 312A, 312B can be plasma-etched. In some such examples, the surfaces 312A, 312B are plasma-etched over carbon tetrafluoride (CF4), carbon tetrachloride (CCl4), sulfur hexafluoride (SF6), xenon difluoride (XeF2), and / or one or more other plasma carbon fluorides, etc. In some examples, the reaction of the etching plasma and the glass of the glass core near surfaces 312A, 312B causes parts of the first glass core 302 to react with it and form a gas, such as a silicon fluoride and / or a silicon chloride, etc. In some examples, the dry etching medium is selected so that it does not react with copper (e.g., the copper of the TGVs 304 does not react with the dry etching medium, etc.). In other examples, surfaces 312A and 312B can be etched using a different dry etching technique.

[0030] Dry etching weakens the portions of the first glass core 302 near surfaces 312A and 312B. After applying the dry etching medium, surfaces 312A and 312B are wet-etched using sulfuric acid (H₂SO₄) (e.g., acid-etching, acid-washing, etc.). In other examples, surfaces 312A and 312B can be wet-etched using a different medium (e.g., a different acid, etc.). In some examples, the weakened glass near surfaces 312A and 312B is removed by the applied cleaning medium (e.g., washed away, dissolved in it, etc.). In some examples, the cleaning medium applied to surfaces 312A and 312B is selected so as not to affect the copper of the TGVs 304.

[0031] In the illustrated example from Fig. 4C is used to etch the copper of the TGVs 304, which is done with the intermediate stage 410. Fig. 4C is associated, is not affected and / or only slightly affected (e.g., not significantly etched, not significantly removed, etc.). Since the conductive material (e.g., the copper, etc.) of the TGVs 304 is not removed by etching, the exposure of the first glass core 302 to the etching media is proportional to its distance from the TGVs 304. The increased exposure of the glass core 302 near the center of the multiple regions 309 causes the glass of the first glass core 302 to be removed unevenly (e.g., comparatively less material is removed from surfaces 312A, 312B near the TGVs 304, comparatively more material is removed from surfaces 312A, 312B near the TGVs 304, etc.). In the illustrated example from Fig. 4C causes the uneven removal of material from the surfaces 312A, 312B of the first glass core 302, such that the several regions 309 exhibit exemplary curved surfaces 414. In the cross-sectional view of the illustrated example from Fig. 4C, the curved surfaces 414 are generally parabolically shaped. In the illustrated example from Fig. 4C each of the curved surfaces 414 is concave (e.g. the surfaces 414 are curved towards the center of the glass core 302, etc.).

[0032] In other examples, the curved surfaces 414 can have any other curvature profile (e.g., hyperbolic, another polynomial, trigonometric, circular, etc.). It is understood that the curved surfaces 414 are three-dimensional and can include curvature profiles that extend into and out of the side. In some such examples, the curved surfaces 414 are generally meniscus-shaped. In the illustrated example from Fig. 4C causes the etching of the first glass core 302 and the removal of material from it, so that the projections 314 are formed. Fig. 3 of the TGVs 304 extend from the curved surfaces 414 of the first glass core 302.

[0033] Fig. 4D is a schematic cross-sectional view of an exemplary fourth intermediate stage 412 of the assembly / manufacture of the first glass core 302 made of Fig. 3. In some examples, the fourth intermediate stage 412 can follow the third intermediate stage 410 from Fig. 4B. During the fourth intermediate stage 412, the buffer layers 307A, 307B are deposited on the first surface 312A and the second surface 312B of the first glass core 302. For example, the buffer layers 307A, 307B can be deposited by lamination, a thin-film deposition process and / or another suitable deposition process (e.g. CVD, ALD, etc.).

[0034] Fig. Figure 5 is a flowchart representing an exemplary procedure 500 that can be carried out to produce any of the exemplary first housing substrate 300 from Fig. 3 via the intermediate stages 400, 406, 410, 412 from Fig. 4A-4D to manufacture. In some examples, some or all of the components used in the exemplary procedure are manufactured from Fig. The five outlined operations are performed automatically by equipment programmed to carry out the operations. That is to say, in some examples, the exemplary procedure or parts thereof can be implemented and / or controlled by one or more processor circuits that execute instructions based on data from sensors and / or user input. Although the exemplary procedure refers to the one in Fig. As described in the illustrated flowchart, many other methods can be used alternatively. For example, the order in which the blocks are executed can be changed, and / or some of the described blocks can be combined, split, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, in some examples, additional processing operations can be performed before, between, and / or after any of the blocks illustrated in the example.

[0035] The exemplary procedure from Fig. Section 5 begins at block 502, where the first glass core 302 is prepared. In some examples, the first glass core 302 can be prepared by pouring a glass mixture into a planar mold. In other examples, the first glass core 302 can be prepared in any other suitable way. In some examples, the first glass core 302 is created with the openings 306. In some examples, the first glass core 302 can be positioned in a fabrication environment. At block 504, the TGVs 304 are created in the first glass core 302. For example, the TGVs 304 can be deposited in the openings 306 by electroplating. In some examples, the TGVs 304 can be created via a preliminary nucleation layer formed on the inner surfaces 402. Fig. 4A is deposited into the openings 306 and electroplated. In some examples, the preliminary nucleation layer can be deposited via an electrolysis process. In other examples, the preliminary nucleation layer can be deposited via another process (e.g., lithography, a thin-film deposition process, etc.). In other examples, the TGVs 304 can be electroplated from one of the surfaces 312A, 312B. Additionally or alternatively, the TGVs 304 can be deposited in another suitable way (e.g., lithography, etc.). In some examples, the generation of the TGVs 304 causes the formation of the overhangs 404A, 404B on the surfaces of the first glass core 302 (e.g., the surfaces 312A, 312B, etc.). The point of fabrication after completion of block 504 corresponds to the structure of the first intermediate stage 400. Fig. 4A.

[0036] In Block 506, the overhangs 404A and 404B of the TGVs 304 are etched. For example, the overhangs 404A and 404B on surfaces 312A and 312B can be etched using wet etching. For example, the outer overhang surfaces 405A and 405B are etched using copper etching to remove the overhangs 404A and 404B. In the illustrated example from Fig. 4B causes the copper to etch on the outer overhang surfaces 405A, 405B the formation of exemplary depressions 408 in the openings 306 from Fig. 3. In the illustrated example, the recesses 408 cause the TGVs 304 to be not flush with the surfaces 312A, 312B. The point of manufacture after completion of block 506 corresponds to the structure of the second intermediate stage 406. Fig. 4B.

[0037] In block 508, the first glass core 302 is plasma-etched. For example, surfaces 312A and 312B can be plasma-etched. These surfaces can be plasma-etched using carbon tetrafluoride (CF4), carbon tetrachloride (CCl4), sulfur hexafluoride (SF6), xenon difluoride (XeF2), and / or other plasma carbon fluorides, etc. In some examples, the reaction of the etchant and the glass of the core near surfaces 312A and 312B causes parts of the first core 302 to react with it, forming a gas such as silicon fluoride and / or silicon chloride, etc. In some examples, the dry etching medium is selected so that it does not react with copper (e.g., the copper of the TGVs 304 does not react with the dry etching medium, etc.). In other examples, surfaces 312A and 312B can be etched using a dry etching technique.In some examples, dry etching weakens the parts of the first glass core 302 near surfaces 312A, 312B. The point of fabrication after completion of block 508 corresponds to the structure of the third intermediate stage 410. Fig. 4C.

[0038] In block 510, the first glass core 302 is wet-etched. For example, surfaces 312A and 312B of the first glass core 302 are wet-etched. For example, surfaces 312A and 312B can be wet-etched with sulfuric acid (H₂SO₄). In other examples, surfaces 312A and 312B can be wet-etched using a different medium (e.g., a different acid, etc.). In some examples, the weakened glasses near surfaces 312A and 312B are removed by the wet-etching medium (e.g., washed away, dissolved in it, etc.). In some examples, the wet-etching medium applied to surfaces 312A and 312B is selected so that it does not affect the copper of the TGVs 304. The point of manufacture after completion of block 510 corresponds to the structure of the third intermediate stage 410. Fig. 4C.

[0039] In block 512, the buffer layers 307A and 307B are deposited onto the surfaces 312A and 312B. For example, the buffer layers 307A and 307B can be deposited by lamination, a thin-film deposition process, and / or another suitable deposition method (e.g., CVD, ALD, etc.). The manufacturing point after completion of block 512 corresponds to the structure of the fourth intermediate 412. Fig. 4D. The 500 process ends. The completed substrate core can then be subjected to any suitable subsequent processing (e.g., adding buildup layers, attaching one or more dies, and implementing other encapsulation processes).

[0040] Although exemplary operations with reference to the in Fig. As described in the 5 illustrated flowcharts, many other methods for assembling / manufacturing the first glass core 302 can be used. Fig. 3. Alternatively, it can be used. For example, the order in which the blocks are executed can be changed and / or some of the described blocks can be modified, removed, or combined.

[0041] Fig. Figure 6 is a cross-sectional side view of an exemplary second housing substrate 600, which is the housing substrate 112 made of Fig. 1 can be implemented. The second housing substrate 600 is the same as the first housing substrate made of Fig. 3 similar, unless otherwise stated. In the illustrated example from Fig. 6 includes the second housing substrate 600, an exemplary second glass core 602, which contains the multiple openings 306 made of Fig. 3 includes. In the illustrated example from Fig. 6 contains the second glass core 602, which includes the several TGVs 304 from Fig. 3 in corresponding of the several openings 306 from Fig. 3, the build-up layers 308A, 308B from Fig. 3 and the intermediate connections 310 from Fig. 3. In the illustrated example from Fig. 6 The second glass core 602 includes several exemplary areas 604 that extend between the TGVs 304. In the illustrated example from Fig. 6 the second glass core 602 includes an exemplary first surface 606A and an exemplary second surface 606B.

[0042] In the illustrated example from Fig. 6. The outer surfaces 606A, 606B of the several regions 604 of the second glass core 602 are essentially planar (e.g., not curved, flat, etc.). That is, the outer surfaces 606A, 606B of the second glass core 602 are parallel to and recessed from the top of the TGVs 304. In the illustrated example from Fig. In example 6, each of the multiple areas 604 is coplanar. In other examples, the multiple areas 604 are not coplanar (e.g., some of the multiple areas 604 are indented by others of the multiple areas 604, etc.). In the illustrated example from Fig. 6. The TGVs 304 collide with the second glass core 602 at the surfaces 606A, 606B and / or the multiple areas 604 (e.g., are in contact with them, contact them directly, etc.).

[0043] In the illustrated example from Fig. Figure 6 includes the second housing substrate 600, an exemplary first buffer layer 607A, and an exemplary second buffer layer 607B. The buffer layers 607A and 607B are derived from the buffer layers 307A and 307B. Fig. 3, similarly, except that the buffer layers 607A, 607B have a planar surface geometry adjacent to the outer surfaces 606A, 606B (e.g., the buffer layers 607A, 607B have a shape that corresponds to and is complementary to the outer surfaces 606A, 606B, etc.). In the illustrated example from Fig. 6 surround (e.g., enclose, partially enclose, etc.) the buffer layers 607A, 607B the projections 314 of the TGVs 304 (e.g., the first buffer layer 607A surrounds the projections 314 extending from the first surface 606A, the second buffer layer 607B surrounds the projections 314 extending from the second surface 606B, etc.).

[0044] In the illustrated example from Fig. 6 include the TGVs 304 projections 608, which are the projections 314 from Fig. 3 are similar unless otherwise stated. In the illustrated example from Fig. 6 The projections 314 of the TGVs 304 extend from the outer surfaces 606A, 606B of the second glass core 602. That is, the projections 608 are not flush with the outer surfaces 606A, 606B and are displaced outwards from the several areas 604 of the second glass core 602 (e.g., protrude, etc.). In the illustrated example from Fig. In 6, the TGVs 304 project from both the first surface 606A and the second outer surface 606B of the second glass core 602. In other examples, the TGVs 304 project from either the first surface 606A or the second outer surface 606B of the second glass core 602. In some examples, the projections 608 project from the outer surfaces 606A, 606B with a thickness between 5% and 20% of the total thickness of the second glass core 602. In some examples, the projections 608 are between 5 and 20 micrometers long. The projections 608 of the TGVs 304 prevent material from the buffer layers 607A, 607B and / or the build-up layers 308A, 308B from entering the through-holes 306 during deposition, thus preventing the formation of a lateral stack of materials with different CTEs (e.g., a lateral stack similar to the lateral stack 210 made of Fig. 2 etc.) prevented. An exemplary second process for producing the second housing substrate 600 from Fig. Section 6 concerning chemical-mechanical polishing and the associated intermediate stages of production are discussed below in conjunction with Fig. 7A-8 described.

[0045] Fig. 7A, Fig. 7B, Fig. 7C and Fig. Figure 7D illustrates different intermediate stages in an exemplary second manufacturing process for producing the second housing substrate 600. Fig. 6. Exemplary operations for producing the second housing substrate 600 from Fig. 6 excludes some or all of the intermediate stages Fig. 7A-7D and are subsequently in conjunction with Fig. 7 described. In some examples, before the exemplary first intermediate stage 400, the following is taken from Fig. 4A, the second glass core 602 is prepared in a manner similar to the preliminary process applied to the first glass core 302 before the first intermediate stage 400, which is in conjunction with Fig. 4A is described.

[0046] Fig. 7A is a schematic cross-sectional view of an exemplary first intermediate stage 700 of the assembly / manufacture of the second glass core 602 made of Fig. 6. During the first intermediate stage 700, the TGVs 304 can be used. Fig. 3 in the openings 306 by electroplating. For example, the TGVs 304 can be electroplated in a similar manner to the deposition of the TGVs 304 that are made in conjunction with the first intermediate stage 400. Fig. 7A is described. In the illustrated example from Fig. 7A forms the separation of the TGVs 304 the overhangs 404A, 404B. Fig. 4A, which form the corresponding outer overhang surfaces 405A, 405B Fig. 4A can be present.

[0047] Fig. 7B is a schematic cross-sectional view of an exemplary second intermediate stage 702 of the assembly / manufacture of the second glass core 602 made of Fig. 6. In some examples, the second intermediate stage 702 can follow the first intermediate stage 700. Fig. 7A. During the illustrated example from Fig. 7B, the outer overhang surfaces 405A, 405B of the glass core are polished by a first chemical-mechanical polishing (CMP) process. In the illustrated example from Fig. In 7B, the first CMP process, applied to the outer overhang surfaces 405A, 405B, causes exemplary depressions 408 to form in the openings 306 (e.g., the first CMP process causes the TGVs 304 to be recessed into the outer surfaces 606A, 606B, etc.). In other examples, the first CMP process causes the top and / or bottom surfaces of the TGVs 304 to be flush with the outer surfaces 606A, 606B (e.g., the depressions 408, etc., are missing).

[0048] In some examples, during the second intermediate stage 702, the outer overhang surfaces 405A, 405B are polished with a medium (e.g., a CMP slurry, etc.) selected to remove the copper of the overhangs 404A, 404B and the TGVs 304 (e.g., copper, etc.) at a faster rate than the glass of the second glass core 602 (e.g., a copper-specific slurry, etc.). For example, an aluminum oxide (AlO3) and / or silicon oxide (SiO2) slurry can be used to abrade and oxidize the copper of the overhangs 404A, 404B (e.g., oxidize to a copper oxide, which is oxidized to a copper chloride, etc.) and is not harsh enough to significantly degrade the glass of the second glass core 602. In some examples, the medium contains chemicals (e.g., ammonium chloride, copper sulfate, ammonium sulfate, etc.) that etch and / or oxidize the copper of the overhangs 404A, 404B.In some examples, after applying the CMP medium, the outer overhang surfaces 405A, 405B can be treated with an acid and / or another solvent to remove the oxidized copper. In the illustrated example from... Fig. 7A involves chemical-mechanical polishing of the outer surfaces 606A, 606B, the overhangs 404A, 404B, and part of the TGVs 304 within the openings 306. In other examples, the outer overhang surfaces 405A, 405B of the overhangs 404A, 404B are polished until the copper of the TGVs 304 is flush with the outer surfaces 606A, 606B.

[0049] Fig. 7C is a schematic cross-sectional view of an exemplary third intermediate stage 704 of the assembly / manufacture of the first glass core 302 made of Fig. 3. In some examples, the third intermediate stage 704 can follow the second intermediate stage 702 from Fig. 7B. During the third intermediate stage 704, the outer surfaces 606A, 606B of the second glass core 602 are polished via a second chemical-mechanical polishing (CMP) process. In some examples, the outer surfaces 606A, 606B can be polished with a medium (e.g., a CMP slurry, etc.) selected to remove material from the glass of the second glass core 602 at a faster rate than the conductive material of the TGVs 304 (e.g., a glass / oxide-specific slurry). For example, a cerium (Ce)-based slurry, such as cerium oxide (CeO2), can be selected to polish the glass of the second glass core 602.

[0050] In the illustrated example from Fig. 7C causes the application of the second CMP process to the outer surfaces 606A, 606B of the second glass core 602 and the corresponding removal of material from it, resulting in the deepening of the several areas 604. In the illustrated example from Fig. 7C, after the second CMP, the projections 314 of the TGVs 304 extend from the outer surfaces 606A, 606B.

[0051] Fig. 7D is a schematic cross-sectional view of an exemplary fourth intermediate stage 706 of the assembly / manufacture of the second glass core 602 made of Fig. 6. In some examples, the fourth intermediate stage 706 can follow the third intermediate stage 704 from Fig. 7C. During the fourth intermediate stage 706, the buffer layers 607A, 607B are deposited on the first outer surface 606A and the second outer surface 606B of the second glass core 602. For example, the buffer layers 607A, 607B can be deposited in a manner similar to the deposition of the buffer layers 307A, 307B, which is carried out in conjunction with the fourth intermediate stage 412. Fig. 4D is described.

[0052] Fig. Figure 8 is a flowchart representing an exemplary second procedure 800 that can be carried out to produce the exemplary second housing substrate 600 from Fig. 6 via the intermediate stages 700, 702, 704 from Fig. 7A-7C to manufacture. In some examples, some or all of the components used in the exemplary procedure are manufactured from Fig. The 8 outlined operations are performed automatically by equipment programmed to carry out the operations. That is to say, in some examples, the exemplary procedure or parts thereof can be implemented and / or controlled by one or more processor circuits that execute instructions based on data from sensors and / or user input. Although the exemplary procedure refers to the one in Fig. As described in the illustrated flowchart 8, many other methods can be used alternatively. For example, the order in which the blocks are executed can be changed, and / or some of the described blocks can be combined, split, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, in some examples, additional processing operations can be performed before, between, and / or after any of the blocks illustrated in the example.

[0053] The exemplary procedure from Fig. Figure 8 begins at block 802, where the second glass core 602 is prepared. In some examples, the second glass core 602 can be prepared by pouring a glass mixture into a planar mold. In other examples, the second glass core 602 can be prepared in any other suitable way. In some examples, the second glass core 602 can be positioned in a manufacturing environment. At block 804, the TGVs 304 are formed in the second glass core 602. For example, the TGVs 304 can be formed via the process used in conjunction with block 504. Fig. The operations described in section 5 are deposited in the second glass core 602. In other examples, the TGVs 304 can be deposited in any other suitable manner. In some examples, the formation of the TGVs 304 causes the overhangs 404A, 404B to be deposited on the outer surfaces 606A, 606B. The point of fabrication after completion of block 804 corresponds to the structure of the first intermediate stage 700. Fig. 7A.

[0054] In Block 806, the outer overhang surfaces 405A, 405B of overhangs 404A, 404B are polished via a first chemical-mechanical polishing (CMP) process. In some examples, the outer overhang surfaces 405A, 405B can be polished with a medium (e.g., a CMP slurry, etc.) selected to remove the copper of overhangs 404A, 404B and the TGVs 304 (e.g., copper, etc.). For example, an aluminum oxide and / or silicon oxide-based slurry can be used to abrade and oxidize the copper of overhangs 404A, 404B (e.g., oxidize to a copper oxide, which is oxidized to a copper chloride, etc.). In some examples, the medium of the first chemical-mechanical polishing process is selected to remove the conductive material (e.g. copper, etc.) of the TGVs 304 and not the glass (e.g. silicon oxide, etc.) of the second glass core 602.In some examples, after applying the medium, the outer overhang surfaces 405A, 405B can be treated with an acid and / or another solvent to remove the oxidized copper. In some examples, chemical-mechanical polishing of the surfaces 312A, 312B removes the overhangs 404A, 404B and a portion of the TGVs 304 within the openings 306. In other examples, the outer overhang surfaces 405A, 405B of the overhangs 404A, 404B are polished until the copper of the TGVs 304 is flush with the outer surfaces 606A, 606B. The point of manufacture after completion of block 806 corresponds to the structure of the second intermediate stage 702. Fig. 7B.

[0055] In Block 808, the outer surfaces 606A, 606B of the second glass core 602 are polished via a second CMP process. In some examples, the outer surfaces 606A, 606B can be polished with a medium (e.g., a CMP slurry, etc.) selected to remove the glass of the second glass core 602 and not the conductive material of the TGVs 304. For example, a cerium (Ce)-based slurry, such as cerium oxide (CeO2), can be selected to abrade the glass of the second glass core 602. In Block 810, the buffer layers 307A, 307B are deposited on the outer surfaces 606A, 606B. For example, the buffer layers 307A, 307B can be deposited via the process used in conjunction with Block 512. Fig. The processes described in 5 are separated. The point of production after completion of block 810 corresponds to the structure of the fourth intermediate stage 706 from Fig. 7D. The 800 procedure is complete. The completed substrate core can then be subjected to any suitable subsequent processing (e.g., adding buildup layers, attaching one or more dies, and implementing other encapsulation processes). Although exemplary operations are described with reference to the [reference to be added], Fig. As illustrated in the flowchart 8, many other methods for assembling / manufacturing the second housing substrate 600 can be used. Fig. 6. Alternatively, it can be used. For example, the order in which the blocks are executed can be changed and / or some of the described blocks can be modified, removed, or combined.

[0056] The exemplary IC package 100 made of Fig. 1 (e.g. with the first housing substrate 300, with the second housing substrate 600, etc.), disclosed herein, can be incorporated into any suitable electronic component. Fig. Figures 9-12 illustrate various examples of devices that may contain or be contained in the IC package 100 disclosed herein.

[0057] Fig. Figure 9 is a top view of a wafer 900 and of dies 902, which are in the IC package 100. Fig. 1 (e.g., any suitable dies 108, 110). The wafer 900 contains a semiconductor material and one or more dies 902 with a circuit arrangement. Each die 902 can be a repeating unit of a semiconductor product. After the fabrication of the semiconductor product is complete, the wafer 900 can undergo a singulation process in which the dies 902 are separated from each other to provide discrete "chips". The die 902 contains one or more transistors (e.g., some of the transistors 1040 discussed below). Fig. 10), a supporting circuit arrangement for routing electrical signals to the transistors, passive components (e.g., traces, resistors, capacitors, inductors, and / or other circuit arrangement), and / or any other components. In some examples, the Die 902 may include and / or implement a memory device (e.g., a random-access memory (RAM) device such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit arrangement. Several of these devices may be combined on a single die (e.g., the Die 902, etc.). For example, a memory array consisting of multiple memory circuits on the same die (e.g., the 902 die, etc.) can be configured like a programmable circuit arrangement (e.g.,the processor circuit arrangement 1202 from . Fig. 12) and / or another logic circuit arrangement. Such a memory can store information for use by the programmable circuit arrangement. The exemplary IC package 100 disclosed herein can be fabricated using a die-on-wafer assembly technique in which some dies are attached to a wafer 900, which contains the other dies, and the wafer 900 is subsequently singulated.

[0058] Fig. Figure 10 is a cross-sectional side view of an IC device 1100, which may be contained in the exemplary IC package 100 (e.g., in any of the dies 108, 110). One or more of the IC devices 1000 may be contained in one or more dies 902 ( Fig. 9) be included. The IC device 1000 can be mounted on a die substrate 1002 (e.g., the wafer 900 made of Fig. 9) be formed and can be in a Die (e.g. the Die 902 from Fig. 9) be included. The die substrate 1002 may be a semiconductor substrate comprising semiconductor materials that include, for example, n-type or p-type material systems (or a combination of both). The die substrate 1002 may, for example, include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 1002 may be formed using alternative materials that may or may not be combined with silicon and that include, among others, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1002.Although only a few examples of materials from which the die substrate 1002 can be formed are described here, any material that can serve as a basis for an IC device 1000 can be used. The die substrate 1002 can be part of a single die (e.g., the die 902 from...). Fig. 9) or a wafer (e.g., wafer 900 from Fig. 9) be.

[0059] The IC device 1000 can include one or more device layers 1004 arranged on and / or above the substrate 1002. The device layer 1004 can include features of one or more transistors 1040 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1002. The device layer 1004 can, for example, include one or more source and / or drain (S / D) regions 1020, a gate 1022 for controlling current flow between the S / D regions 1020, and one or more S / D contacts 1024 for supplying electrical signals to / from the S / D regions 1020. The 1040 transistors may include additional features not shown for clarity, such as device isolation areas, gate contacts, and the like. The 1040 transistors are not shown in the Fig. The type(s) and configuration(s) shown are limited and can include a wide variety of other types and / or configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors, such as dual-gate or tri-gate transistors, and wrap-around or all-around-gate transistors, such as nanoband and nanowire transistors.

[0060] Each 1040 transistor can include a 1022 gate, including a gate dielectric and a gate electrode. The gate dielectric can consist of a single layer or a stack of layers. The single or multiple layers can contain silicon dioxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material can contain elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and / or lead zinc cniobate.In some examples, a tempering process can be performed on the gate dielectric to improve its quality when a high-k material is used.

[0061] The gate electrode can be formed on the gate dielectric and, depending on whether the 1040 transistor is to be a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor, may contain at least one p-type or n-type output metal. In some implementations, the gate electrode may contain a stack of two or more metal layers, where one or more metal layers are output metal layers and at least one metal layer is a filler metal layer. Additional metal layers, such as a barrier layer, may also be included. For a PMOS transistor, metals that can be used for the gate electrode include, among others, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide) and / or any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning).For an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and / or aluminum carbide) and / or any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

[0062] In some embodiments, when viewed as a cross-section of transistor 1040 along the source-channel-drain direction, the gate electrode may comprise a U-shaped structure comprising a lower portion that is substantially parallel to the surface of the die substrate 1002 and two sidewall portions that are substantially perpendicular to the first surface of the die substrate 1002. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer that is substantially parallel to the first surface of the die substrate 1002 and does not include any sidewall portions that are substantially perpendicular to the first surface of the die substrate 1002. In still other examples, the gate electrode may comprise a combination of U-shaped structures and / or planar, non-U-shaped structures.For example, the gate electrode can include one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0063] In some examples, a pair of sidewall spacers may be formed on opposite sides of the gate stack to clamp the gate stack. The sidewall spacers can be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. Processes for forming sidewall spacers are well known in engineering and generally involve deposition and etching processes. In some examples, multiple pairs of spacers may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0064] The S / D regions 1020 can be formed within the die substrate 1002 adjacent to the gate 1022 of a corresponding transistor (or transistors) 1040. The S / D regions 1020 can be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the die substrate 1002 to form the S / D regions 1020. A tempering process, which activates the dopants and causes them to diffuse further into the die substrate 1002, can follow the ion implantation process. In the latter process, the die substrate 1002 can first be etched to form depressions at the locations of the S / D areas 1020.An epitaxial deposition process can then be performed to fill the wells with a material used to fabricate the S / D regions 1020. In some implementations, the S / D regions 1020 can be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy can be doped in situ with dopants, such as boron, arsenic, or phosphorus. In some examples, the S / D regions 1020 can be formed using one or more alternative semiconductor materials, such as germanium or a Group III-V material or alloy. In other examples, one or more layers of metal and / or metal alloys can be used to form the S / D regions 1020.

[0065] Electrical signals, such as power and / or input / output (I / O) signals, can be passed to and / or from the devices (e.g., transistors 1040) of the device layer 1004 through one or more interconnection layers located on the device layer 1004 (in Fig. 10 are arranged as interconnection layers 1006-1010. For example, electrically conductive features of the device layer 1004 (e.g., the gate 1022 and the S / D contacts 1024) can be electrically coupled to the interconnection structures 1028 of the interconnection layers 1006-1010. The one or more interconnection layers 1006-1010 can form a metallization stack (also referred to as an "ILD stack") 1019 of the IC device 1000.

[0066] The interconnection structures 1028 can be arranged within the interconnection layers 1006-1010 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to those shown in Fig. 10. The special configuration of interconnect structures shown is limited to 1028). Although a special number of interconnect layers 1006-1010 in Fig. The examples shown in Figure 10 include IC devices with more or fewer interconnect layers than shown.

[0067] In some examples, the interconnection structures 1028 may include conductors 1028A and / or vias 1028B filled with an electrically conductive material, such as a metal. The conductors 1028A may be arranged to carry electrical signals in a direction along a plane that is substantially parallel to a surface of the die substrate 1002 on which the device layer 1004 is formed. For example, the conductors 1028A may carry electrical signals in a direction into and / or out of the side from the perspective in Fig. The vias 1028B can be arranged to carry electrical signals in a direction along a plane that is substantially perpendicular to the surface of the die substrate 1002 on which the device layer 1004 is formed. In some examples, the vias 1028B can electrically couple lines 1028A of different interconnection layers 1006-1010.

[0068] The intermediate interconnect layers 1006-1010 can include a dielectric material 1026 arranged between the intermediate interconnect structures 1028, as shown in Fig. Figure 10 shows. In some examples, the dielectric material 1026 arranged between the interconnection structures 1028 in different interconnection layers 1006-1010 can have different compositions; in other examples, the composition of the dielectric material 1026 can be the same between different interconnection layers 1006-1010.

[0069] A first interconnection layer 1006 (designated as metal 1 or "M1") can be formed directly on the device layer 1004. In some examples, the first interconnection layer 1006 can include conductors 1028A and / or vias 1028B, as shown. The conductors 1028A of the first interconnection layer 1006 can be coupled to contacts (e.g., the S / D contacts 1024) of the device layer 1004.

[0070] A second interconnect layer 1008 (designated as Metal 2 or "M2") can be formed directly on top of the first interconnect layer 1006. In some examples, the second interconnect layer 1008 may include vias 1028B to couple the conductors 1028A of the second interconnect layer 1008 to the conductors 1028A of the first interconnect layer 1006. Although the conductors 1028A and the vias 1028B are structurally delineated by a line within each interconnect layer (e.g., within the second interconnect layer 1008) for clarity, the conductors 1028A and the vias 1028B may be structurally and / or materially connected in some examples (e.g., being filled simultaneously during a dual-damascene process).

[0071] A third interconnect layer 1010 (designated as Metal 3 or “M3”) (and additional interconnect layers if required) can be formed sequentially on the second interconnect layer 1008 according to similar techniques and / or configurations described in connection with the second interconnect layer 1008 or the first interconnect layer 1006. In some examples, the interconnect layers located “further up” in the metallization stack 1019 in the IC device 1000 (i.e., farther from the device layer 1004) can be thicker.

[0072] The IC device 1000 can include a solder mask material 1034 (e.g., polyimide or a similar material) and one or more conductive contacts 1036 formed on the interlinking layers 1006-1010. Fig. Figure 10 illustrates the conductive contacts 1036 taking the form of bond pads. The conductive contacts 1036 can be electrically coupled to the interconnection structures 1028 and configured to carry the electrical signals from the transistor(s) 1040 to other external devices. For example, solder bonds can be formed on one or more of the conductive contacts 1036 to mechanically and / or electrically couple a chip containing the IC device 1000 to another component (e.g., a printed circuit board). The IC device 1000 can include additional or alternative structures to carry the electrical signals from the interconnection layers 1006-1010; for example, the conductive contacts 1036 can include other analog features (e.g., pins) that carry the electrical signals to external components.

[0073] Fig. Figure 11 is a cross-sectional side view of an IC device assembly 1100, which may include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 1100 includes a number of components arranged on a printed circuit board 1102 (which may, for example, be a main board). The IC device assembly 1100 includes components arranged on a first surface 1140 of the printed circuit board 1102 and on an opposite second surface 1142 of the printed circuit board 1102; generally, components may be arranged on one or both surfaces 1140 and 1142. Any of the IC packages discussed below with reference to the IC device assembly 1100 may have the shape of the exemplary IC package 100. Fig. exhibit 1.

[0074] In some examples, the printed circuit board 1102 can be a printed circuit board (PCB) containing several metal layers separated by layers of dielectric material and connected by electrically conductive vias. One or more of the metal layers can be arranged in a desired circuit structure to carry electrical signals (optionally in conjunction with other metal layers) between the components connected to the printed circuit board 1102. In some examples, the printed circuit board 1102 can be a non-PCB substrate.

[0075] The in Fig. Figure 11 illustrates the IC device assembly 1100, which includes a package-on-interposer structure 1136 coupled to the first surface 1140 of the printed circuit board 1102 by coupling components 1116. The coupling components 1116 can electrically and mechanically couple the package-on-interposer structure 1136 to the printed circuit board 1102 and can accommodate solder balls (as shown in Figure 1100). Fig. 11), including male and female parts of a base, an adhesive, a backing material and / or any other suitable electrical and / or mechanical coupling structure.

[0076] The package-on-interposer structure 1136 can include an IC package 1120 coupled to an interposer 1104 by coupling components 1118. The coupling components 1118 can take any shape suitable for the application, such as the shapes discussed above with reference to the coupling components 1116. Although a single IC package 1120 in Fig. As shown in Figure 11, several IC packages can be coupled to the interposer 1104; in fact, additional interposers can be coupled to the interposer 1104. The interposer 1104 can provide an intermediate substrate that forms a bridge between the printed circuit board 1102 and the IC package 1120. The IC package 1120 can, for example, be a die (the die 902 from Fig. 9), an IC device (e.g. the IC device 1000 from Fig. 10) or any other suitable component, or include it. In general, the interposer 1104 can spread a connection to a larger pitch or redirect a connection to another connection. For example, the interposer 1104 can couple the IC package 1120 (e.g., a die) to a set of conductive BGA contacts of the coupling components 1116 for coupling to the printed circuit board 1102. In the case of the Fig. In the 11 illustrated examples, the IC package 1120 and the printed circuit board 1102 are mounted on opposite sides of the interposer 1104; in other examples, the IC package 1120 and the printed circuit board 1102 may be mounted on the same side of the interposer 1104. In some examples, three or more components may be interconnected using the interposer 1104.

[0077] In some examples, the interposer 1104 may be formed as a PCB comprising several metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 1104 may be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1104 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 1104 may include metal interfacings 1108 and vias 1110, including, but not limited to, silicon through-silicon vias (TSVs) 1106.The interposer 1104 can further include embedded devices 1114, which comprise both passive and active devices. Such devices can include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the interposer 1104. The package-on-interposer structure 1136 can take the form of any package-on-interposer structure known in the art.

[0078] The IC device assembly 1100 can include an IC package 1124, which is coupled to the first surface 1140 of the printed circuit board 1102 by coupling components 1122. The coupling components 1122 can take the form of any of the examples discussed above with reference to the coupling components 1116, and the IC package 1124 can take the form of any of the examples discussed above with reference to the IC package 1120.

[0079] The in Fig. Figure 11 illustrates the IC device assembly 1100, which includes a case-on-case structure 1134 coupled to the second surface 1142 of the printed circuit board 1102 by coupling components 1128. The case-on-case structure 1134 can include a first IC package 1126 and a second IC package 1132, which are coupled to each other by coupling components 1130 such that the first IC package 1126 is located between the printed circuit board 1102 and the second IC package 1132. The coupling components 1128, 1130 can take the form of any examples of the coupling components 1116 discussed previously, and the IC packages 1126, 1132 can take the form of any examples of the IC package 1120 discussed previously. The package-on-package structure 1134 can be configured according to any package-on-package structure known in the art.

[0080] Fig. Figure 12 is a block diagram of an exemplary electrical device 1200, which may include one or more of the exemplary IC package 100. For example, any suitable components of the electrical device 1200 may include one or more of the device assemblies 1100, IC devices 1000, or Dies 902 disclosed herein and may be arranged in the exemplary IC package 100. A number of components are shown in Figure 12. Fig. Figure 12 illustrates the components contained in electrical device 1200; however, any one or more of these components may be omitted or duplicated as appropriate for the application. In some examples, some or all of the components contained in electrical device 1200 may be attached to one or more mainboards. In some examples, some or all of these components may be fabricated on a single system-on-a-chip (SoC) die.

[0081] In addition, in various examples, the electrical device 1200 may not include one or more of the components described in Fig.Of the 12 illustrated components, the electrical device 1200 may include an interface circuit arrangement for coupling with one or more of the components. For example, the electrical device 1200 may not include a display 1206, but may include a display interface circuit arrangement (e.g., a connector and a driver circuit arrangement) to which a display 1206 can be coupled. In another set of examples, the electrical device 1200 may not include an audio input device 1218 (e.g., a microphone) or an audio output device 1208 (e.g., a loudspeaker, a headset, earphones, etc.), but may include an audio input or output device interface circuit arrangement (e.g., a connector and a support circuit arrangement) to which an audio input device 1218 or an audio output device 1208 can be coupled.

[0082] The electrical device 1200 can include a programmable circuit arrangement 1202 (e.g., one or more processing devices). The programmable circuit arrangement 1202 can include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1200 can include a memory 1204, which itself can include one or more memory devices, such as volatile memory (e.g., dynamic random-access memory (DRAM)), non-volatile memory (e.g.,Read-only memory (ROM), flash memory, solid-state memory, and / or a hard disk. In some examples, memory 1204 may include a memory that shares a die with the programmable circuit arrangement 1202. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or magnetic spin transfer torque random-access memory (STT-MRAM).

[0083] In some examples, the electrical device 1200 may include a communication chip 1212 (e.g., one or more communication chips). For example, the communication chip 1212 may be configured to manage wireless communications for the transmission of data to and from the electrical device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices contain no wires whatsoever, although in some examples they may not.

[0084] The 1212 communication chip can implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g. IEEE 802.16-1105 amendment), Long-Term Evolution (LTE) project along with all changes, updates and / or revisions (e.g. Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass compliance and interoperability tests for the IEEE 802.16 standards.The 1212 communication chip can operate according to a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The 1212 communication chip can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The 1212 communication chip can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and variations thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. The 1212 communication chip can also operate according to other wireless protocols in other examples.The electrical device 1200 can include an antenna 1222 to enable wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions).

[0085] In some examples, the 1212 communication chip can manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., Ethernet). As mentioned above, the 1212 communication chip can contain multiple communication chips. For example, a first 1212 communication chip can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second 1212 communication chip can be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first 1212 communication chip can be dedicated to wireless communications and a second 1212 communication chip can be dedicated to wired communications.

[0086] The electrical device 1200 may include a battery / power circuit arrangement 1214. The battery / power circuit arrangement 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit arrangement for coupling components of the electrical device 1200 to a power source separate from the electrical device 1200 (e.g., the AC mains supply).

[0087] The electrical device 1200 can include a display 1206 (or a corresponding interface circuit arrangement, as discussed above). The display 1206 can include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0088] The electrical device 1200 can include an audio output device 1208 (or a corresponding interface circuit arrangement, as previously discussed). The audio output device 1208 can include any device that generates an acoustic indicator, such as a loudspeaker, headphones, or earphones.

[0089] The electrical device 1200 can include an audio input device 1218 (or a corresponding interface circuit arrangement, as discussed above). The audio input device 1218 can include any device that generates a signal representing a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a Musical Instrument Digital Interface (MIDI) output).

[0090] The electrical device 1200 can include a GPS circuit arrangement 1216. The GPS circuit arrangement 1216 can communicate with a satellite-based system and receive a location data for the electrical device 1200, as is known in the art.

[0091] The electrical device 1200 can include any other output device 1210 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other output device 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for delivering information to other devices, or an additional storage device.

[0092] The electrical device 1200 can include any other input device 1220 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other input device 1220 can include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick-response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0093] The electrical device 1200 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), an electrical desktop device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or an electrical wearable device. In some examples, the electrical device 1200 can be any other electronic device that processes data.

[0094] “Containing” and “comprising” (and all forms and tenses thereof) are used here as open terms. It is therefore understood that whenever a claim uses any form of “containing” or “comprising” (e.g., encompasses, includes, encompassing, incorporating, exhibiting, etc.) as a preamble or within any kind of claim recitation, additional elements, expressions, etc., may be present without falling outside the scope of protection of the claim or recitation in question. As used here, when the expression “at least” is used as the transitional phrase in, for example, a claim preamble, it is open in the same way as the terms “comprising” and “containing” are open.The term "and / or," when used in a form such as A, B and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used here in the context of describing structures, components, items, objects, and / or things, the expression "at least one of A and B" refers to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used here in the context of describing structures, components, items, objects, and / or things, the expression "at least one of A or B" refers to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.As used here in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" refers to implementations that include any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used here in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A or B" refers to implementations that include any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0095] As used here, singular references (e.g., "a," "an," "first," "second," etc.) do not preclude plurals. The term "a" object, as used here, refers to one or more of these objects. The terms "a," "a or more," and "at least one" are used interchangeably here. Furthermore, although not listed individually, multiple means, elements, or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, they may potentially be combined, and inclusion in different examples or claims does not indicate that a combination of features is not feasible and / or advantageous.

[0096] As used here, the term "above," unless otherwise specified, describes the relationship of two parts relative to the Earth. A first part is above a second part if the second part has at least one part between the Earth and the first part. Likewise, as used here, a first part is "below" a second part if the first part is closer to the Earth than the second part. As noted above, a first part may be above or below a second part with one or more of the following: other parts in between, without other parts in between, with the first and second parts in contact, or without the first and second parts in direct contact with each other.

[0097] Notwithstanding the foregoing, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and / or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” does not refer to the ground, but instead refers to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Accordingly, as used herein, and unless otherwise specified or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die if, during fabrication / manufacturing, the first component is further supported by a substrate (e.g., a substrate, a substrate, or a support) on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided.a semiconductor wafer) than the second component on which the two components are fabricated or otherwise provided. Unless otherwise specified or implied from the context, a first component within an IC package (e.g., a semiconductor die) is likewise considered to be “above” a second component within the IC package during fabrication if the first component is farther away from a printed circuit board (PCB) on which the IC package is to be mounted or attached. It is understood that semiconductor devices are frequently used in a different orientation than when they were fabricated. Accordingly, when reference is made to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and / or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e.,, the term “above” describes the relationship of two parts relative to the earth) probably based on the context of use.

[0098] As used in this patent, the statement that any part (e.g., a layer, a film, a region, an area, or a plate) is located on another part in any way (e.g., positioned, located on, arranged on, or formed on, etc.) indicates that said part is either in contact with the other part or that said part is located above the other part with one or more intervening part(s) between them.

[0099] As used here, connection references (e.g., attached, coupled, connected, and joined) can include intermediate elements between the elements referenced by the connection reference and / or relative movement between those elements, unless otherwise specified. Therefore, connection references do not necessarily imply that two elements are directly connected and / or in a fixed relationship to each other. As used here, the statement that any part is in "contact" with another part is defined as meaning that there is no intermediate element between the two parts.

[0100] Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used here without implying or otherwise indicating any significance of priority, physical order, arrangement in a list, and / or order in any way, but are used merely as labels and / or arbitrary names to distinguish elements for the ease of understanding the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element in a claim may be referred to by a different descriptor such as "second" or "third."In such cases, it is understood that such descriptors are used only to uniquely identify those elements within the context of the discussion (for example, within a claim), where the elements might otherwise share the same name.

[0101] As used here, "approximately" and "about" modify their meanings / values ​​to acknowledge the potential presence of variations that occur in real-world applications. For example, "approximately" and "about" can modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections, as an average person would understand. For example, "approximately" and "about" can indicate dimensions that may fall within a tolerance range of + / - 10%, unless otherwise specified here.

[0102] As used here, "essentially real-time" refers to a near-instantaneous occurrence, acknowledging that real-world delays for computing time, transmission, etc., may exist. Accordingly, unless otherwise specified, "essentially real-time" refers to real-time + / - 1 second.

[0103] As used here, the phrase “in communication”, including variations thereof, includes direct communication and / or indirect communication through one or more intermediaries and does not require direct physical (e.g., wired) communication and / or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals and / or one-off events.

[0104] As used here, the term “programmable circuit arrangement” is defined as including: (i) one or more specialized electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform one or more specific operations and incorporating one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general-purpose semiconductor-based electrical circuits programmable with instructions to perform one or more specific functions and / or operations and incorporating one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of a programmable circuit arrangement include programmable microprocessors, such as central processing units (CPUs).that can execute first instructions to perform one or more operations and / or functions, field-programmable gate arrays (FPGAs) that can be programmed with second instructions to configure and / or structure the FPGAs to instantiate one or more operations and / or functions according to the first instructions, graphics processing units (GPUs) that can execute first instructions to perform one or more operations and / or functions, digital signal processors (DSPs) that can execute first instructions to perform one or more operations and / or functions, XPUs, network processing units (NPUs), one or more microcontrollers that can execute first instructions to perform one or more operations and / or functions,and / or integrated circuits such as application-specific integrated circuits (ASICs). An XPU can, for example, be implemented by a heterogeneous computer system comprising several types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or a combination thereof) and an orchestration technology (e.g., application programming interfaces (APIs)) that can distribute computational tasks to each of the different types of programmable circuitry that are suitable and available for performing the computational tasks.

[0105] As used here, an integrated circuit / circuit assembly is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more by an ASIC, an FPGA, a chip, a microchip, a programmable logic assembly, a semiconductor substrate coupling multiple circuit elements, a system-on-chip (SoC), etc.

[0106] From the foregoing, it is understood that exemplary systems, devices, manufactured articles, and processes have been disclosed that incorporate glass cores with increased durability and reduce (e.g., minimize, etc.) the risk of Seware defects. Examples disclosed herein include glass cores with TGVs protruding from the top of the glass core. Examples disclosed herein reduce the probability of stress concentration sites, associated with the lateral stacking of materials with different coefficients of thermal expansion, forming at the entrance of glass vias. Examples disclosed herein prevent the deposition of buffer material within the vias, thereby reducing the thermal stress to which the glass core of housing substrates is subjected and the probability of Seware defects occurring.

[0107] Further examples and combinations thereof include the following: Example 1 includes a substrate for an integrated circuit package, wherein the substrate comprises: a glass core incorporating a surface, and a copper-glass via (TGV) extending through the glass core, the TGV extending above the surface of the glass core. Example 2 includes the substrate from a previous example, which includes a buffer layer on the surface, with the buffer layer surrounding a projection of the TGV above the surface. Example 3 includes the substrate from a previous example, where the surface is a first surface and the buffer layer includes a second surface that is complementary to the first surface. Example 4 includes the substrate from a previous example, where the TGV and the projection are integral. Example 5 includes the substrate from a previous example, wherein the TGV is a first TGV and the substrate includes a second TGV, wherein the glass core has a second region between the first TGV and the second TGV, and wherein the first region and second region are essentially coplanar. Example 6 includes the substrate from a previous example, wherein the TGV is a first TGV and the substrate includes a second TGV, wherein the glass core has a second region between the first TGV and the second TGV, and wherein the second region has a curved shape. Example 7 includes the substrate from a previous example, where the curved shape is concave. Example 8 includes a device comprising: a semiconductor die, and a housing substrate for supporting the semiconductor die, wherein the housing substrate comprises: a glass core having a curved surface, and a copper-glass via (TGV) extending through the glass core, the TGV extending out of the curved surface. Example 9 includes the device from a previous example, which includes a buffer layer on the curved surface, wherein the buffer layer surrounds a projection of the TGV above the curved surface. Example 10 includes the device from a previous example, wherein the projection has a length parallel to a thickness of the glass core, the length being between 5% and 20% of the thickness of the glass core. Example 11 includes the device from a previous example, which further includes a build-up layer that includes an intermediate connection that is electrically coupled to the TGV, wherein the buffer layer is located between the glass core and the build-up layer. Example 12 includes the device from a previous example, wherein the curved surface is a first curved surface, the projection is a first projection, the glass core further includes a second curved surface opposite the first curved surface, and the TGV includes a second projection extending from the second curved surface. Example 13 includes the device from a previous example, wherein the curved surface is concave. Example 14 includes the device from a previous example, wherein the curved surface is meniscus-shaped. Example 15 includes a device comprising: a semiconductor die, and a housing substrate for supporting the semiconductor die, wherein the housing substrate comprises: a glass core including an outer surface, and a build-up layer above the glass core, wherein the build-up layer includes an intermediate that is electrically coupled to the semiconductor die, and a copper-glass via (TGV) in a through-hole of the glass core, wherein the TGV includes an end that protrudes above the outer surface, the end being electrically coupled to the intermediate. Example 16 includes the setup from a previous example, which further includes a buffer layer between the build-up layer and the glass core, wherein the buffer layer is intended to at least partially surround the end. Example 17 includes the setup from a previous example, wherein the glass core has a first thickness adjacent to the TGV and a second thickness distal to the TGV, the first thickness being greater than the second thickness. Example 18 includes the setup from a previous example, where the outer surface is essentially planar. Example 19 includes the setup from a previous example, wherein the outer surface is a first outer surface, the end is a first end, the glass core includes a second outer surface opposite the first outer surface, and the TGV includes a second end extending from the second outer surface. Example 20 includes the setup from a previous example, with the TGV in contact with the glass core adjacent to the outer surface. Example 21 includes a method that involves: creating a hole in a glass core of a housing substrate, plating a glass through-hole (GOH) in the hole of the housing substrate, and processing the GOH and / or the glass core so that the GOH includes a projection extending from the glass core. Example 22 includes the procedure from a previous example, wherein the processing of the TGV and / or the glass core includes plasma dry etching of the glass core and wet etching of the glass core. Example 23 includes the procedure from a previous example, wherein wet etching involves applying sulfuric acid to the glass core. Example 24 includes the procedure from a previous example, wherein processing the TGV and / or the glass core involves performing a two-stage polishing process. Example 25 includes the procedure from a previous example, wherein performing a two-stage polishing process includes: polishing the glass core with a copper slurry, and polishing the glass core with a silicon dioxide slurry. Example 26 includes the method from a previous example, which further includes the deposition of a buffer layer on the glass core, wherein the projection extends into the buffer layer.

[0108] The following claims are hereby incorporated into this detailed description by reference. Although certain exemplary systems, devices, articles, and processes have been disclosed herein, the scope of protection of this patent is not limited thereto. Rather, this patent covers all systems, devices, articles, and processes that reasonably fall within the scope of protection of the claims of this patent.

Claims

[1] Substrate for an integrated circuit package, wherein the substrate comprises: a glass core that includes a surface; and a copper-glass through-hole (TGV) extending through the glass core, with the TGV extending above the surface of the glass core. [2] Substrate according to claim 1, comprising a buffer layer on the surface, wherein the buffer layer surrounds a projection of the TGV above the surface. [3] Substrate according to claim 2, wherein the surface is a first surface and the buffer layer includes a second surface which is complementary to the first surface. [4] Substrate according to one of claims 2-3, wherein the TGV and the projection are integral. [5] Substrate according to any one of claims 1-4, wherein the TGV is a first TGV and the substrate includes a second TGV and a third TGV, wherein the glass core has a first region between the first TGV and the second TGV, wherein the glass core has a second region between the second TGV and the third TGV and the first region and the second region are substantially coplanar. [6] Substrate according to one of claims 1-4, wherein the TGV is a first TGV and the substrate includes a second TGV, wherein the glass core has a second region between the first TGV and the TGV and wherein the second region has a curved shape. [7] Substrate according to claim 6, wherein the curved shape is concave. [8] Device comprising the following: a semiconductor die; and a housing substrate for supporting the semiconductor die, wherein the housing substrate comprises the following: a glass core that includes a curved surface; and a copper-glass through-hole (TGV) extending through the glass core, with the TGV extending out of the curved surface. [9] Device according to claim 8, comprising a buffer layer on the curved surface, wherein the buffer layer surrounds a projection of the TGV above the curved surface. [10] Device according to claim 9, wherein the projection has a length parallel to a thickness of the glass core, the length being between 5% and 20% of the thickness of the glass core. [11] Device according to one of claims 9-10, which further includes a build-up layer comprising an intermediate connection which is electrically coupled to the TGV, wherein the buffer layer is located between the glass core and the build-up layer. [12] Device according to one of claims 9-11, wherein the curved surface is a first curved surface, the projection is a first projection, the glass core further comprises a second curved surface opposite the first curved surface, and the TGV comprises a second projection extending from the second curved surface. [13] Device according to one of claims 8-12, wherein the curved surface is concave. [14] Device according to claim 13, wherein the curved surface is meniscus-shaped. [15] Institution comprising the following: a semiconductor die; and a housing substrate for supporting the semiconductor die, wherein the housing substrate comprises the following: a glass core that includes an outer surface; and A build-up layer above the glass core, wherein the build-up layer includes an intermediate that is electrically coupled to the semiconductor die; and a copper-glass via (TGV) in a through hole of the glass core, wherein the TGV includes an end that protrudes above the outer surface, the end being electrically coupled to the intermediate connection. [16] Device according to claim 15, which further includes a buffer layer between the build-up layer and the glass core, wherein the buffer layer is to at least partially surround the end. [17] Device according to one of claims 15-16, wherein the glass core has a first thickness adjacent to the TGV and a second thickness distal to the TGV, wherein the first thickness is greater than the second thickness. [18] Device according to claim 17, wherein the outer surface is substantially planar. [19] Device according to one of claims 15-18, wherein the outer surface is a first outer surface, the end is a first end, the glass core includes a second outer surface opposite the first outer surface and the TGV includes a second end that protrudes from the second outer surface. [20] Device according to one of claims 15-19, wherein the TGV is in contact with the glass core adjacent to the outer surface. [21] Method which includes the following: Creating a hole in the glass core of a housing substrate; Plating a glass through-hole (TGV) in the hole of the package substrate; and Processing the TGV and / or the glass core so that the TGV includes a projection extending from the glass core. [22] Method according to claim 21, wherein the processing of the TGV and / or the glass core includes plasma dry etching of the glass core and wet etching of the glass core. [23] Method according to claim 22, wherein the wet etching involves applying sulfuric acid to the glass core. [24] Method according to claim 21, wherein the processing of the TGV and / or the glass core includes performing a two-stage polishing process comprising: Polishing the glass core with a copper slurry; and Polishing the glass core with a silicon dioxide slurry. [25] Method according to one of claims 21-24, further comprising depositing a buffer layer on the glass core, wherein the projection extends into the buffer layer.

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