LOCAL REGISTRATION SCHEME FOR INTERSECTION TARRAYS

Abstract

Technology for reading programmable resistive memory cells in a cross-point array. Module-specific voltage offsets are used to compensate for differences between capture amplifiers, thereby improving read accuracy. The memory system comprises banks, each containing a number of modules. Each module includes a capture amplifier and a cross-point array with programmable resistive memory cells. A bank controller outputs a digital code to each module in the bank, where the digital code specifies a base value for a reference voltage. Each module can modify the digital code with a module-specific voltage offset. The module then generates a module-specific analog reference voltage, which is provided to the capture amplifier to compensate for variations between the capture amplifiers in different modules.

Description

BACKGROUND Memory is widely used in various electronic devices, such as mobile phones, digital cameras, PDAs, medical electronics, portable computing devices, stationary computing devices, and data servers. Memory can be either non-volatile or volatile. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (such as a battery). Some memory arrays are arranged in a crossover configuration, with word lines perpendicular to bit lines and memory cells located at the intersections of the bit and word lines. Such arrays may be called crossover arrays or crossbar arrays. Programmable resistive memory cells can be used in a crossover array. An example of programmable resistive memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, unlike some other memory technologies that use electronic charges for data storage. In general, MRAM comprises a large number of magnetic memory cells formed on a semiconductor substrate, with each memory cell representing (at least) one data bit.A data bit is written to a memory cell by changing the magnetization direction of a magnetic element within the memory cell, and a bit is read by measuring the resistance of the memory cell (a low resistance typically represents a "0" bit and a high resistance typically represents a "1" bit). In the sense used here, the magnetization direction is the direction in which the magnetic moment is aligned. Read circuits can be used to read data from programmable resistive memory cells. Acquisition amplifiers can be provided to perform the acquisition. Data can be read by sensing current or voltage at a sensing node while current flows through a selected programmable resistive memory cell. As an example, current is passed through the programmable resistive memory cell to generate a voltage at a sensing node. The sensing node voltage is fed into the sensing amplifier, which compares the sensing node voltage to a reference voltage. The resistance difference between the low-resistance and high-resistance states of a programmable resistive memory cell can be relatively small. Therefore, the voltage difference across the memory cell for the low-resistance and high-resistance states can also be relatively small. For example, with a typical read current flowing through the memory cell, the difference between the low-resistance and high-resistance states might be only about 200 millivolts. Furthermore, a few transistors may be placed between the memory cell and the sensing amplifier, which can reduce the voltage variation between the low-resistance and high-resistance states. Additionally, variations between sensing amplifiers can occur due to factors such as limitations in the semiconductor manufacturing process. The above factors make the accurate measurement of programmable resistive memory cells a technical challenge. In this context, the disclosures of US 2006 / 0221712 A1, DE 10 2008 009 880 A1, US 2016 / 0093393 A1 and US 2022 / 0263667 A1 may be helpful for understanding the present invention. US Patent 2006 / 0221712 A1 discloses the use of a voltage derived from accessing a selected bit using an initial read current to read a selected bit of an untriggered phase-change memory after the read current has been changed. This allows the use of different reference voltages to detect the state of selected cells with higher resistance versus those with lower resistance. The resulting read window or read margin can be improved in some embodiments. German patent DE 10 2008 009 880 A1 relates to a storage device comprising a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicating whether an error correction mode should be used. Access to the portion of the memory that stores the parity information is blocked when the error correction mode is enabled. US 2016 / 0093393 A1 relates to a flash memory device with a physically non-clonable function (PUF) and a corresponding method.More specifically, the flash memory device comprises a flash memory unit, which includes a main memory area and a peripheral memory area; a challenge input unit, which receives a challenge value; a read voltage setting unit, which sets a read voltage based on the input challenge value; a data read unit, which reads data by applying the read voltage to a memory cell located in a predefined memory area of ​​the peripheral memory area each time a challenge value is input; and a response output unit, which outputs the read data as a response value corresponding to the challenge value, the predefined memory area consisting of a plurality of memory cells, each comprising two or more memory cells with different threshold voltages. Finally, US 2022 / 0263667 A1 relates to an embodiment of a device comprising a memory and a processor. The memory is designed to store trim and redundancy information of an integrated circuit (IC). The processor is designed to extract bits from the IC trim and redundancy information, apply a hash function to the extracted bits to generate hashed bits, and output the hashed bits in response to one or more criteria being met by their statistical properties. In some embodiments, the memory storing the IC trim and redundancy information may be distinct from other memory used by the device for further operations (e.g., accessing user data and program data written to system memory). BRIEF DESCRIPTION OF THE DRAWING Elements with the same number refer to common components in the various figures. Fig. 1A shows an embodiment of a host-connected memory system. Fig. 1B shows an embodiment of memory core control circuitry. Fig. 2A shows an embodiment of a memory die having a number of banks. Fig. 2B shows an embodiment of a bank having a number of modules. Fig. 2C shows an embodiment of a module. Fig. 3 is a block diagram of an embodiment of a memory die. Fig. 4 shows an alternative arrangement to that of Fig. 3, which can be implemented using wafer-to-wafer bonding to provide a bonded die pair for the integrated memory arrangement. Fig. 5 shows an example of a capture amplifier. Fig. 6 shows an example of a memory access (read) operation.Figure 7A shows an embodiment of part of a memory array forming a crossover architecture in an oblique view. Figures 7B and 7C show a side view and a top view, respectively, of the crossover structure in Figure 7A. Figure 7D shows an embodiment of part of a two-stage memory array forming a crossover architecture in an oblique view. Figure 8 illustrates an embodiment of the structure of an MRAM memory cell. Figure 9A schematically shows an example of reading a programmable resistive memory cell that includes an MRAM cell connected in series with a selector. Figure 9B illustrates voltage distributions that can be compared by a comparator of the acquisition amplifier in an acquisition operation. Figures 10A and 10B show examples of an acquisition operation directed at a programmable resistive memory cell.Figure 11 represents an embodiment of a detection amplifier that can provide module-dependent compensation. Figure 12 represents an embodiment of the module-dependent reference voltage source. Figure 13 is a flowchart of an embodiment of a process for generating a module-specific reference voltage for a detection amplifier. Figure 14 is a flowchart of an embodiment of a process for performing a module-specific adjustment of a detection voltage for a detection amplifier. Figure 15 is a flowchart of an embodiment of a process for reading a programmable resistive memory cell based on a module-specific voltage adjustment for a detection amplifier. Figure 16 is a flowchart of an embodiment of a process for reading a programmable resistive memory cell based on a module-specific voltage adjustment for a detection amplifier. DETAILED DESCRIPTION The present invention relates to a device according to claim 1, a method according to claim 9 and a storage system according to claim 12. Advantageous embodiments may include features of pending claims. Accordingly, a technology for reading programmable resistive memory cells in a crosspoint array is disclosed. With programmable resistive memory cells in a crosspoint array, the read margin can be very small. In one embodiment, module-specific voltage offsets are used to compensate for differences between sensing amplifiers and thereby improve the read accuracy. In another embodiment, the memory system is divided into banks, each bank having a number of modules. Each module has a sensing amplifier and a crosspoint array with programmable resistive memory cells. Each sensing amplifier can have a comparator having a first input that receives a sensing voltage based on the sensing of a selected memory cell in the crosspoint array, and a second input that receives a reference voltage.The comparator outputs a state of the selected memory cell based on a comparison of the sensing voltage with the reference voltage. Typically, there are some variations between transistors in the comparators from module to module (and also from bank to bank). To compensate for such variations, each module can access a module-specific voltage offset and adjust at least one of the reference or sensing voltages based on this module-specific offset. In one embodiment, a bank controller outputs a digital code to each module in the bank, where the digital code specifies a base value for a reference voltage. Each module can modify the digital code with a module-specific voltage offset.The module then generates a module-specific analog reference voltage, which is provided to the comparator in the acquisition amplifier to compensate for variations between the acquisition amplifiers in different modules. This improves the read accuracy for programmable resistive memory cells. Fig. 1A shows an embodiment of a memory system 100 connected to a host 106. The memory system 100 can implement the memory cell sensing technology presented herein. Many different types of memory systems can be used with the technology proposed here. Exemplary memory systems include memory cards, including dual in-line memory modules (DIMMs) as DRAM replacements, solid-state drives (“SSDs”), and embedded storage devices; however, other types of memory systems can also be used. The memory system 100 is connected to a host 106 (e.g., a PC or a mobile computing device). The memory system 100 includes a memory chip controller 105 and a memory chip 102 (also referred to as a “memory die”). The term “device” herein may include, but is not limited to, the memory system 100 or the memory chip (or die) 102.The memory chip controller 105 may include one or more state machines, page registers, SRAMs, or other control logic for controlling the operation of the memory chip 102. The one or more state machines, page registers, SRAMs, and / or other control logic for controlling the operation of the memory chip may be referred to as management or control circuits for enabling one or more memory array operations, including setting, resetting, erasing, programming (or writing), or reading operations. The memory chip controller can receive data and instructions from the host 106 and provides memory chip data to the host 106. In one embodiment, the memory chip controller 105 and the memory chip 102 can be arranged on a single integrated circuit. In other embodiments, the memory chip controller 105 and the memory chip 102 can be arranged on separate integrated circuits. The memory chip 102 includes memory core control circuits 104 and a memory core 103. The memory core control circuits 104 can include logic for controlling the selection of memory blocks (or arrays) within the memory core 103, for controlling the generation of voltage references to bias a particular memory array into a read or write state, or for generating row and column addresses. The memory core 103 can include one or more two-dimensional arrays of memory cells or one or more three-dimensional arrays of memory cells.In one embodiment, the memory core control circuits 104 and the memory core 103 are arranged on a single integrated circuit. In other embodiments, the memory core control circuits 104 and the memory core 103 are arranged on different integrated circuits. The controller 105 communicates with the host 106 via an interface that implements a protocol such as a JEDEC standard interface with double the data rate or low power consumption at double the data rate (DDR or LPDDR), such as DDR5 or LPDDR5. Other interfaces, such as NVM Express (NVMe) or Compute Express Link (CXL) over PCI Express (PCIe), can be used. The host 106 is located outside of and separate from the storage system 100. In one embodiment, the storage system 100 is embedded within the host 106. Referring to Fig. 1A, a storage system operation can be initiated when the host 106 sends instructions to the memory chip controller 105 indicating that it wants to read data from or write data to the storage system 100. In the case of a write (or program) operation, the host 106 sends both a write command and the data to be written to the memory chip controller 105. The data to be written can be buffered by the memory chip controller 105, and error correction code (ECC) data can be generated according to the data to be written. The ECC data, which enables the detection and / or correction of data errors that occur during transmission or storage, can be written to the memory core 103 or stored in non-volatile memory within the memory chip controller 105.In one embodiment, the ECC data is generated, and data errors are corrected by switching logic within the memory chip controller 105. As soon as a read or write operation is initiated by the memory chip controller 105, the memory core control circuits 104 can generate the appropriate bias voltages (and / or currents) for word lines and bit lines within the memory core 103, as well as the appropriate memory block, row, and column addresses. Fig. 1B shows an embodiment of the memory core control circuits 104. As shown, the memory core control circuits 104 include address decoders 170, signal generators for selected control lines 172, voltage generators for unselected control lines 174, and detection amplifiers 176. The signal generators for selected control lines 172 can include voltage generators and / or current generators. In some embodiments, memory cells are read and / or written by passing a current through the memory cells. In some embodiments, memory cells are read and / or written by applying a voltage across the memory cells. Control lines can include word lines, bit lines, or a combination of word lines and bit lines.Selected control lines can include selected word lines or selected bit lines used to put memory cells into a selected state. Unselected control lines can include unselected word lines or unselected bit lines used to put memory cells into an unselected state. The signal generators (or signal regulators) for the selected control lines 172 can include one or more voltage generators for generating selected control line voltages and / or one or more current generators for generating selected control line currents. The voltage generators for the unselected control lines 174 can include one or more voltage generators for generating unselected control line voltages.The address decoders 170 can generate memory block addresses as well as row and column addresses for a specific memory block. The detection amplifiers 176 can compare a detected signal from a memory cell with a reference signal to determine the state of the memory cell. In one embodiment, a detection amplifier 176 determines whether a memory cell is in a high-resistance (HRS) or low-resistance (LRS) state. In one embodiment, while a current is passed through the memory cell, the voltage across the memory cell is detected and compared with a reference voltage. In another embodiment, while a voltage is applied across the memory cell, the current through the memory cell is detected and compared with a reference current. In one embodiment, a memory die is divided into a hierarchy of banks, modules, and tiles. Fig. 2A shows an embodiment of a memory die 102 having a number of banks 202. Each bank 202 can contain memory cells and control logic, including a bank controller. The memory cells can be programmable resistive memory cells in crosspoint arrays. There can be additional control logic 204 outside the banks. In this example, there are 16 banks per memory die, but there can also be more or fewer than 16 banks per memory die. As another example, there are 32 banks for a memory die. In one embodiment, each bank 202 includes a number of modules. Fig. 2B shows an embodiment of a bank 202 comprising a bank controller 220 and a number of modules 210. There are n columns of modules 210 and m rows of modules 210. For example, n can be 8, where there can be eight columns of modules 210. For example, m can be 16, where there can be 16 rows of modules. Other elements, such as bit line drivers, word line drivers, and buffers, are not shown in Fig. 2B. Each module 210 has a memory array 502 comprising programmable resistive memory cells and control switching logic, including a sensing amplifier 176. The memory array can be a cross-point array. There can be significant variations in the control switching logic across the different modules 210, which can affect read accuracy. For example, there can be differences between the sensing amplifiers 176. Such differences can arise due to limitations in the semiconductor manufacturing process. For example, transistor characteristics, such as the threshold voltage, can vary depending on their position within the bank 202. Typically, there are also bank-to-bank variations between the sensing amplifiers. During the initial testing of the memory system, the modules 210 can be characterized to determine a module-specific offset voltage for each module 210. The module-specific offset voltage is used during reading to compensate for differences between the acquisition amplifiers 176. The module-specific offset voltage can be stored in a module-specific code storage device 582. The module-specific code storage device 582 is a digital storage medium, such as a flip-flop. The digital storage medium used for the module-specific code storage device 582 can be non-volatile or volatile. Examples of digital storage media include flip-flops, registers, data latches, RAM, ROM, EEPROM, or other storage technologies, or any other medium that can be used to store digital information.A digital storage medium or digital storage media does not contain any widespread, modulated, or transitory signals. The module-specific offset voltage can be a digital code. In one embodiment, the module-specific code storage 582 is a volatile memory that is written upon power-up. However, the module-specific code storage 582 can also be a non-volatile memory. The bank controller 220 controls all of the modules 210 in the bank. In one embodiment, the bank controller 220 sends the same digital trim code, which specifies a base value for the acquisition amplifiers 176 to be used as a reference voltage, to all modules 210. The digital trim code could, for example, be a four-bit code. It should be noted that this digital trim code may depend on factors such as the current temperature and the position of the memory cells selected for reading within the arrays. However, in one embodiment, each module 210 receives the same digital trim code for the current read operation, which is performed in parallel in the modules 210. Each module 210 can modify this digital code based on a digital code stored in the module-specific code storage 582.Module 210 can then generate an analog reference voltage, which is to be used as an input to the acquisition amplifier 176. In particular, the analog reference voltage can be used as an input for a comparator in the acquisition amplifier 176. Therefore, each module 210 is capable of generating a module-specific reference voltage to compensate for differences between the acquisition amplifiers 176. Fig. 2C shows further details of an embodiment of a module 210. The module 210 contains a bitline decoder 230 and a wordline decoder 240. In this example, the bitline decoders 230 are divided into four groups. Each group of bitline decoders 230 can, for example, contain 1000 bitline decoders. Similarly, the wordline decoders 240 are divided into four groups. Each group of wordline decoders 240 can, for example, contain 1000 wordline decoders. Thus, for example, there are 4000 bitline decoders 230 and 4000 wordline decoders 240 in the module 210. Each bitline decoder is connected to a bitline via a bitline connection (bitline connection areas 232 are shown). Each word line decoder is connected to a word line via a word line connection (word line connection areas 242 are shown).Figure 2C shows an example word line (WL) and an example bit line (BL). However, there can be thousands of word lines and thousands of bit lines per module 210. Figure 2C shows an example position for the acquisition amplifier 176 and the module-specific code storage 582. The acquisition amplifier 176 and the module-specific code storage 582 can also be located elsewhere in the module 210. Figure 3 is a block diagram illustrating an example of a memory system 500 that can implement the technology described here. The memory system 500 includes a memory array 502, which can contain any of the memory cells described below. The array connection lines of the memory array 502 include the (different) layer(s) of word lines, which are organized as rows, and the (different) layer(s) of bit lines, which are organized as columns. However, other orientations can also be implemented. The memory system 500 includes a row control circuit 520, which is connected to the respective word lines of the memory array 502 via the lines 508.The line control switching logic 520 receives line address signals and one or more different control signal(s) from a system control logic 560 and can usually include circuits such as line decoders 522 and word line drivers (WL drivers) 524 for read and write operations. The memory system 500 also includes a column control circuit 510, whose inputs / outputs 506 are connected to the respective bit lines of the memory array 502. Although only a single block is shown for the memory array 502, a memory die can contain multiple arrays or "tiles" that can be accessed individually. The column control circuit 510 receives column address signals and one or more different control signals from the system control logic 560 and can typically include circuits such as column decoders 512, bit line drivers (BL drivers) 514, and read / write circuits (R / W circuits) 516, which may include, for example, acquisition amplifiers for reading. The system control logic 560 receives data and commands from a host and provides output data and status to the host. In other embodiments, the system control logic 560 receives data and commands from a separate control circuit and provides output data to this control circuit, which communicates with the host. In some embodiments, the system control logic 560 can include a state machine that enables die-level control of memory operations. In one embodiment, the state machine is software-programmable. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuits). In another embodiment, the state machine is replaced by a microcontroller, which is located on or off the memory die.The system control logic 560 may also include a power control module that controls the power and voltages supplied to the rows and columns of the memory array 502 during memory operations, and may include charge pumps and a control circuit for generating control voltages. The system control logic 560 may include one or more state machines, registers, and other control logic for controlling the operation of the memory system 500. In some embodiments, all elements of the storage system 500, including the system control logic 560, can be formed as part of a single die. In other embodiments, part or all of the system control logic 560 can be formed on a different die. For the purposes of this document, the term “one or more control circuit(s)” may include a controller, a state machine, a microcontroller and / or other control switching logic such as that represented by the System Control Logic 560 and / or other analog circuits used to control programmable resistive memories. In one embodiment, the memory structure 502 comprises a three-dimensional memory array of programmable resistive memory cells in which multiple memory layers are formed on a single substrate, such as a wafer. The memory structure can include any type of programmable resistive memory that is monolithically formed in one or more physical layers of memory cells and has an active region arranged on a silicon substrate (or another type of substrate). In another embodiment, the memory structure 502 comprises a two-dimensional memory array of programmable resistive memory cells. The exact type of memory array architecture or memory cell contained in Memory Structure 502 is not limited to a specific example. Many different types of memory array architectures or memory technologies can be used to form Memory Structure 502. Examples of suitable technologies for Memory Cells in Memory Structure 502 include ReRAM (Resistive Random Access Memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, Phase Change Memory (e.g., PCM), and the like. Examples of suitable technologies for Memory Cell Architectures in Memory Structure 502 include two-dimensional arrays, three-dimensional arrays, intersection point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like. An example of programmable resistive memory is magnetoresistive random-access memory (MRAM), which stores data using magnetic storage elements. These elements consist of two ferromagnetic layers, each capable of holding a magnetization, separated by a thin insulating layer. One of the layers is a permanent magnet with a specific polarity; the magnetization of the other layer can be changed to match that of an external field to store data. A memory device is constructed from a grid of such memory cells. In one programming embodiment, each memory cell is positioned between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below it. When current flows through them, an induced magnetic field is created.MRAM-based memory implementations are explained in more detail below. Phase-change memory (PCM) devices can also be used. PCMs exploit the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve non-thermal phase changes simply by altering the coordination state of the germanium atoms with a programming current pulse. It should be noted that the use of the term "pulse" in this document does not refer to a rectangular pulse, but includes any (continuous or discontinuous) oscillation or burst of sound, current, voltage, light, or other wave. The memory elements within each selectable memory cell or bit may include another serial element that is a selector, such as an ovonic threshold switch or a metal insulator substrate. Another example of a programmable resistive memory is ReRAM. ReRAM can be used in a crosspoint memory arranged in crosspoint arrays accessed via X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells can include conductive bridge memory elements. A conductive bridge memory element can also be called a programmable metallization cell. A conductive bridge memory element can be used as a state-change element based on the physical displacement of ions within a solid electrolyte. In some cases, a conductive bridge memory element can include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes.As the temperature increases, so does the mobility of the ions, which lowers the programming threshold for the conductive bridge memory cell. Therefore, the conductive bridge memory element can exhibit a wide range of programming thresholds depending on the temperature. A person skilled in the art will recognize that the technology described here is not limited to a single specific storage structure, storage design or material composition, but covers many relevant storage structures within the meaning and scope of the technology described here and as understood by a person skilled in the art. The elements of Fig. 3 can be grouped into two parts: the memory structure 502 (including the memory cells) and the peripheral switching logic, including all other elements. An important property of a memory circuit is its capacity, which can be increased by enlarging the area of ​​the memory die of the memory system 500 available to the memory structure 502. However, this reduces the area of ​​the memory die available for the peripheral switching logic. This can lead to significant limitations of these peripheral elements. For example, the need to fit sensing amplifier circuits within the available area can be a significant constraint on the sensing amplifier design architecture. With respect to the system control logic 560, reduced area availability can limit the functionalities that can be implemented on the chip.Consequently, a fundamental compromise in the design of a memory die for the memory system 500 is how much area should be allocated to the memory structure 502 and how much area to the peripheral switching logic. Another area where conflicts often arise between the 502 memory structure and the peripheral switching logic is the processing associated with the formation of these regions, since these regions often involve different processing technologies, and the trade-off is having different technologies on a single die. For example, if the memory structure (502) is a NAND flash, it is an NMOS structure, while the peripheral switching logic is often based on CMOS. For instance, PMOS devices are frequently used in elements such as sensing amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral switching logic within the system control logic (560). The processing operations for manufacturing a CMOS die differ in many aspects from the processing operations optimized for NMOS flash memory or other memory cell technologies. To overcome these limitations, the embodiments described below can distribute the elements from Fig. 3 onto separately formed dies, which are then connected by bonding. More precisely, the memory structure 502 can be formed on one die, and some or all of the peripheral circuit elements, including one or more control circuits, can be formed on a separate die. For example, a memory die can consist solely of the memory elements, such as the array of memory cells of a flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or another type of memory. Some or all of the peripheral circuitry, even elements such as decoders and acquisition amplifiers, can then be moved to a separate die. This allows each memory die to be individually optimized according to its technology.For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about the CMOS elements, which are now moved to a separate die for peripheral circuitry that can be optimized for CMOS processing. This frees up more space for the peripheral elements, which can now integrate additional functions that could not be easily integrated if they were confined to the edges of the same die holding the memory cell array. The two dies can then be bonded together in a bonded multi-die memory circuit, connecting the array on one die to the peripheral elements on the other memory circuit.Although the following focuses on a bonded memory circuit consisting of one memory die and one die for peripheral circuits, other embodiments may use more dies, such as two memory dies and one die for the peripheral circuits. Fig. 4 shows an alternative arrangement to that in Fig. 3, which can be implemented by wafer-to-wafer bonding to provide a bonded die pair for the integrated memory assembly 600. Fig. 4 shows an example of the peripheral switching logic, including control circuits, formed in a peripheral circuit or control die 611, which is coupled to the memory structure 602 formed in the memory die 601. As with 502 in Fig. 3, the memory die 601 can include several independently accessible arrays or “tiles.” Common components are labeled similarly to Fig. 3 (e.g., 502 is now 602, 510 is now 610, etc.). It is evident that the system control logic 660, the row control circuit 620 and the column control circuit 610 (which can be formed by a CMOS process) are located in the control die 611.Additional elements, such as functionalities from the 105 controller, can also be moved to the 611 control die. The 660 system control logic, the 620 row control switching logic, and the 610 column control switching logic can be formed by a common process (e.g., a CMOS process), so that adding elements and functionalities that are typically found on a 105 memory controller may require few or no additional process steps (i.e., the same process steps used to manufacture the 105 controller can also be used to manufacture the 660 system control logic, the 620 row control switching logic, and the 610 column control switching logic). While moving such circuitry from a die, such as the memory die of the Memory System 500, may reduce the number of steps required to manufacture such a die, adding such circuitry to a die, such as the Control Die 611, may not require any additional process steps. Fig. 4 shows the column control circuit 610 on the control die 611, which is connected via electrical paths 606 to the memory structure 602 on the memory die 601. For example, the electrical paths 606 can provide an electrical connection between the column decoder 612, the driver circuit 614, the R / W circuits 616, and the bit lines of the memory structure 602. Electrical paths can run from the column control circuit 610 in the control die 611 through pads on the control die 611 that are bonded to corresponding pads of the memory die 601, which in turn are connected to bit lines of the memory structure 602. Each bit line of the memory structure 602 can have a corresponding electrical path in the electrical paths 606, including a pair of bonded pads connected to the column control circuit 610. Likewise, the row control switching logic 620, including the row decoder 622 and the word line drivers (WL drivers) 624, is coupled to the memory structure 602 via electrical paths 608.Each electrical path 608 can correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 611 and the memory die 601. In comparison to Fig. 3, the on-die control circuits of Fig. 4 can include additional functionalities within their logic elements, both more general capabilities than are usually found in the memory controller 105, as well as some CPU capabilities, but also application-specific features. The following may include the system control logic 560 / 660, the column control switching logic 510 / 610, the row control switching logic 520 / 620, and / or the controller 105 (or circuits with equivalent function), in combination with all or a subset of the other circuits shown in Fig. 3 or on the control die 611 in Fig. 4, as part of the one or more control circuits that perform the functions described herein. The control circuits may include hardware only or a combination of hardware and software (including firmware). An example of a control circuit is a controller programmed by firmware to perform the functions described herein. A control circuit may include a processor, FPGA, ASIC, integrated circuit, or another type of circuit. In the following explanation, the memory array 502 / 602 of Figures 3 and 4 is primarily discussed in the context of a crosspoint architecture, although much of the explanation can also be applied more generally. The following discussion focuses mainly on embodiments based on a crosspoint architecture using MRAM memory cells, although much of the discussion can be applied more generally to programmable resistor memory cells. Fig. 5 shows an example of a capture amplifier 176 (e.g., in the read / write circuits 516 or 616). Fig. 5 shows a capture node 572 that can be connected to a selected programmable resistive memory cell (e.g., via a selected bit line that can be chosen by the column decoder 512 or 612). A current mirror 574, connected to a supply voltage VNN, controls the current through the selected programmable resistive memory cell during capture. The capture amplifier 176 includes a comparator 576 that has a first input (e.g., a non-inverting input) which receives a voltage from the capture node 572 and compares it to a reference voltage (VRef.) received at a second input (e.g., an inverting input) from a module-dependent reference voltage source 578.For example, the comparator 576 can generate a digital output (logic 1 or 0) depending on whether the voltage at the sensing node 572 is above or below the reference voltage. The digital output from the comparator 576 is temporarily stored in the data latch 580 and output as acquisition data. The acquisition amplifier 176 also features a module offset memory 582, which can be used to store an offset specific to the module in which the acquisition amplifier is located. This offset can be provided to the module-dependent reference voltage source 578, which generates the VRef. based on a trim code and the module offset. The trim code can be a digital code provided by the bank controller 220. In one embodiment, the bank controller 220 provides the same trim code to each module in the bank. However, the value of this trim code can vary depending on factors such as the temperature and the position of the selected memory cell within the intersection point array. The module-specific VRef. can be used to compensate for differences between the acquisition amplifiers 176. For example, input transistors in the comparators 576 may have different threshold voltages. Fig. 6 illustrates a read operation directed at a selected memory cell 680 located at the intersection of the selected word line 682 and the selected bit line 684 (e.g., in structure 502 / 602). The word line drivers 542 generate a first supply voltage VPP (e.g., a positive voltage), which is then applied to the selected word line 682 by the row decoder 522. The column decoder 512 selects the selected bit line 684 and connects it to the capture node 572, where the voltage is captured by the capture amplifier 176, while current flows through the current mirror, which receives a second supply voltage VNN (e.g., a negative voltage) from the bit line drivers 514. The detection amplifier 176 can detect the state of the selected memory cell 680 based on the voltage at the detection node 572, while a predetermined current flows from the current mirror 574 through the selected memory cell 680.Fig. 7A shows an embodiment of part of a memory array forming a cross-point architecture in an oblique view. The memory array 502 / 602 from Fig. 7A is an example of an implementation of the memory array 502 in Fig. 3 or Fig. 602 in Fig. 4, wherein a memory die can contain several such array structures. The bit lines BL1-BL5 are arranged in a first direction (e.g., "bit line direction," shown as extending into the side) relative to an underlying substrate (not shown) of the die, and the word lines WL1-WL5 are arranged in a second direction (e.g., "word line direction") perpendicular to the first direction (across the side).Figure 7A is an example of a horizontal crossover point structure in which word lines WL1-WL5 and BL1-BL5 both run horizontally relative to the substrate, while the memory cells, two of which are shown at Figure 701, are oriented such that current flows vertically through a memory cell (as shown at 1Cell). In a memory array with additional layers of memory cells, as explained below with reference to Figure 7D, there would be corresponding additional layers of bit lines and word lines. As shown in Fig. 7A, the memory array 502 / 602 includes a plurality of memory cells 701. The memory cells 701 can include rewritable memory cells, such as those that can be implemented using ReRAM, MRAM, PCM, FeRAM, or other materials with programmable resistance. The current in the memory cells of the first memory level is shown as flowing upwards, as indicated by the arrow 1Cell, but the current can flow in both directions, as will be explained in more detail below. Figures 7B and 7C show a side view and a top view, respectively, of the intersection point structure in Figure 7A. The side view in Figure 7B shows a lower wire, or word line, WL1, and the upper wires, or bit lines, BL1-BLn. At the intersection point between each upper and lower wire is an MRAM memory cell, although PCM, FeRAM, ReRAM, or other technologies could also be used. Figure 7C is a top view illustrating the intersection point structure for M lower wires WL1-WLM and N upper wires BL1-BLN. In a binary embodiment, the MRAM cell at each intersection point can be programmed to one of two resistance states: high and low. Further details of embodiments for an MRAM memory cell design and techniques for programming them are given below. The intersection point array of Fig. 7A illustrates an embodiment with a single layer (floor) of word lines and bit lines, where the MRAM or other memory cells are located at the intersection of the two sets of lines. To increase the storage density of a memory die, multiple layers (floors) of such memory cells and conductive lines can be formed. A two-layer (two-story) example is illustrated in Fig. 7D. Fig. 7D shows an embodiment of part of a two-level (two-story) memory array, which, in an oblique view, forms a crossover architecture. As in Fig. 7A, Fig. 7D shows a first layer 718 (first story) of memory cells 701 of an array 502 / 602, which are connected at the crossover points of the first layer by word lines WL1,1-WL1,4 and bit lines BL1-BL5. A second layer (second story) of memory cells 720 is formed above the bit lines BL1-BL5 and between these bit lines and a second set of word lines WL2,1-WL2,4. Although Fig. 7D shows two layers (story) 718 and 720 of memory cells, the structure can be extended upwards by additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array from Fig.7D can be biased for read or programming operations, so that the current flows in each layer from the word line layer to the bit line layer or vice versa. The use of an intersection point architecture enables arrays with a small footprint, and multiple such arrays can be formed on a single die. The memory cells formed at each intersection point can be resistance-type memory cells, in which data values ​​are encoded as different resistance levels. Depending on the embodiment, the memory cells can be binary and exhibit either a low- or high-resistance state, or they can be multi-level cells (MLCs) that may have an additional resistance level between the low- and high-resistance states. Fig. 8 illustrates one embodiment of the structure of an MRAM memory cell. The memory cell includes a lower electrode 801, a threshold switching selector 820, a pair of magnetic layers (reference layer 803 and free layer 807) separated by a separating or tunneling layer of magnesium oxide (MgO) 805 in this example, and then an upper electrode 811 separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetizations of the reference layer 803 and the free layer 807: when the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low-resistance (LRS) state; and when they have the opposite orientation, the memory cell is in an antiparallel (AP) high-resistance (HRS) state.An MLC implementation would include additional intermediate states. The orientation of the reference layer 803 is fixed and, in the example shown in Fig. 8, is oriented upwards. The reference layer 803 is also referred to as the fixed layer or solid layer. Data is written to an MRAM memory cell by programming the free layer 807 to have either the same or the opposite orientation. The reference layer 803 is designed to maintain its orientation when the free layer 807 is programmed. The reference layer 803 may have a more complex structure, including synthetic antiferromagnetic layers and additional reference layers. For simplicity, these additional layers are omitted from the figures and explanation, and the focus is solely on the solid magnetic layer, which is primarily responsible for the tunnel magnetoresistance in the cell. In one embodiment, each memory cell has a threshold switching selector 820 in series with the programmable resistive element. A threshold switching selector 820 has a high resistance (in the off or non-conducting state) when it is biased to a voltage lower than its threshold voltage, and a low resistance (in the on or conducting state) when it is biased to a voltage higher than its threshold voltage. The threshold switching selector 820 remains on until its current is reduced below a holding current or its voltage is reduced below a holding voltage. When this occurs, the threshold switching selector 820 returns to the off state. To program a memory cell at a crossover point, a voltage or current is applied accordingly.which is sufficient to turn on the associated threshold switching selector 820 and set or reset the memory cell; and to read a memory cell, the threshold switching selector 820 must likewise be activated by turning it on before the resistance state of the memory cell can be determined. A set of examples of a threshold switching selector 820 is an ovonic threshold switching material of an ovonic threshold switch (OTS). To read data from or write data to an MRAM memory cell, a current must be passed through the memory cell. In embodiments in which a threshold switching selector 820 is placed in series with the MRAM device, the threshold switching selector 820 must be turned on before the current can flow through the MRAM device by applying a sufficient voltage across the series combination of the threshold switching selector and the MRAM device.Fig. 9A schematically shows an example of reading a programmable resistive memory cell 920, which includes an MRAM cell 922 connected in series with a selector 924. The MRAM cell 922 is schematically represented as two resistors with resistance values ​​RP and RAP, corresponding to the resistance of the MRAM cell 922 in the parallel and antiparallel states, respectively. A constant current, Iread, is maintained through the MRAM cell 922 during a read operation (e.g., by a current mirror such as the current mirror 574), so that VMRAM can have two different values ​​depending on whether the MRAM cell 922 is in the parallel or antiparallel state (e.g., VMRAM = Iread * RP or VMRAM = Iread * RAP). The selector 924 is schematically represented as a voltage source which, in the ON state (e.g. as soon as a threshold voltage is exceeded), provides a constant voltage difference VOffset.The detection amplifier 176 is connected to the detection voltage at the detection node 572 (e.g. the voltage is different depending on the resistance of the MRAM cell 922 and the resulting voltage VMRAM). Fig. 9B illustrates voltage distributions that can be compared by a comparator of the acquisition amplifier 176 (e.g., comparator 576) during an acquisition process. A first voltage distribution labeled "P" (e.g., at acquisition node 572) corresponds to MRAM cells in the parallel or "P" state. A second voltage distribution labeled "AP" corresponds to MRAM cells in the antiparallel or "AP" state. A reference voltage VRef. (e.g., from VRef. source 578) lies between these distributions. By comparing the voltage at acquisition node 572 with the reference voltage VRef., the state of an MRAM cell can be determined (e.g., a detected voltage < VRef. indicates the P state, and a detected voltage > VRef. indicates the AP state). Fig. 10A shows an example of a read operation directed at a programmable resistive memory cell. A positive voltage VPP is applied to the selected programmable resistive memory cell 1082 via switch 1080 and a selected bit line (e.g., bit line 1110, schematically shown as RBL). A selected word line (e.g., word line 1120, schematically shown as RWL) connects the selected programmable resistive memory cell 1082 to a negative voltage VNN via switch 1084. A detection amplifier 176 is connected to the detection node 572 between the selected bit line and the current mirror 574. The voltage at the detection node 572, designated VErf., is input to the comparator 576 in the detection amplifier 176. A reference voltage VRef. is also input to the comparator 576 in the detection amplifier 176. The comparator 576 compares VErf. with VRef.and outputs a signal that indicates a physical state of the selected memory cell. Fig. 10B shows another example of a read operation directed at a programmable resistive memory cell. A positive voltage VPP is connected to the selected programmable resistive memory cell 1072 via switch 1070 and a selected word line (schematically shown as RWL). A selected bit line (schematically shown as RBL) connects the selected programmable resistive memory cell 1072 to a negative voltage VNN via switch 1074. A detection amplifier 176 is connected to the detection node 572 between the selected word line and the current mirror 574. The voltage at the detection node 572, designated VErf., is input to the comparator 576 in the detection amplifier 176. A reference voltage VRef. is also input to the comparator 576 in the detection amplifier 176. The comparator 576 compares VErf. with VRef.and outputs a signal that indicates a physical state of the selected memory cell. Regardless of the direction of the read current, there are technical challenges in accurately reading the memory cell. When reading some MRAM cells, the difference between the P-state and the AP-state may be only about 200 mV. However, there are decoder transistors in the read path that can further reduce the voltage difference between the P-state and the AP-state. For example, the difference between the P-state and the AP-state may be only about 100 mV at VErf. Furthermore, the threshold voltages of the input transistors in the comparators 576 in the acquisition amplifiers 176 typically vary from one acquisition amplifier to the next. Therefore, accurately acquiring programmable resistive memory cells, such as MRAM, is a technical challenge. In one embodiment, each module has at least one detection amplifier 176. Typically, there are variations between the detection amplifiers from module to module. In one embodiment, each module applies a module-specific offset to compensate for such differences between the detection amplifiers. Fig. 11 shows an embodiment of a detection amplifier 176 that can provide module-dependent compensation. The detection amplifier 176 has a comparator 576, as discussed previously. The detection amplifier 176 also has a module offset memory 582, which can be used to store an offset specific to the module in which the detection amplifier is located. This offset can be provided to the module-dependent reference voltage source 578, which generates VRef. based on a trim code and the module offset.The trim code can be a digital code provided by the bank controller 220. In one embodiment, the bank controller 220 provides the same trim code to each module 210 in the bank. However, the value of this trim code can vary depending on factors such as the temperature and position of the selected memory cell within the intersection point array. In another embodiment, the module-dependent reference voltage source 578 modifies the trim code based on the module offset and then generates a VRef based on the modified trim code. Therefore, each module 210 in the bank 202 is able to generate a VRef specific to that module 210. The module-specific VRef can be used to compensate for differences between the sensing amplifiers 176, such as differences in the threshold voltages of transistors within the comparators 576. Fig. 12 shows an embodiment of the module-dependent reference voltage source 578. The module-dependent reference voltage source 578 has a switched capacitor network 1202 and a set of booster capacitors 1204. Only two of the capacitors (C5, C6) of the switched capacitor network 1202 are shown, but more capacitors may be present. C5 receives an input voltage VEin when switch S0 is closed and switch S1 is open. S0 can then be opened to temporarily store VEin in C5. Switch S1 is closed (with S0 and S2 open) to divide the charge between C5 and C6 according to their relative capacitances. Additional capacitors and switches may be present in the switched capacitor network 1202 to allow coarse trimming of VEin. Switch S2 can be closed (with S1 open) to share the charge with the booster capacitors 1204.Once S2 is open, the booster capacitors 1204 are used to increase the voltage to reach the final VRef. In this example, there are four booster capacitors: C1, C2, C3, and C4. However, there may be more or fewer than four booster capacitors. The relative capacitances of the booster capacitors C1, C2, C3, and C4 are selected to achieve the desired gain for each capacitor. Fine-tuning can be used for module-specific adjustments to VRef. The module-specific code storage 582 stores the module-specific code. In this example, the module-specific code is a four-bit digital code. The bank code, which can be provided by the bank controller 220, is also a four-bit digital code. The adaptation switching logic 1210 inputs the bank code and the module-specific code and either adds the module-specific code to the bank code or subtracts the module-specific code from the bank code. In one embodiment, the adaptation switching logic 1210 includes an adder, a subtractor, and switching logic that selects whether the adder or the subtractor should be used. The output of the 1210 matching logic circuit is a four-bit digital code, with one bit allocated to each of the 1206-1, 1206-2, 1206-3, and 1206-4 inverters. Each 1206 inverter is connected to one of the booster capacitors.Fig. 13 is a flowchart of an embodiment of a process 1300 for generating a module-specific reference voltage for a detection amplifier. The process 1300 is discussed with respect to the switching logic in Fig. 12; however, the process 1300 is not limited to this switching logic. Step 1302 includes accessing a module-specific digital code from the module-specific code storage 582 in the module 210. Step 1304 includes receiving a bank-specific digital trim code from the bank controller 220. Step 1306 includes modifying the bank-specific digital trim code with the module-specific digital code. Step 1306 may include an adder in the matching switching logic 1210, which adds the module-specific code to the bank-specific digital trim code.Step 1306 may include a subtractor in the matching logic 1210, which subtracts the module-specific digital code from the bank-specific digital trim code. The matching logic 1210 then outputs the modified digital code to the inverters 1206. Step 1308 includes generating the module-specific VRef. based on the modified digital code. Step 1308 may include using voltages output by the inverters 1206 to modify the voltages across the booster capacitors 1204. Note that prior to step 1308, the switched capacitor network 1202 may be used to perform a rough matching to VEin. Step 1310 includes inputting the module-specific analog VRef. into a comparator 576 in the sensing amplifier 176.Step 1310 may include transferring a voltage from the upper plates of the booster capacitors 1204 to the reference input of the comparator 576. In some embodiments, the module-specific offset is used to modify the reference voltage VRef. provided to the comparator 576 in the sensing amplifier 176. In another embodiment, the module-specific offset is used to modify the sensing voltage VErf. provided to the comparator 576 in the sensing amplifier 176. Fig. 14 is a flowchart of an embodiment of a process 1400 for performing a module-specific adjustment of a sensing voltage for a sensing amplifier 176. Step 1402 involves accessing a module-specific digital code from the module offset memory 582 in the module. The module-specific digital code specifies how much the sensing voltage should be adjusted (up or down). Step 1404 involves modifying the sensing voltage VErf. based on the module-specific digital code.Step 1404 can include accessing VErf. from the acquisition node 572 and increasing or decreasing VErf. based on the module-specific digital code. Step 1406 includes inputting the modified acquisition voltage into the comparator 576 in the acquisition amplifier 176. A reference voltage VRef. is also provided to the comparator 576 in the acquisition amplifier 176. In this example, the reference voltage VRef. does not need to be module-specific. Fig. 15 is a flowchart of an embodiment of a process 1500 for reading a programmable resistive memory cell based on a module-specific voltage matching for a sensing amplifier. Step 1502 involves passing a read current through the selected programmable resistive memory cell. In one embodiment, Iread is passed through the memory cell (see, for example, Fig. 10A, Fig. 10B). Step 1504 involves sensing a voltage in response to the passed current. In one embodiment, Vreq (at the sensing node 572) is provided to a first input of the comparator 576 in the sensing amplifier 176. Step 1506 involves inputting the module-specific VRef. into a second input of the comparator 576 in the acquisition amplifier 176. The module-specific VRef. can be generated as described with reference to Figures 11 and / or 12. The comparator 576 then compares VErf. with VRef. and provides an output based on the comparison. Step 1508 involves storing the output of the comparator 576 in a data latch 580. Fig. 16 is a flowchart of an embodiment of a process 1600 for reading a programmable resistive memory cell based on a module-specific voltage adjustment for a sensing amplifier 176. Step 1602 includes passing a read current through the selected programmable resistive memory cell. In one embodiment, Iread is passed through the memory cell (see, for example, Fig. 10A, Fig. 10B). Step 1604 includes inputting a modified sensing voltage into a first input of the comparator 576 in the sensing amplifier 176. Step 1604 may include performing the process in Fig. 14 to modify VRef. Step 1606 includes inputting VRef into a second input of the comparator 576 in the sensing amplifier 176. The comparator 576 then compares VRef with VRef and provides an output based on the comparison.Step 1608 includes storing the output of comparator 576 in a data latch 580. According to a first set of aspects, a device comprises a bank, which in turn includes a variety of modules. Each module includes a sense amplifier and a crosspoint array. The crosspoint array contains a variety of programmable resistive memory cells. The sense amplifier of each module is configured to receive a sense voltage at its first input, based on the detection of a selected memory cell in the module's crosspoint array. The sense amplifier of each module is configured to receive a reference voltage at its second input. The sense amplifier of each module is configured to output a state of the selected memory cell based on a comparison of the sense voltage with the reference voltage.Each module in the bank is configured to access a module-specific voltage offset and to adjust at least one of the reference voltages or the sensing voltages based on the module-specific voltage offset. In another aspect, each module is configured to adjust the reference voltage input to the module's detection amplifier based on the module-specific voltage offset. In another aspect, each module is configured to adjust the detection voltage input into the module's detection amplifier based on the module-specific voltage offset. In another aspect, each module includes a digital storage medium. And each module is configured to access the module-specific voltage offset from the digital storage medium. In another aspect, the setup also includes a bank controller configured to output a digital code to each module in the bank, specifying a base reference voltage value. Each module is configured to generate the reference voltage for its respective sensing amplifier based on this base reference voltage value and the module-specific voltage offset. In another aspect, each module includes an adder / subtractor circuit configured to add or subtract the module-specific voltage offset from the digital code. In another aspect, the bank is the first of many banks within the facility. And the digital code sent by the bank controller to the many modules of the first bank is a reference voltage specific to that first bank. In another aspect, the module-specific voltage offset of each respective module is independent of the position of the selected memory cell within the intersection point array of the respective module. In another aspect, each programmable resistive memory cell comprises a magnetoresistive direct access memory cell (MRAM cell) in series with a threshold switching selector. One embodiment includes a method for detecting a programmable resistive memory cell. The method comprises sending a digital bank code, specifying a base reference voltage, to each module in a bank comprising a plurality of modules. Each module comprises a detection amplifier and a crosspoint array comprising a plurality of programmable resistive memory cells. The method includes detecting a selected programmable resistive memory cell in the crosspoint array of the respective module at each module in the bank.For each module, the acquisition includes: accessing a module-specific digital code from a digital storage medium within the module; modifying the digital bank code based on the module-specific digital code to form a module-specific digital reference voltage code; generating a module-specific analog reference voltage based on the module-specific digital reference voltage code; and acquiring a state of the selected programmable resistor memory cell in the intersection array based on the module-specific analog reference voltage. One embodiment includes a storage system comprising a plurality of banks. Each bank comprises a plurality of modules and a bank controller. Each module includes a capture amplifier and a crosspoint array. The crosspoint array has a plurality of programmable resistive memory cells. The bank controller is configured to output a bank-specific digital code to each of the plurality of modules in the bank. The bank-specific digital code specifies a base value for a reference voltage for the capture amplifiers in the bank for a read operation of selected memory cells in the bank. Each module comprises a digital storage medium and one or more control circuits. The one or more control circuits are configured to access a module-specific digital code from the digital storage medium.The one or more control circuits are configured to modify the bank-specific digital code received from the bank controller, based on the module-specific digital code, to generate a modified digital code. The one or more control circuits are configured to generate a module-specific reference voltage based on the modified digital code. The one or more control circuits are configured to detect the state of the selected memory cell in the intersection array of the respective module, based on the module-specific reference voltage. For the purposes of this document, references to “one embodiment”, “an embodiment”, “some embodiments” or “another embodiment” may be used in the patent specification to describe different embodiments or the same embodiment. For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases where an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intermediary elements. When an element is described as being directly connected to another element, there are no intermediary elements between that element and the other element. Two devices are "in communication" when they are connected, directly or indirectly, in such a way that they can communicate electronic signals with each other. In this document, the phrase "at least one of A or B" means only A, only B, or both A and B. In this document, the phrase "adjust at least one of the reference voltage or the sensing voltage based on the module-specific voltage offset" includes one or more of: adjusting only the reference voltage based on the module-specific voltage offset, adjusting only the sensing voltage based on the module-specific voltage offset, or adjusting both the reference voltage and the sensing voltage based on the module-specific voltage offset. For the purposes of this document, the term “based on” may be read as “at least partially based on”. For the purposes of this document, the use of numerical terms such as "first" object, "second" object, and "third" object without additional context may not indicate the order of the objects, but may instead be used for identification purposes to identify different objects. Within the context of this document, the term "set" of objects can refer to a "set" of one or more objects. The foregoing detailed description serves for illustration and explanation purposes. It makes no claim to completeness, nor is it intended to be limited to the exact form disclosed. In light of the above teaching, many modifications and variations are possible. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling other skilled persons to make optimal use of it in various embodiments and with various modifications, as appropriate for their respective intended uses. The scope of protection is to be defined by the accompanying claims.

Claims

Device (100, 102), comprising: a bank (202), comprising a plurality of modules (210), each module (210) comprising a detection amplifier (176) and a crosspoint array (502), the crosspoint array (502) comprising a plurality of programmable resistive memory cells (701), the detection amplifier (176) of each respective module (210) being configured to: receive a detection voltage (VErf) based on the detection of a selected memory cell (701) in the crosspoint array (502) of the module (210) at a first input of the detection amplifier (176); receive a reference voltage (VRef) at a second input of the detection amplifier (176); and output a state of the selected memory cell (701) based on a comparison of the detection voltage (VErf) with the reference voltage (VRef);and wherein each respective module (210) in the bank (202) is configured to: access a module-specific voltage offset and adjust at least one of the reference voltage (VRef) or the sensing voltage (VErf) based on the module-specific voltage offset, characterized in that the device (100, 102) further comprises a bank controller (220) configured to output a digital code to each module (210) in the bank (202) specifying a base value of the reference voltage (VRef), wherein each respective module (210) is configured to generate the reference voltage (VRef) for the sensing amplifier (176) of the respective module (210) based on the base value of the reference voltage (VRef) and the module-specific voltage offset, and wherein each module (210) comprises an adder / subtractor circuit (1210) configured to add the module-specific voltage offset to the digital code or to subtract from it.; Device (100, 102) according to claim 1, wherein each respective module (210) is configured to adjust the reference voltage (VRef) input into the detection amplifier (176) of the module (210) based on the module-specific voltage offset. Device (100, 102) according to claim 1, wherein each respective module (210) is configured to adjust the detection voltage (VErf) input into the detection amplifier (176) of the module (210) based on the module-specific voltage offset. Device (100, 102) according to claim 1, wherein: each module (210) comprises a digital storage medium (582) and each module (210) is configured to access the module-specific voltage offset from the digital storage medium (582). Device (100, 102) according to claim 4, further comprising one or more control circuit(s) configured to store the module-specific voltage offset for the respective module (210) in the digital storage medium (582) of the respective module (2109). Device (100, 102) according to claim 1, wherein: the bank (202) is a first bank of a plurality of banks in the device (100, 102) and the digital code sent by the bank controller (220) to the plurality of modules (210) of the first bank (202) is a reference voltage specific to the first bank (202). Device (100, 102) according to claim 1, wherein the module-specific voltage offset of each respective module (210) is independent of the position of the selected memory cell (701) within the intersection point array (502) of the respective module (210). Device (100, 102) according to claim 1, wherein each programmable resistive memory cell comprises a magnetoresistive direct access memory cell (MRAM cell) (922) in series with a threshold switching selector (820, 924). Method for acquiring a programmable resistive memory cell, the method comprising: sending a digital bank code specifying a base reference voltage to each module (210) in a bank (202) comprising a plurality of modules (210), each module (210) comprising an acquiring amplifier (176) and a crosspoint array (502) comprising a plurality of programmable resistive memory cells (701); and acquiring a selected programmable resistive memory cell (701) in the crosspoint array (502) of the respective module (210) at each respective module (210) in the bank (202), including for each respective module (210): accessing a module-specific digital code from a digital storage medium (582) within the module (210); modifying the digital bank code based on the module-specific digital code to form a module-specific digital reference voltage code;Generating a module-specific analog reference voltage (VRef) based on the module-specific digital reference voltage code and acquiring a state of the selected programmable resistor memory cell (701) in the intersection point array (502) based on the module-specific analog reference voltage, characterized in that modifying the digital bank code based on the module-specific digital code to form a module-specific digital reference voltage code includes: adding the module-specific digital reference voltage code to the digital bank code or subtracting the module-specific digital reference voltage code from the digital bank code. Method according to claim 9, further comprising: Accessing each of the module-specific digital codes for the modules (210) of the bank (202) from the non-volatile storage and writing the module-specific digital code being accessed to the digital storage medium (582) of each respective module (210) in the bank (202). The method of claim 9, wherein the detection of the state of the selected programmable resistive memory cell (701) in the intersection array (502) based on the module-specific analog reference voltage (VRef) includes: passing a read current through the selected programmable resistive memory cell (701); applying a detection voltage (VErf), resulting from passing the read current through the selected programmable resistive memory cell (701), to a first input of the detection amplifier (176) of the respective module (210); applying the module-specific analog reference voltage (VRef) to a second input of the detection amplifier (176) of the respective module (210); and outputting a comparison of the detection voltage (VErf) with the module-specific analog reference voltage (VRef) by the detection amplifier (176). Storage system (100) comprising: a plurality of banks (202), each bank (202) comprising: a plurality of modules (210), each module (210) comprising a capture amplifier (176) and a crosspoint array (502), the crosspoint array (502) comprising a plurality of programmable resistive memory cells (701); and a bank controller (220) configured to output a bank-specific digital code to each of the plurality of modules (210) in the bank (202), the bank-specific digital code specifying a base value for a reference voltage for the capture amplifiers (176) in the bank (202) for a read operation of selected memory cells in the bank (202); and wherein each respective module (210) comprises: a digital storage medium (582) and one or more control circuit(s) (1210) configured to: access a module-specific digital code from the digital storage medium (582);Modifying the bank-specific digital code received from the bank controller (220) based on the module-specific digital code to generate a modified digital code; generating a module-specific reference voltage (VRef) based on the modified digital code; and acquiring a state of the selected memory cell (701) in the intersection point array (502) of the respective module (210) based on the module-specific reference voltage (VRef), characterized in that each respective module (210) comprises an adder configured to selectively add the module-specific digital code to the bank-specific digital code received from the bank controller (220). Storage system (100) according to claim 12, wherein each respective module (210) further comprises a subtractor configured to selectively subtract the module-specific digital code from the bank-specific digital code received from the bank controller (220). Memory system (100) according to claim 12, wherein each programmable resistive memory cell comprises a magnetoresistive direct access memory cell (MRAM cell) (922) in series with a threshold switching selector (820, 924). Storage system (100) according to claim 12, wherein the bank controller (220) is further configured to write the module-specific digital code to the digital storage medium (582) of each respective module (210) in the bank (202).

Images