SYSTEM AND METHOD FOR EFFICIENT COMPRESSION OF NON-ALIGNED DATA

Abstract

A processing system comprises a memory and a processor configured to store multiple data elements with a bit width that is not a power of two across multiple registers with a bit width that is a power of two. The processor stores each bit of the data elements in separate registers, with the first bit stored in a first register, the second bit in a second register, and so on. Arithmetic operations are performed on corresponding bits across registers. The number of data elements corresponds to the register bit width. An arithmetic logic unit operates concurrently on the data elements using bits stored across registers. The system enables efficient storage and processing of low-precision values, optimizes cache utilization, and reduces wasted bits.This novel approach improves performance for applications such as artificial intelligence using narrow data types.

Images