DISPLAY DEVICE

Abstract

A display device (100, 200, 300, 400, 500) according to an exemplary embodiment of the present disclosure can comprise a substrate (111) having a display area (AA) and a non-display area (NA) on the outside of the display area (AA), an insulating layer (117) and a planarizing layer (115, 215) arranged above the substrate (111) and extending from the display area (AA) to the non-display area (NA), at least one trench (180, 280, 285) arranged in the non-display area (NA) and formed by removing at least one of the insulating layer (117) and the planarizing layer (115, 215), a dam (116, 216) arranged on the planarizing layer (115, 215) and extending to the non-display area (NA), an organic layer (132), which is located on the dam (116, 216), a cathode (133, 233, 433, 533) which extends to the organic layer (132),and a protective layer arranged on the cathode (133, 233, 433, 533), and a gate-in-panel (GIP) circuit part (108) arranged on a first side in the non-display area (NA) and positioned on the inside of the at least one trench (180, 280, 285), thereby minimizing a moisture permeation effect and improving the reliability of the display device (100, 200, 300, 400, 500).

Description

Area The present disclosure relates to a display device and in particular a display device that is capable of preventing the ingress of moisture. BACKGROUND In the current information age, the field of display devices that visually indicate electrical information signals is developing rapidly, and research is being conducted to develop features such as thinning, weight reduction, and low power consumption for various display devices. Representative display devices include a liquid crystal display (LCD), an electrowetting display (EWD), and an organic light-emitting display (OLED). Among these, an electroluminescent display device, which incorporates an organic light-emitting display element, is a self-emitting display device and, unlike a liquid crystal display device, does not require a separate light source. Therefore, it can be manufactured to be lightweight and thin. Furthermore, electroluminescent displays offer advantages due to their low-voltage drive, resulting in lower power consumption. They also provide superior color rendering, response time, viewing angle, and contrast ratio, making them suitable for a variety of applications. In an electroluminescent display device, a specific bezel clearance is essential to prevent moisture ingress and ensure reliability. However, the shadowed area resulting from the gap between the mask and the substrate during the deposition processes of the cathode and organic layer acts as a major factor limiting bezel reduction. Furthermore, reducing the bezel clearance significantly increases the likelihood of corrosion in the gate-in-panel (GIP) wiring due to moisture ingress, which can compromise reliability. OVERVIEW One problem to be solved by the present disclosure is to provide a display device that blocks moisture and oxygen while reducing a bezel width. Another problem to be solved by the present disclosure is to provide an indicator device capable of preventing corrosion of the wiring of a GIP circuit part. The tasks of this disclosure are not limited to those mentioned above, and other tasks not mentioned above can be clearly understood by the person skilled in the art from the following descriptions. According to aspects of this disclosure, display devices are provided in accordance with the independent claims. Further embodiments are described in the dependent claims. A display device according to an exemplary embodiment of the present disclosure may comprise a substrate having a display area and a non-display area on an outer surface of the display area, an insulating layer and a planarizing layer arranged on the substrate and extending from the display area to the non-display area, at least one trench arranged in the non-display area and formed by removing a portion of at least one of the insulating layer and the planarizing layer, a dam arranged on the planarizing layer and extending to the non-display area, an organic layer arranged on the dam, a cathode arranged on the organic layer and extending to the at least one trench, a protective layer arranged on the cathode, and a gate-in-panel (GIP) circuit component.which is located on a first page in the non-display area and is positioned on the inside of at least one trench. A display device according to a further exemplary embodiment of the present disclosure may comprise a substrate having a display area and a non-display area on an outside of the display area, at least one trench arranged in the non-display area, a first low-potential current line arranged in the trench, a cathode arranged in the display area such that it extends to the trench and is coupled to the first low-potential current line, a gate-in-panel circuit part arranged on a first side in the non-display area and positioned on the inside of the trench, and grounding wiring arranged on the first side and a third side in the non-display area on the outside of the trench. Further detailed details of the embodiments are included in the detailed description and drawings. In accordance with at least one embodiment of the present disclosure, a trench is formed in a shadowed area caused by the use of a separation mask, thereby enabling the edging width to be reduced and improving the reliability of moisture resistance. In accordance with at least one embodiment of the present disclosure, the GIP circuit part is arranged on the inside of the trench (in other words, inwards from the trench; in yet other words, inwards from the trench (i.e., on a side of the trench that is close to the display area, as opposed to a side of the trench that is farther from the display area); in yet other words, on a side of the trench that is closer to the display area; for example, between the trench and the display area), and the GIP circuit part is encapsulated by a cathode, thereby minimizing the effect of moisture ingress and improving the reliability of the display device. The effects according to the present disclosure are not limited to the contents illustrated above as examples, and various other effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS The above and further aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which: Fig. 1 is a top view of a display device according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view of a subpixel of the display device of Fig. 1. Fig. 3 is a view showing part of a cross-section of the display device of Fig. 1 corresponding to Ia-Ia'. Fig. 4 is a view showing part of a cross-section of the display device of Fig. 1 corresponding to Ib-Ib'. Fig. 5 is a view showing part of a cross-section of the display device of Fig. 1 corresponding to Ic-Ic'. Fig. 6 is a top view of a display device according to a second embodiment of the present disclosure.Figure 7 is a cross-sectional view along line IIa-IIa' of the display device of Figure 6. Figure 8 is a cross-sectional view along line IIb-IIb' of the display device of Figure 6. Figure 9 is a cross-sectional view of a display device according to a third embodiment of the present disclosure. Figure 10 is a cross-sectional view of a display device according to a fourth embodiment of the present disclosure. Figure 11 is a cross-sectional view of a display device according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EXECUTION FORM The advantages and properties of the present disclosure and a method for achieving these advantages and properties will become clear by reference to exemplary embodiments, which are described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that the person skilled in the art may fully understand the disclosures and the scope of the present disclosure. The shapes, sizes, ratios, angles, numbers, and the like shown in the accompanying drawings to describe exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited to them. Furthermore, a detailed explanation of known related technologies may be omitted from the following description of the present disclosure to avoid unnecessarily obscuring the subject matter of the present disclosure. The terms used herein, such as "containing," "with," and "featuring," are generally intended to permit the addition of further components, unless the terms are used with the term "only." Any references to the singular may include the plural unless expressly stated otherwise. Components are interpreted as having a normal error range, even if this is not explicitly stated. When the positional relationship between two parts is described using terms such as "on", "above", "below" and "next to", one or more parts may be positioned between the two parts unless the terms are used with the term "immediately" or "directly". If one element or layer is placed “on” another element or layer, another layer or element can be placed directly on top of the other element or in between. Although the terms "first," "second," and the like are used to describe different components, these components are not limited by these terms. These terms are merely used to distinguish one component from the others. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure. The same reference symbols generally denote the same elements throughout the entire revelation. The size and thickness of each component shown in the drawing are shown for the sake of simplicity of description, and the present disclosure is not limited to the size and thickness of the component shown. The features of different embodiments of the present disclosure can be partially or completely attached to one another or combined with one another, can interlock and be operated in technically different ways, and the embodiments can be carried out independently of one another or in combination with one another. Exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Fig. 1 is a top view of a display device according to a first embodiment of the present disclosure. Referring to Fig. 1, a display device 100 according to the first embodiment of the present disclosure can comprise a substrate 111, an encapsulation substrate 160 and pad parts 107 and 108. The display device 100 is a device for displaying an image to a user. The display device 100 can include a display element for showing images, a control element for controlling the display element, and wiring for transmitting various signals to the display element and the control element. The display element can be defined differently depending on the type of display device 100. For example, if the display device 100 is an organic light-emitting display device, the display element can be an organic light-emitting element comprising an anode, an organic emission layer, and a cathode. Similarly, if the display device 100 is a liquid crystal display device, the display element can be a liquid crystal display element. In the following, although the display device 100 is assumed to be the organic light-emitting display device, the display device 100 is not limited to the organic light-emitting display device. The display device 100 can have a display area AA and a non-display area NA. The AA display area is an area in which 100 images are displayed in the display device. Within the display area AA, a plurality of subpixels, which together form a plurality of pixels, and a circuit for driving the plurality of subpixels can be arranged. The plurality of subpixels are minimal units that constitute the display area AA, and a display element can be located within each of the plurality of subpixels, and the plurality of subpixels can form a pixel. For example, the organic light-emitting element, which has the anode, the organic emission layer, and the cathode, can be located within any of the plurality of subpixels, but is not limited to doing so. Furthermore, a circuit for driving the plurality of subpixels can include a drive element, wiring, and the like. For example, the circuit can be formed from a thin-film transistor, a storage capacitor, a gate line, a data line, or the like, but is not limited to these. The non-display area (NA) is an area where no image is displayed. Fig. 1 shows that the non-display area NA surrounds the display area AA, which has a rectangular shape. However, the shapes and arrangements of the display area AA and the non-display area NA are not limited to the example shown in Fig. 1. In other words, the display area AA and the non-display area NA can have shapes suitable for the design of an electronic device equipped with the display device 100. For example, an exemplary shape of the display area AA could be a pentagon, a hexagon, a circle, or an oval. The non-display area NA may contain various wiring and circuits for controlling the organic light-emitting element of the display area AA. For example, the non-display area NA may contain, but is not limited to, interconnect lines for transmitting signals to the majority of subpixels and circuits of the display area AA, control ICs such as gate driver ICs and data driver ICs, or pad parts 107 and 108. The display device 100 can include various additional elements for generating different signals or driving pixels in the display area AA. The additional elements for driving the pixels can include an inverter circuit, a multiplexer, an electrostatic discharge (ESD) circuit, and the like. The display device 100 can also include additional elements that perform functions other than pixel driving. For example, the display device 100 can include additional elements that provide a touch detection function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure detection function, a tactile feedback function, and the like. The aforementioned additional elements can be located in the non-display area NA and / or an external circuit connected to the interface. Pad parts 107 and 108 can be arranged to receive a signal from the outside. The pad parts 107 and 108 can be arranged in the non-display area NA of the display device 100 such that they are electrically connected to various wiring and circuit boards arranged in the display area AA. For example, pad parts 107 and 108 can function to transmit a signal to each of the gate line and the data line, and may include a gate pad part 108 for transmitting a gate signal to the gate line and a data pad part 107 for transmitting a data signal to the data line, but are not limited to this. The gate pad part 108 can be located on at least one side of the display device 100, for example in the non-display area NA on the first side of the display device 100, but is not limited to this. For example, the first side can mean a left and right side of the display device 100 that adjoin the top and bottom sides. The data pad portion 107 can be arranged on a different side of the display device 100, for example, in the non-display area NA on the second side of the display device 100, but is not limited to this. For example, the second side can be a top side of the display device 100. However, the present disclosure is not limited to this, and any of the first, second, third, and fourth sides of the non-display area NA can be designated as a respective side of the non-display area NA. For example, the data pad part 107 can be electrically connected to a data driver such that it supplies a data voltage to a plurality of data lines. The data driver can receive image data from the timing controller and supply a data voltage to the plurality of data lines to drive the plurality of data lines. The data driver can be implemented by having one or more integrated source driver circuits. For example, each integrated source driver circuit can include a shift register, a capture register circuit, a digital-to-analog converter (DAC), an output buffer, and the like. The data driver may also, in some cases, include one or more analog-to-digital converters (ADCs). The gate driver can control multiple gate lines by outputting a sampling signal to them. For example, the gate driver can control multiple gate lines sequentially by sequentially supplying sampling signals to them. Under timing control, the gate driver can sequentially supply an on-voltage sampling signal or an off-voltage sampling signal to multiple gate lines. The gate driver can have multiple gate drive circuits. These multiple gate drive circuits can correspond to a multiple gate lines. For example, each gate control circuit can include a shift register, a level shifter, and the like. Each gate drive circuit can be implemented in a gate-in-panel (GIP) type and embedded in the display device 100. For example, each gate drive circuit can be located directly on the gate pad part 108, and in this case the gate pad part 108 can be referred to as a GIP circuit part. In the display device 100 according to the first exemplary embodiment of the present disclosure, the trench 180 can be provided in the non-display area NA to ensure reliability, such as preventing the ingress of moisture. The trench 180 can be arranged in such a way that it surrounds the display area AA except for the second side, for example the top side, but is not limited to this. Furthermore, in the display device 100 according to the first exemplary embodiment of the present disclosure, the GIP circuit part (or the gate pad part) 108 is arranged on the inside of the trench 180 (in other words, inwards from the trench 180), so that it is arranged at a predetermined distance G from the trench 180, so that the effect of moisture penetration on the GIP circuit part 108 can be minimized, which will be described in detail with reference to Fig. 3, Fig. 4 to Fig. 5. Fig. 2 is a cross-sectional view of a subpixel of the display device of Fig. 1. Fig. 3 is a view showing part of a cross-section of the display device of Fig. 1 corresponding to Ia-Ia'. Fig. 4 is a view showing part of a cross-section of the display device of Fig. 1 corresponding to Ib-Ib'. Fig. 5 is a view showing part of a cross-section of the display device of Fig. 1 corresponding to Ic-Ic'. Fig. 3 shows part of the non-display area NA on the second side of the display device 100 of Fig. 1, and Fig. 4 shows part of the non-display area NA on the first side of the display device 100 of Fig. 1. Furthermore, Fig. 5 shows part of the non-display area NA on the third side of the display device 100 of Fig. 1. For example, the first page may refer to the left side of the display device 100, the second page may refer to the top side of the display device 100, and the third page may refer to the bottom side, which is on the side opposite the top side, but is not limited to this. For the sake of simplicity, Fig. 4 shows a schematic representation of the GIP circuit part 108 in the non-display area NA. In Fig. 3, Fig. 4 to Fig. 5, for the sake of simplicity of description, at least some of a buffer layer 112, a gate-insulating layer 113 and an intermediate insulating layer 114 are shown as insulating layers 117. Referring to Fig. 2, Fig. 3, Fig. 4 to Fig. 5, in the display device 100 of the first embodiment of the present disclosure the control element 120 can be arranged above the substrate 111. Furthermore, the planarization layer 115 can be arranged above the control element 120. Furthermore, the light-emitting element 130, which is electrically connected to the control element 120, can be arranged above the planarization layer 115, and the protective layer 140 can be arranged above the light-emitting element 130. The adhesive layer 165 and the encapsulation substrate 160 can be arranged sequentially over the protective layer 140. However, according to the first embodiment of the present disclosure, the display device 100 is not limited to this laminated structure. In this case, the trench 180 can be provided at an edge of the non-display area NA between the substrate 111 and the encapsulation substrate 160. Substrate 111 can be a glass or plastic substrate. In the case of a plastic substrate, a polyimide-based or polycarbonate-based material can be used, provided it exhibits flexibility. In particular, polyimide is a material that can withstand high-temperature processing and can be applied, making it widely used as a plastic substrate. A buffer layer 112 can be arranged on the substrate 111. In this context, although not shown, a light-shielding layer can be arranged on the substrate 111 to block light penetrating from a lower section of the substrate 111. A light-shielding layer can be arranged on the substrate 111 at a position where the active layer 124 is to be formed. In particular, it is preferred that the size of the light-shielding layer is somewhat larger so that the active layer 124 is completely covered. The buffer layer 112 can be arranged on the entire surface of the substrate 111 on which the light-shielding layer is formed. The buffer layer 112 is a layer for protecting various electrodes and wiring from impurities, such as alkali ions, released from the substrate 111 or the underlying layers. The buffer layer 112 can have a multilayer structure comprising a first buffer layer 112a and a second buffer layer 112b, but is not limited to this. For example, the buffer layer 112 can be made of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer of these materials. The buffer layer 112 can delay the diffusion of moisture and / or oxygen penetrating the substrate 111. Furthermore, the buffer layer 112 can include a multiple buffer and / or an active buffer. The active buffer protects the active layer 124, which is made from the semiconductor of the driver element 120, and can block various types of defects penetrating from the substrate 111. The active buffer can be made of amorphous silicon (a-Si) or the like. Various wiring and circuits for controlling the light-emitting element 130 of the display area AA can be arranged in the non-display area NA. For example, connecting lines for transmitting signals to the majority of subpixels and circuits of the display area AA, control ICs such as gate driver ICs and data driver ICs, or pad parts 107 and 108 can be arranged in the non-display area NA, but are not limited to these. For example, the grounding wiring GW can be located in the non-display area NA above the substrate 111. The grounding wiring GW can be located at one extreme edge of the non-display area NA, excluding the second side. The grounding wiring GW can be arranged adjacent to the edge of the encapsulation substrate 160. A first light-blocking structure PP1 can be arranged on the inside of the grounding wire GW. The first light-blocking structure PP1 can be arranged between the grounding wire GW and the trench 180. The connecting line LW can be located in the non-display area NA on the second side above the substrate 111. In the non-display area NA on the left and right sides, the GIP circuit part 108 can be arranged on the inside of the trench 180 (in other words, inwards from the trench 180). A detailed description of this will be provided later with reference to Fig. 4. The GIP circuit part 108 may include a control signal timing line CW, a logic unit LP, a buffer TFT unit B-TFT and a power line GVSS, but is not limited to these. For example, the control signal timing line CW, the logic unit LP, the buffer TFT unit B-TFT and the power line GVSS can be arranged successively from trench 180, but the present disclosure is not limited to this. In this case, the control signal timing line CW, the logic unit LP, the buffer TFT unit B-TFT and the power line GVSS can be made of a material that forms the light shielding layer and / or the drive element 120 of the display area AA, but are not limited to this. Furthermore, in the non-display area NA on the third and / or fourth side, where the GIP circuit part 108 and the data pad part 107 are not present, a second light-blocking structure PP2 and a high-potential current line EVDD may be arranged inside or on an inside of trench 180 (in other words, inwards from trench 180). For example, the second light-blocking structure PP2 and the high-potential power line EVDD can be arranged successively from trench 180, but the present disclosure is not limited to this. The second light-blocking structure PP2 and the high-potential current line EVDD can be formed from a material that forms the light-shielding layer and / or the control element 120 of the display area AA, however, the present disclosure is not limited to this. The control element 120 can comprise an active layer 124, a gate-insulating layer 113, a gate electrode 121, an intermediate insulating layer 114, a source electrode 122, and a drain electrode 123. Furthermore, the control element 120 can be electrically connected to the light-emitting element 130 via a connecting electrode 125 for the purpose of transmitting a current or a signal to the light-emitting element 130. In addition to the top-gate structure shown, the control element 120 can be implemented in various configurations, such as a bottom-gate structure in which the gate electrode is located below the active layer, and a coplanar structure in which the gate electrode, source electrode, and drain electrode are arranged on the same plane. The active layer 124 can be positioned on the buffer layer 112. The active layer 124 can be made of polysilicon (p-Si), in which case a predefined region can be doped with impurities. Furthermore, the active layer 124 can be made of amorphous silicon (a-Si) and can be made of an organic semiconductor material, such as pentacene. Finally, the active layer 124 can be formed from an oxide semiconductor. The gate-insulating layer 113 can be positioned on the active layer 124. For example, the gate-insulating layer 113 can be formed from an insulating inorganic material, such as silicon dioxide (SiOx) or silicon nitride (SiNx), or from an insulating organic material. The gate electrode 121 can be positioned on the gate insulating layer 113. For example, the gate electrode 121 can be made of various conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or an alloy thereof. The intermediate insulating layer 114 can be positioned on the gate electrode 121. For example, the intermediate insulating layer 114 can be formed from an insulating material, such as silicon oxide (SiOx) or silicon nitride (SiNx), or an insulating organic material. A contact hole, through which the source and drain regions are exposed, can be formed by selectively removing the gate insulating layer 113 and the intermediate insulating layer 114. The source electrode 122 and the drain electrode 123 can be formed using an electrode material in a single layer or a multilayer structure on the intermediate insulating layer 114. If necessary, an additional protective layer made of an inorganic insulating material can be formed in such a way that it covers the source electrode 122 and the drain electrode 123. In this case, at least some of the buffer layer 112, the gate-insulating layer 113 and the intermediate insulating layer 114, i.e. the insulating layer 117, can extend from the display area AA to the non-display area NA. The planarization layer 115 can be arranged above the control element 120, which is formed as described above. The planarization layer 115 can have a multi-layer structure comprising at least two layers. For example, with reference to Fig. 2, the planarization layer 115 can have a first planarization layer 115a and a second planarization layer 115b, but is not limited to this. For example, the first planarization layer 115a is arranged such that it covers the control element 120, and can be arranged such that it exposes part of the source electrode 122 or the drain electrode 123 of the control element 120. The planarization layer 115 can extend from the display area AA to the non-display area NA. The planarization layer 115 can be a coating layer, but is not limited to this. The connecting electrode 125 for electrically connecting the control element 120 and the light-emitting element 130 can be arranged on the first planarization layer 115a. Furthermore, although not shown in Fig. 2, various metal layers serving as wires / electrodes, such as data lines and signal lines, can be arranged on the first planarization layer 115a. Additionally, the color filter CF can be arranged on the first planarization layer 115a, and is not limited to this; the color filter CF can be omitted depending on the type of organic light-emitting element 130. The color filter CF of each subpixel can have one red, one green, and one blue color. Furthermore, in the case of a subpixel in which white is implemented, the color filter CF can be omitted. The arrangement of red, green, and blue can be formed in various ways. Furthermore, the second planarization layer 115b can be arranged on top of the first planarization layer 115a and the connecting electrode 125. Because the display device 100 has a high resolution, the planarization layer 115 of the first exemplary embodiment of the present disclosure is composed of two layers due to the increasing number of different signal lines. Accordingly, it is difficult to arrange all the wiring on a single layer while ensuring a minimal gap; therefore, an additional layer is formed. The addition of this extra layer (i.e., the second planarization layer 115b) can provide space for a wiring arrangement, which can simplify the design of a wiring / electrode assembly.Furthermore, if a dielectric material is used as the planarization layer 115, which is formed as a multilayer, it can be used to form a capacitance between metal layers. The second planarization layer 115b can be formed in such a way that it exposes part of the connecting electrode 125. Furthermore, the drain electrode 123 of the control element 120 and the anode 131 of the light-emitting element 130 can be electrically connected by the connecting electrode 125. In this case, the light-emitting element 130 can be formed such that the anode 131, a plurality of organic layers 132, and the cathode 133 are arranged sequentially. This means that the light-emitting element 130 can have the anode 131, which is arranged on the planarization layer 115, the organic layer 132, which is arranged on the anode 131, and the cathode 133, which is arranged on the organic layer 132. The display device 100 can be implemented in a top-emission or a bottom-emission type. In the top-emission type, a reflective layer made of an opaque conductive material with high reflectivity, for example silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof, can be added below the anode 131 such that light emitted by the organic layer 132 is reflected by the anode 131 and directed upwards, that is, in the direction towards the cathode 133 at the top. Conversely, in the case of the bottom emission type, the anode 131 can only be made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO).The following description assumes that the display device 100 of the present disclosure is a bottom-emission type. However, the present disclosure is not limited to this. A dam 116 can be formed in a region other than an emission region above the planarization layer 115. This means that the dam 116 has a dam hole that exposes the anode 131 according to the emission region. The dam 116 can be made of an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material, such as BCB, acrylic resin, or imide resin. Dam 116 can extend to the non-display area NA. The organic layer 132 can be arranged on the anode 131, which is exposed by the dam 116. The organic layer 132 can have an emission layer, an electron injection layer, an electron transport layer, a hole transport layer, a hole injection layer, and the like. The organic layer 132 can extend to the non-display area NA. The cathode 133 can be arranged on the organic layer 132. In the case of the top-emission type, the cathode 133 can be made of a transparent conductive material. For example, the cathode 133 can be made of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like. In the case of the bottom-emission type, the cathode 133 can be made of a metal material from a group consisting of, for example, gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), magnesium (Mg), palladium (Pd), copper (Cu), or an alloy thereof.Alternatively, the cathode 133 can be formed by laminating a layer made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and a layer made of a metallic material, such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), magnesium (Mg), palladium (Pd), copper (Cu), or an alloy thereof, but is not limited to this. The cathode 133 can extend to the non-display area NA. Although not shown, a cover layer can be arranged on the cathode 133. The cover layer can be made of a material with a high refractive index and a high light absorption rate to reduce scattered reflection of external light. The protective layer 140 can be arranged above the light-emitting element 130, which is formed as described above. The protective layer 140 can be an inorganic layer and in this case can be made of silicon oxide (SiOx), silicon nitride (SiNx) or a multiple layer thereof. The protective layer 140 can extend to the non-display area NA. The adhesive layer 165 and the encapsulation substrate 160 can be arranged above the protective layer 140. However, the present disclosure is not limited to this, and an encapsulation structure of a multilayer structure composed of a sealing element and a reinforcing substrate may be arranged above the protective layer 140. The adhesive layer 165 can be arranged between the protective layer 140 and the encapsulation substrate 160. For example, the adhesive layer 165 can serve to delay lateral penetration of moisture. For example, the adhesive layer 165 may further comprise a desiccant, such as a getter, in addition to isobutyl rubber resin. The desiccant may comprise calcium oxide. The desiccant may consist of particles that are hygroscopic and absorb moisture and oxygen from the outside in order to minimize the penetration of moisture and oxygen into the AA display area. The encapsulation substrate 160 can be arranged on the adhesive layer 165. The encapsulation substrate 160, together with the adhesive layer 165, can protect the light-emitting element 130 from external moisture, oxygen, shocks and the like. For example, the encapsulation substrate 160 can serve to prevent moisture from penetrating from the front. For example, the encapsulation substrate 160 can be made of stainless steel (SUS) or Invar, but is not limited to these materials. Invar is an alloy consisting of nickel and iron and has a very low coefficient of thermal expansion, making it relatively stable under temperature changes. In the non-display area NA, at least some layers can extend from the buffer layer 112, the gate-insulating layer 113 and the intermediate insulating layer 114, i.e., the insulating layer 117. Furthermore, the planarization layer 115 can extend to the non-display area NA. For example, the insulating layer 117 and the planarizing layer 115, which extend to the non-display area NA, can extend to one end of the substrate 111, but are not limited to this. In the display device 100, a minimum edging distance is required to ensure reliability, such as preventing the ingress of moisture, and while there is an increasing need to slim down the non-display area NA, excluding the display area AA where an image is displayed, in order to meet the need for a slimmer display device 100, a shadow area is created due to the gap between the mask and the substrate during the deposition of the cathode 133 and the organic layer 132, which limits the reduction of the edging. Accordingly, in the first embodiment of the present disclosure, the trench 180 is located in the non-display area NA within the shadowed area. This means that, in the first embodiment of the present disclosure, the trench 180 can delay the rate of moisture penetration towards the side of the display device 100. Furthermore, by converting the conventional shadowed area into the reliability boundary area L in this way, the boundary width can be reduced. The reliability boundary area L can be defined from an end section of the encapsulation substrate 160 to an end section of the cathode 133. The trench 180 can be formed in the non-display area NA on the left, right, and bottom sides of the display device 100, except for the top side where the data pad portion 107 is located (see Fig. 1), but is not limited to these areas. In this case, for example, the trench 180 in the non-display area NA can be formed by laser melting by removing portions of at least one of the insulating layer 117 and the planarization layer 115. Accordingly, the reliability confinement area L can be extended, and the confinement width can be reduced by the length of the added reliability confinement area L. In this case, for example, the trench 180 can expose at least some of the buffer layer 112, the gate insulating layer 113, and the intermediate insulating layer 114. For example, the trench 180 can have a predetermined width to prevent a deterioration of the moisture permeability performance, regardless of the position where the cathode 133 is formed, taking into account a process error and a process margin. In this case, a low-potential power line 135 can be arranged in the trench 180. For example, the low-potential power line 135 can be arranged such that it covers the interior of the trench 180. This means that the low-potential power line 135 can be arranged such that it covers an upper surface and side surfaces of the insulating layer 117 and the planarizing layer 115 that are exposed by the trench 180. For example, the low-potential power line 135 can be located in the non-display area NA on the left, right and bottom of the display device 100 along the trench 180, but is not limited to this. The low-potential power line 135 can have an inner section and an outer section arranged on a sloping side face of the trench 180. For example, the dam 116 in the non-indication area NA, except for the second side, can extend to the non-indication area NA in such a way that it covers an inner section of the low-potential power line 135. Here, the inner section of the low-potential power line 135 can be defined as a side section adjacent to the indication area AA and can be opposite a side section adjacent to an outer section of the non-indication area NA. In this case, the inner section of the low-potential power line 135 can be arranged on the inner side wall of the trench 180 with a predetermined slope.For example, the side wall of trench 180 and the side section of low-potential power line 135 can have a gentle slope of about 30 degrees or less. Such a gentle slope ensures that the thickness of the cathode 133 deposited on top is 1,000 Å or more. The outer dam 116' can cover the outer section of the low-potential power line 135 in an island shape or in the form of an island. In this case, the dam 116 and the outer dam 116' can be separate and arranged on either side of the trench 180, and part of the upper surface of the low-potential power line 135 can be exposed without being covered by the outer dam 116'. The outer dam 116' can be arranged such that it is positioned at a predetermined distance from an edge of the adhesive layer 165 and the encapsulation substrate 160. This means that, in the first embodiment of the present disclosure, the outer dam 116' is formed such that it covers the low-potential current conductor 135 and the inclined section of the planarizing layer 115, and is located away from the remaining areas. Accordingly, the water transfer rate (WTV) can be suppressed. For example, it can be seen that when the dam is removed from the outer area, the rate of moisture penetration is reduced by about 10%. In contrast, dam 116 can extend in the non-indication area NA on the second side along the planarization layer 115 to the non-indication area NA, but is not limited to this. In this case, the organic layer 132 can be located on the dam 116 in the non-display area NA. The organic layer 132 extends to the non-display area NA, and its edge may be located on the inside relative to the edge of the dam 116, but is not restricted to this. In the non-display area NA, the cathode 133 can be arranged on the organic layer 132. In this case, the cathode 133 can extend into the trench 180 in such a way that it covers part of the exposed upper surface or top surface of the low-potential power line 135, but is not limited to this. For example, the cathode 133 can extend into the trench 180 in such a way that it covers the dam 116 and the organic layer 132 within the trench 180. The cathode 133 can be in contact with the exposed top or upper surface of the low-potential current line 135 and can thus receive low-potential current from the low-potential current line 135. The cathode 133 can be arranged in the display area AA such that it extends to the trench 180 and is coupled to the low-potential current line 135. Furthermore, the protective layer 140 can extend into the trench 180 in such a way that it covers the cathode 133, but is not limited to this. The protective layer 140 can be arranged on the cathode 133. For example, in the non-display area NA, excluding the second side, the protective layer 140 can be arranged in such a way that it surrounds the cathode 133. Alternatively, in the non-display area NA, the protective layer 140 can cover part of the upper surface of the cathode 133 on the second side. For example, the protective layer 140 can be made of an inorganic insulating material. The protective layer 140 can delay the penetration of moisture from above and suppress defects caused by pressure marks or foreign substances. The protective layer 140 can be made of silicon dioxide (SiOx), silicon nitride (SiNx) or a multilayer structure thereof to delay the penetration of moisture, but is not limited to this. The encapsulation substrate 160 can be arranged with an interposed adhesive layer 165 above the protective layer 140. In this case, the display device 100 according to the first embodiment of the present disclosure, which is formed as described above, is characterized in that the GIP circuit part 108 is arranged on the inside of the trench 180 (in other words, inwards from the trench 180). This means that if the GIP circuitry is located below the trench or at the edge of the encapsulation substrate, as in conventional technology, control failures frequently occur due to wiring corrosion during moisture ingress. For example, in the conventional design, the GIP circuitry was positioned approximately 0.2 mm from the edge of the encapsulation substrate, allowing moisture to corrode the GIP circuitry and cause control malfunctions. The first embodiment of the present disclosure is characterized in that the trench 180 is arranged at the edge of the non-display area NA, and the GIP circuit part 108 is arranged on the inside of the trench 180 (in other words, inwards from the trench 180), such that it is located at a predetermined distance G from the trench 180. Accordingly, for example, a distance of 1.5 mm or more between the GIP circuit part 108 and the edge of the encapsulation substrate 160 can be ensured. Furthermore, in the first embodiment of the present disclosure, the main wiring (i.e. the high-potential current line EVDD) can be rearranged on the inside of trench 180. In the first embodiment of the present disclosure, the cathode 133 can extend into the trench 180 to seal the GIP circuit part 108. This means that, in conventional techniques, moisture penetrates the dam or the organic layer material of the planarization layer, damaging not only the GIP circuit part but also the light-emitting element. However, in the present disclosure, the cathode 133 can extend into the trench 180, lie next to the low-potential current line 135, and seal the entire GIP circuit part 108 and the display area AA, thus preventing the ingress of moisture or oxygen. Accordingly, the present disclosure can minimize the effect of moisture ingress, thereby drastically improving the stability and durability of the GIP circuit component 108. Consequently, it is possible to improve the reliability of the display device 100. In the present revelation, an additional trench may be arranged on the inside of the trench (in other words, inwards from the trench), which will be described in detail with reference to the drawings. Fig. 6 is a top view of a display device according to a second embodiment of the present disclosure. Fig. 7 is a cross-sectional view along a line IIa-IIa' of the display device of Fig. 6 . Fig. 8 is a cross-sectional view along line IIb-IIb' of the display device of Fig. 6 . The second embodiment of Figs. 6, 7 to 8 has a different trench configuration 280 and 285 than the first embodiment described above in Figs. 1, 2, 3, 4 to 5, and the remaining configuration is essentially the same, so redundant descriptions are omitted. The same components are designated by the same reference numerals. In the following, the description of the same reference numerals may refer to Figs. 1, 2, 3, 4 to 5. Fig. 7 shows part of the non-display area NA on the second side of the display device 200 of Fig. 6, and Fig. 8 shows part of the non-display area NA on the first side of the display device 200 of Fig. 6. For the sake of simplicity, Fig. 8 shows a schematic representation of the GIP circuit part 108 in the non-display area NA. Furthermore, for the sake of simplicity of description, at least some of the buffer layer, the gate-insulating layer and the intermediate insulating layer are shown as the insulating layer 117 in Fig. 7 and Fig. 8. Referring to Fig. 6, Fig. 7 to Fig. 8, in the display device 200 according to the second exemplary embodiment of the present disclosure a planarization layer 215 can be arranged over the substrate 111. The grounding wire GW can be arranged in the non-display area NA, except on the second side above the substrate 111. The grounding wire GW can be arranged in the non-display area NA on the first and third sides on the outside of trenches 280 and 285. A first light-blocking structure PP1 can be arranged on the inside of the grounding wiring GW. The connecting line LW can be located in the non-display area NA on the second side above the substrate 111. In the non-display area NA on the left and right sides of the second exemplary embodiment of the present disclosure, the GIP circuit part 108 can be arranged on the inside of the trenches 280 and 285 (in other words, inwards from the trenches 280 and 285). The GIP circuit part 108 may include a control signal timing line CW, a logic unit LP, a buffer TFT unit B-TFT and a power line GVSS, but is not limited to these. A light-emitting element (130 in Fig. 2) which is electrically connected to the control element (120 in Fig. 2) can be arranged above the planarization layer 215 of the display area AA. A dam 216 can be formed in the remaining area excluding the emission area above the planarization layer 215. The insulating layer 117, the planarizing layer 215 and the dam 216 can extend to the non-display area NA. For example, the insulating layer 117 and the planarizing layer 215, which extend to the non-display area NA, can extend to one end of the substrate 111, but are not limited to this. In the second exemplary embodiment of the present disclosure, a plurality of trenches 280 and 285 are arranged in the shadow area in the non-display area NA. Trenches 280 and 285 may have a first trench 280 and one or more second trenches 285. The first trench 280 can, for example, be located in the non-display area NA. Apart from the top side where the data pad portion 107 is located (see Fig. 6), it can be formed on the left, right, and bottom sides of the display device 200 in the non-display area NA, but is not limited to these areas. In this case, for example, the first trench 280 in the non-display area NA can be formed by removing portions of the insulating layer 117 and the planarization layer 215. Accordingly, the first trench 280 can, for example, expose at least some of the buffer layer, the gate insulating layer, and the intermediate insulating layer. The second trench 285 can be positioned on the inside of the first trench 280 and extend across the four sides of the display device 200, that is, across the non-display area NA on the top, left, right, and bottom sides (see Fig. 6), but is not limited to this. In this case, for example, the second trench 285 can be formed by removing a section of the planarization layer 215 of the non-display area NA. Furthermore, for example, the second trench 285 can expose at least some of the buffer layer, the gate-insulating layer, and the intermediate insulating layer. The majority of second trenches 285 can be arranged. The first trench 280 can have a width greater than that of any second trench 285. For example, the first trench 280 can be referred to as an OC (cover) hole, and the second trench 285 can be referred to as a ledge trench. For example, a plurality of dams 250 can be arranged between the second ditches 285. For example, the majority of dams 250 may be arranged between the first ditch 280 and the second ditch 285 and between the second ditches 285, but are not limited to this. Dam 250 can be set up as the planarization layer 215, but is not limited to this. Dam 250 can have a height lower than that of the surrounding planarization layer 215, but is not limited to this. In this case, a first low-potential power line 235 can be arranged in the first trench 280. The first low-potential power line 235 can be arranged such that it covers the interior of the first trench 280. This means that the first low-potential power line 235 can be arranged such that it covers an upper surface and side faces of the insulating layer 117 and the planarizing layer 215 exposed by the first trench 280. The first low-potential power line 235 can be arranged such that it covers an upper surface of the insulating layer 117 and part of an upper surface and a side face of the planarizing layer 215 exposed by the first trench 280. In this case, the first low-potential power line 235 can be located in the non-indicating area NA on the left, right and bottom of the indicator device 200 along the first trench 280, but is not limited to this. Furthermore, a second low-potential power line 236 can be arranged in the second trench 285 and coupled to the cathode 233. The second low-potential power line 236 can be arranged such that it covers the interior of the second trench 285. This means that the second low-potential power line 236 can be arranged such that it covers an upper surface of the insulating layer 117 and the side surface and part of the upper surface of the dam 250 exposed by the second trench 285. In this case, the second low-potential power line 236 can be arranged in the non-display area NA on the upper, left, right and lower sides of the display device 200 along the second trench 285, but is not limited to this. For example, an outer dam 216' and an inner dam 216", separated from the dam 216 in an island shape, can be arranged on the outside of the GIP circuit part 108. For example, in the non-indication area NA, except for the second side, the outer dam 216' can cover an outer section of the first low-potential power line 235 in an island configuration. In this configuration, the outer dam 216' and the inner dam 216" can be separate and arranged on either side with respect to the first trench 280, and part of the upper surface of the first low-potential power line 235 can be exposed without being covered by the outer dam 216'. The outer dam 216' can be arranged at a predetermined distance from the edges of the adhesive layer 165 and the encapsulation substrate 160. This means that, in the second embodiment of the present disclosure, the outer dam 216' is formed such that it covers the inclined sections of the first low-potential current conductor 235 and the planarization layer 215 on the outside of the first trench 280, and is removed in the remaining areas. For example, the inner dam 216" can be arranged in an island shape such that it covers the inner section of the first low-potential power line 235 and / or the side section of the second low-potential power line 236. This means that the inner dam 216" and the second low-potential power line 236 can be provided multiple times: One inner dam 216" can cover the inner section or the inner side of the first low-potential power line 235 and the side section of the second low-potential power line 236, while another inner dam 216" can cover the side section of a second low-potential power line 236 and the side section of yet another second low-potential power line 236. In contrast, dam 216 can extend in the non-indication area NA on the second side along the planarization layer 215 to the non-indication area NA, but is not limited to this. In this case, the organic layer 132 can be located on the dam 216 in the non-display area NA. The organic layer 132 extends to the non-display area NA, and its edge may be located on the inside relative to the edge of the dam 216, but is not restricted to this. In the non-display area NA, the cathode 233 can be located on the organic layer 132. In this case, the cathode 233 can extend into the first trench 280 in such a way that it covers part of the exposed upper surface of the first low-potential power line 235, but is not limited to this. For example, the cathode 233 can extend into the first trench 280 in the non-display area NA, excluding the second side, in such a way that it covers the inner dam 216" and the second low-potential power line 236. Alternatively, the cathode 233 can extend into the non-display area NA on the second side in such a way that it covers the inner dam 216" and the second trench 285. The cathode 233 can be in contact with the exposed upper surface of the first low-potential current line 235, such that it receives low-potential current from the first low-potential current line 235. Furthermore, the protective layer 240 can extend into the trenches 280 and 285 in such a way that it covers the cathode 233, but is not limited to this. In this case, for example, the protective layer 240 can be arranged such that it surrounds the cathode 233 in the non-display area NA, excluding the second side. In contrast, in the non-display area NA, the protective layer 240 can cover part of the upper surface of the cathode 233 on the inside of the second trench 285. The protective layer 240 can also cover the interior of the second trench 285. The encapsulation substrate 160 can be arranged with an interposed adhesive layer 165 above the protective layer 240. In this case, the display device 200 according to the second exemplary embodiment of the present disclosure, which is formed as described above, is characterized in that the GIP circuit part 108 is arranged on the inside of the second trench 285. The second embodiment of the present disclosure is characterized in that the first trench 280 and the plurality of second trenches 285 are arranged at the edge of the non-display area NA, and the GIP circuit part 108 is arranged on the inside of the second trench 285 such that it is located at a predetermined distance G1 from the innermost second trench 285. As described above, in the second exemplary embodiment of the present disclosure, a plurality of second grooves 285 are additionally arranged in the first groove 280, such that the rate of moisture penetration into the side surface of the display device 200 is further delayed. Furthermore, in the second exemplary embodiment of the present disclosure, the GIP circuit part 108 is arranged on the inside of the second groove 285, which is positioned further inside than the first groove 280, such that the penetration of moisture or oxygen is more effectively suppressed. According to the present disclosure, an encapsulation structure of a multilayer structure, composed of a sealing element and a reinforcing substrate, can be arranged on a cathode, and this will be described in detail with reference to the drawings. Fig. 9 is a cross-sectional view of a display device according to a third embodiment of the present disclosure. The third embodiment of Fig. 9 is essentially the same as the second embodiment described above in Figs. 6, 7 to 8, except that the encapsulation structure of the multilayer structure, composed of the sealing element 365 and the reinforcing substrate 360, is used. Therefore, a redundant description of it will be omitted. Furthermore, the same reference numerals are used for the same components. In the following, the description of the same reference numerals may refer to Figs. 1, 2, 3, 4, 5, 6, 7 to 8. Fig. 9 shows, as an example in the display device 300 according to the third embodiment of the present disclosure, a part of the non-display area NA on the first side. Referring to Fig. 9, in the display device 300 according to the third embodiment of the present disclosure a first trench 280 and a plurality of second trenches 285 can be arranged in the non-display area NA. A plurality of dams 250 can be arranged between the second ditches 285. A first low-potential power line 235 can be arranged in the first trench 280. Furthermore, a second low-potential power line 236 can be arranged within the second trench 285. In the non-display area NA on the left and right sides of the third exemplary embodiment of the present disclosure, the GIP circuit part 108 can be arranged on the inside of the second trench 285. For example, an outer dam 216' and an inner dam 216", separated from the dam 216 in an island shape, can be arranged on the outside of the GIP circuit part 108. Furthermore, the cathode 233 can extend into the first trench 280 in such a way that it covers part of the exposed upper surface of the first low-potential power line 235. The cathode 233 can extend into the first trench 280 in such a way that it covers the inner dam 216" and the second low-potential power line 236. An encapsulation structure of a multilayer structure, composed of a sealing element 365 and a reinforcing substrate 360, can be arranged above the cathode 233. A small display panel used in mobile and portable devices has a small surface area, allowing for rapid heat dissipation and fewer bonding issues. However, in a large display panel used in a monitor, tablet, or television receiver, the surface area is large, necessitating an encapsulation structure for optimal heat dissipation and bond strength. Furthermore, to compensate for insufficient rigidity, the display device can also incorporate a separate inner plate on the encapsulation substrate. In this case, it is necessary to provide space for this separate inner plate, and there is a problem in that the weight of the inner plate limits the slimming and lightening of the display device. Additionally, an air gap created between the encapsulation substrate and the inner plate, equal to the thickness of the adhesive tape used to bond them, creates a vertical space, thus reducing heat dissipation performance. Accordingly, in the third embodiment of the present disclosure, it is possible to fix the reinforcing substrate 360, which has a relatively large thickness, while the separate inner plate is removed, and it is characterized in that the encapsulation structure of the multilayer structure, which has the sealing element 365 that can prevent the process error, is applied. For example, according to the third exemplary embodiment of the present disclosure, the sealing element 365 can have a first adhesive layer 365a facing the substrate 111, a second adhesive layer 365c facing the reinforcing substrate 360, and a barrier layer 365b arranged between the first adhesive layer 365a and the second adhesive layer 365c. In this case, both the first adhesive layer 365a and the second adhesive layer 365c can be made from a polymer material with adhesive properties. For example, the first adhesive layer 365a can be made from one of the following polymer materials: olefin-based, epoxy-based, or acrylate-based. Furthermore, the second adhesive layer 365c can be made from one of the following materials: olefin-based, epoxy-based, acrylate-based, amine-based, phenol-based, or acid anhydride-based, provided it does not contain a carboxyl group. For heat dissipation from the substrate 111, at least the first adhesive layer 365a and the second adhesive layer 365c can be formed from a mixture containing particles of an adhesive polymer material and a metal material. For example, the metal material particles can be powder made of nickel (Ni). In this way, since the speed at which the control heat generated in the substrate 111 is released by the sealing element 365 can be improved, the heat dissipation effect on the substrate 111 can be improved. Furthermore, to prevent moisture penetration, the first adhesive layer 365a can be formed from a mixture that also contains a hygroscopic inorganic filler. The hygroscopic inorganic filler can be at least one of barium oxide (BaO), calcium oxide (CaO), and magnesium oxide (MgO). Furthermore, since the first adhesive layer 365a and the second adhesive layer 365c are formed in a multilayer structure, there is an advantage in that the reliability in reducing the warping phenomenon, in which the display panel is bent, can also be improved. Barrier layer 365b can be formed from a metallic material and an inorganic insulating material. This means that barrier layer 365b can contain a metallic material such as Al, Cu, Sn, Ag, Fe, Zn, and the like. Alternatively, barrier layer 365b can be formed from a thin film of an inorganic insulating material such as SiOx and SiONx. As described above, the sealing element 365 of the third embodiment of the present disclosure, since it comprises the first adhesive layer 365a and the second adhesive layer 365c, which are separated by the barrier layer 365b, can be implemented such that, without any process defect, it has a thickness approximately twice that of the adhesive material of each layer. Accordingly, since the reinforcing substrate 360, which is fixed by the sealing element 365, can be provided with a considerable thickness, there is an advantage in that the increase in stiffness and the improvement of the heat dissipation effect can be easily achieved. For example, the 360 ​​reinforcement substrate can be made from a combination of glass, metal, and plastic polymers. For example, the 360 ​​reinforcement substrate can be made from a metal material containing components of Al, Cu, Sn, Ag, Fe, or Zn. In this case, the cathode of the present revelation can be arranged in such a way that it completely covers the interior of the trench, and this will be described in detail with reference to the drawings. Fig. 10 is a cross-sectional view of a display device according to a fourth embodiment of the present disclosure. Fig. 11 is a cross-sectional view of a display device according to a fifth embodiment of the present disclosure. The fourth embodiment of Fig. 10 is essentially the same as the first embodiment described above in Figs. 1, 2, 3, 4 to 5, except for the configurations of the cathode 433 and the protective layer 440. Accordingly, their common features are essentially the same, and therefore redundant descriptions thereof will be omitted. Furthermore, in the fifth embodiment of Fig. 11, only one configuration of the cathode 533 differs from that of the third embodiment described above in Figs. 7, 8 to 9, and other configurations, including the protective layer 540, are essentially the same, so that a redundant description will be omitted. The same components are designated by the same reference numerals. In the following, the description of the same reference numerals may refer to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 to Fig. 9. Figs. 10 and 11 represent, as an example in the display devices 400 and 500 of the fourth and fifth embodiments of the present disclosure, a part of the non-display area NA on the first side. Referring to Fig. 10, a trench 180 can be provided at an edge of the non-display area NA between the substrate 111 and the encapsulation substrate 160. In the non-display area NA on the left and right sides, the GIP circuit part 108 can be located on the inside of the trench 180 (in other words, inwards from the trench 180). A low-potential power line 135 can be arranged in trench 180. For example, dam 116 may extend to the non-indication area NA in such a way that it covers an inner section of the low-potential power line 135. In this case, the outer dam 116', which is separated from dam 116 by trench 180, may cover the outer section of the low-potential power line 135 in an island shape, and part of the upper surface of the low-potential power line 135 may be exposed without being covered by the outer dam 116'. In the non-display area NA, the cathode 433 can be located on the organic layer 132. The cathode 433 according to the fourth embodiment of the present disclosure can extend to the non-indicator area NA in such a way that it covers the entire trench 180. This means, for example, that the cathode 433 can extend to the non-indicator area NA in such a way that it covers the side surface and part of the upper surface of the outer dam 116' on the top and outer side of the exposed low-potential power line 135. Furthermore, the protective layer 440 can extend to the non-display area NA in such a way that it covers the cathode 433, but is not limited to this. For example, the protective layer 440 can also extend to the non-display area NA in such a way that it surrounds the cathode 433 and the outer dam 116'. Referring to Fig. 11, the GIP circuit part 108 can be arranged in the non-display area NA on the left and right sides on the inside of the trenches 280 and 285 (in other words, inwards from the trenches 280 and 285). The GIP circuit part 108 can be arranged together on the first side and the second side facing the first side. The ditches 280 and 285 can have a first ditch 280 and a plurality of second ditches 285 arranged successively from the outside. For example, a plurality of dams 250 can be arranged between the second ditches 285. A first low-potential power line 235 can be arranged in the first trench 280. Furthermore, a second low-potential power line 236 can be arranged within the second trench 285. For example, an outer dam 216' and an inner dam 216", separated from the dam 216 in an island shape, can be arranged on the outside of the GIP circuit part 108. For example, the outer dam 216' can cover an outer section of the first low-potential power line 235 in an island shape. Furthermore, the inner dam 216" can cover the inner section of the first low-potential power line 235 and / or the side section of the second low-potential power line 236 in an island shape. In the non-display area NA, the cathode 533 can be located on the organic layer 132. The cathode 533 according to the fifth embodiment of the present disclosure can extend to the non-display area NA such that it covers the entire trenches 280 and 285. For example, the cathode 533 can extend to the non-display area NA such that it covers the inner dams 216" and the second low-potential current line 236, including an upper surface of the exposed low-potential current line 235 and a side face and part of an upper surface of the outer dam 216'. Furthermore, the protective layer 540 can extend to the non-display area NA such that it covers the cathode 533, but is not limited to this. For example, the protective layer 540 can also extend to the non-display area NA such that it surrounds the cathode 533 and the outer dam 216'. The exemplary embodiments of the present disclosure can also be described as follows:A display device according to an exemplary embodiment of the present disclosure may comprise a substrate having a display area and a non-display area on an outer surface of the display area, an insulating layer and a planarizing layer arranged over the substrate and extending from the display area to the non-display area, at least one trench arranged in the non-display area and formed by removing a portion of at least one of the insulating layer and the planarizing layer, a dam arranged on the planarizing layer and extending to the non-display area, an organic layer arranged on the dam, a cathode arranged on the organic layer and extending to the at least one trench, a protective layer arranged on the cathode, and a gate-in-panel (GIP) circuit component.which is located on a first side in the non-display area and is positioned on the inside of the at least one trench (in other words, inwards from the at least one trench; in yet other words, inwards from the at least one trench (i.e., on a side of the at least one trench that is close to the display area, as opposed to a side of the at least one trench that is farther from the display area); for example, between the at least one trench and the display area). A data pad portion can be located on a second side adjacent to the first side on which the gate-in-panel circuit portion is located. The at least one trench can be arranged in such a way that it surrounds the display area except for the second side. The display device may further comprise a grounding wire arranged in the non-display area except the second side above the substrate, a first light-blocking structure arranged on the inside of the grounding wire, and a connecting wire arranged in the non-display area on the second side above the substrate. The display device may further comprise a second light-blocking structure and a high-potential current line, arranged on a third and / or fourth side, where the gate-in-panel circuit part and the data pad part are not present, in the non-display area and positioned on the inside of the at least one trench. The indicator device may further comprise a first low-potential current line arranged in the at least one trench such that it covers the interior of the at least one trench, wherein the first low-potential current line may cover an upper surface of the insulating layer, a part of an upper surface and a side surface of the planarizing layer exposed by the at least one trench. The first low-potential power line may, in the non-indication area except the second side, have an inner section and an outer section arranged on an inclined side surface of the at least one trench; the embankment may extend to the non-indication area in such a way as to cover the inner section of the first low-potential power line; and in the non-indication area on the second side, the embankment may extend along the planarization layer to the non-indication area. The indicator device may further comprise an outer dam which is separated from the dam in respect of the at least one trench and covers an outer section of the first low-potential power line in the form of an island, and part of an upper surface of the first low-potential power line may be exposed without being covered by the outer dam. An encapsulation substrate can be arranged with an interposed adhesive layer over the protective layer, and the outer dam can be positioned at a predetermined distance from the edges of the adhesive layer and the encapsulation substrate. The cathode can extend into the at least one trench in such a way that it covers part of the upper surface of the exposed first low-potential power line, the cathode can be in contact with the upper surface of the exposed first low-potential power line, and the cathode can cover the dam and the organic layer on the inside of the at least one trench. In the non-display area, excluding the second side, the protective layer may be arranged to surround the cathode, and in the non-display area on the second side, the protective layer may cover part of an upper surface of the cathode. The at least one trench may have a first trench located in the non-display area except the second side, and a second trench positioned on the inside of the first trench and located on the first to fourth sides in the non-display area. The first trench can be formed by removing portions of the insulating layer and the planarization layer of the non-display area, and the second trench can be formed by removing a portion of the planarization layer of the non-display area. A plurality of secondary trenches may be arranged, and the display device may further comprise a plurality of dams arranged between the plurality of secondary trenches and forming the planarization layer. The indicator device may further comprise a first low-potential current line arranged in the first trench such that it covers the interior of the first trench, wherein the first low-potential current line may be arranged such that it covers an upper surface of the insulating layer and part of an upper surface and a side surface of the planarizing layer exposed by the first trench. The indicator device may further comprise a second low-potential current line arranged in the second trench such that it covers the interior of the second trench, wherein the second low-potential current line may be arranged such that it covers an upper surface of the insulating layer and part of an upper surface and a side face of the dam exposed by the second trench. The display device may further comprise, in the non-display area except the second side, an outer dam and an inner dam, which are separated from the dam and arranged in an island shape on an outside of the GIP circuit part; the outer dam may cover an outer section of the first low-potential current line, and part of the upper surface of the first low-potential current line may be exposed without being covered by the outer dam. An encapsulation substrate can be arranged with an interposed adhesive layer over the protective layer, and the outer dam can be positioned at a predetermined distance from the edges of the adhesive layer and the encapsulation substrate. The inner dam and the second low-potential power line can be formed in multiples; one of the inner dams can cover an inner side of the first low-potential power line and a side of one of the second low-potential power lines, and another of the inner dams can cover the side of one of the second low-potential power lines and a side of another of the second low-potential power lines. In the non-display area, excluding the second side, the cathode may extend into the first trench in such a way that it covers the inner dam and the second low-potential power line, and in the non-display area on the second side, the cathode may extend into the non-display area in such a way that it covers the inner dam and the second trench. In the non-display area, excluding the second side, the protective layer may be arranged to surround the cathode, and in the non-display area on the second side, the protective layer on the inside of the second trench may cover part of an upper surface of the cathode. The cathode can extend to the non-display area in such a way that it covers the entirety of at least one trench, and the protective layer can extend to the non-display area in such a way that it surrounds the cathode. The gate-in-panel circuitry can be arranged together on the first side and the second side facing the first side.

Claims

A display device (100, 200, 300, 400, 500) comprising: a substrate (111) having a display area (AA) and a non-display area (NA) on the outside of the display area (AA); an insulating layer (117) and a planarizing layer (115, 215) arranged on the substrate (111) and extending from the display area (AA) to the non-display area (NA); at least one trench (180, 280, 285) arranged in the non-display area (NA) and formed by removing a portion of at least one of the insulating layer (117) and the planarizing layer (115, 215); a dam (116, 216) arranged on the planarizing layer (115, 215) and extending to the non-display area (NA); a organic layer (132) arranged on the dam (116, 216);a cathode (133, 233, 433, 533) arranged on the organic layer (132) and extending to the at least one trench (180, 280, 285); a protective layer (140, 240, 440, 540) arranged on the cathode (133, 233, 433, 533); and a gate-in-panel circuit part (108) arranged on a first side on the non-display area (NA) and positioned on the inside of the at least one trench (180, 280, 285). The display device (100, 200, 300, 400, 500) according to claim 1, wherein a data pad part (107) is arranged on a second side adjacent to the first side on which the gate-in-panel circuit part (108) is arranged. The display device (100, 200, 300, 400, 500) according to claim 2, wherein the at least one trench (180, 280, 285) is arranged such that it surrounds the display area (AA) except the second side. The display device (100, 200, 300, 400, 500) according to claim 2 or 3, further comprising: a grounding wiring (GW) arranged above the substrate (111) in the non-display area (NA) except the second side; a first light-blocking structure (PP1) arranged on the inside of the grounding wiring (GW); and a connecting line (LW) arranged in the non-display area (NA) on the second side above the substrate (111). The display device (100, 200, 300, 400, 500) according to claim 4, further comprising: a second light-blocking structure (PP2) and a high-potential current line (EVDD) arranged on a third side and / or a fourth side, where the gate-in-panel circuit part (108) and the data pad part (107) are not present, above the non-display area (NA) and positioned on the inside of the at least one trench (180, 280, 285). The display device (100, 200, 300, 400, 500) according to any one of claims 2 to 5, further comprising: a first low-potential current line (135, 235) arranged in the at least one trench (180, 280) such that it covers the interior of the at least one trench (180, 280), wherein the first low-potential current line (135, 235) covers an upper surface of the insulating layer (117) and a part of an upper surface and a side surface of the planarizing layer (115, 215) exposed by the at least one trench (180, 280). The indicator device (100, 200, 300, 400, 500) according to claim 6, wherein the first low-potential current line (135, 235) has an inner section and an outer section arranged on an inclined side surface of the at least one trench (180, 280), wherein the dam (116, 216) extends in the non-indicator area (NA) except on the second side to the non-indicator area (NA) such that it covers the inner section of the first low-potential current line (135, 235), and wherein the dam (116, 216) extends in the non-indicator area (NA) on the second side along the planarization layer (115, 215) to the non-indicator area (NA). The display device (100, 200, 300, 400, 500) according to claim 7, further comprising: an outer dam (116', 216') which is separated from the dam (116, 216) with respect to the at least one trench (180, 280, 285) and covers the outer section of the first low-potential power line (135, 235) in the form of an island, wherein part of an upper surface of the first low-potential power line (135, 235) is exposed without being covered by the outer dam (116', 216'). The display device (100, 200, 400, 500) according to claim 8, wherein an encapsulation substrate (160) with an interposed adhesive layer (165) is arranged over the protective layer (140, 240, 440, 540), and wherein the outer dam (116', 216') is arranged at a predetermined distance from the edges of the adhesive layer (165) and the encapsulation substrate (160). The display device (100, 200, 300, 400, 500) according to claim 8 or 9, wherein the cathode (133, 233, 433, 533) extends into the at least one trench (180, 280, 285) such that it covers part of an upper surface of the exposed first low-potential current line (135, 235), wherein the cathode (133, 233, 433, 533) is in contact with the upper surface of the exposed first low-potential current line (135, 235), and wherein the cathode (133, 233, 433, 533) covers the dam (116, 216) and the organic layer (132) on the inside of the at least one trench (180, 280, 285). 285) covered. The display device (100, 200, 300, 400, 500) according to any one of claims 2 to 10, wherein in the non-display area (NA) except the second side the protective layer (140, 240, 440, 540) is arranged such that it surrounds the cathode (133, 233, 433, 533), and wherein in the non-display area (NA) on the second side the protective layer (140, 240, 440, 540) covers part of an upper surface of the cathode (133, 233, 433, 533). The display device (200, 300, 500) according to claim 5, wherein the at least one trench (280, 285) has: a first trench (280) which is arranged in the non-display area (NA) except the second side; and a second trench (285) which is positioned on the inside of the first trench (280) and is arranged in the non-display area (NA) on the first to fourth side. The display device (200, 300, 500) according to claim 12, wherein the first trench (280) is formed by removing partial areas of the insulating layer (117) and the planarization layer (215) of the non-display area (NA), and wherein the second trench (285) is formed by removing a partial area of ​​the planarization layer (215) of the non-display area (NA). The display device (200, 300, 500) according to claim 12 or 13, wherein a plurality of second trenches (285) are arranged, and wherein the display device (200, 300, 500) further comprises a plurality of dams (250) arranged between the plurality of second trenches (285) and forming the planarization layer (215). The display device (200, 300, 500) according to claim 12 or 13, further comprising: a first low-potential current line (235) arranged in the first trench (280) such that it covers the interior of the first trench (280), wherein the first low-potential current line (235) is arranged such that it covers an upper surface of the insulating layer (117) and a part of an upper surface and a side surface of the planarizing layer (215) exposed by the first trench (280). The display device (200, 300, 500) according to claim 15, further comprising: a second low-potential current line (236) arranged in the second trench (285) such that it covers the interior of the second trench (285), wherein the second low-potential current line (236) is arranged such that it covers an upper surface of the insulating layer (117) and a part of an upper surface and a side surface of the dam (250) exposed by the second trench (285). The display device (200, 300, 500) according to claim 16, further comprising: an outer dam (216') and an inner dam (216"), which are separated from the dam (216) and are arranged in an island shape on an outer side of the gate-in-panel circuit part (108), wherein the outer dam (216') covers an outer section of the first low-potential current line (235) in the non-display area (NA) except the second side, and wherein a portion of the upper surface of the first low-potential current line (235) is exposed without being covered by the outer dam (216'). The display device (200, 500) according to claim 17, wherein an encapsulation substrate (160) with an interposed adhesive layer (165) is arranged over the protective layer (240, 540), and wherein the outer dam (216') is arranged at a predetermined distance from the edges of the adhesive layer (165) and the encapsulation substrate (160). The display device (200, 500) according to claim 17 or 18, wherein the inner dam (216") and the second low-potential current line (236) are formed in a plurality, wherein one of the inner dams (216") covers an inner side of the first low-potential current line (235) and a side of one of the second low-potential current lines (236), and wherein another of the inner dams (216") covers the side of one of the second low-potential current lines (236) and a side of another of the second low-potential current lines (236). The display device (200, 500) according to claim 17 or 18, wherein the cathode (233, 533) extends into the first trench (280) in the non-display area (NA), excluding the second side, such that it covers the inner dam (216") and the second low-potential current line (236), and wherein, in the non-display area (NA), on the second side, the cathode (233, 533) extends to the non-display area (NA) such that it covers the inner dam (216") and the second trench (285). The display device (200, 500) according to one of claims 17 to 20, wherein the protective layer (240, 540) in the non-display area (NA) except the second side is arranged such that it surrounds the cathode (233, 533), and wherein the protective layer (240, 540) in the non-display area (NA) on the second side covers a part of an upper surface of the cathode (233, 533) on the inside of the second groove (285). The display device (400) according to one of claims 1 to 21, wherein the cathode (433) extends to the non-display area (NA) in such a way that it covers the entire at least one trench (180), and wherein the protective layer (440) extends to the non-display area (NA) in such a way that it surrounds the cathode (433). The display device (100, 200, 300, 400, 500) according to one of claims 1 to 22, wherein the gate-in-panel circuit part (108) is arranged together on the first side and the second side facing the first side. A display device (100, 200, 300, 400, 500) comprising: a substrate (111) having a display area (AA) and a non-display area (NA) on the outside of the display area (AA); at least one trench (180, 280, 285) arranged in the non-display area (NA); a first low-potential current line (135, 235) arranged in the at least one trench (180, 280, 285); a cathode (133, 233, 433, 533) arranged in the display area (AA) such that it extends to the at least one trench (180, 280, 285) and is coupled to the first low-potential current line (135, 235); a Gate-in-panel circuit part (108) arranged on a first side in the non-display area (NA) and positioned on the inside of the at least one trench (180, 280, 285);and an earthing wiring (GW) located in the non-indication area (NA) on the first side and a third side on the outside of the at least one trench (180, 280, 285). The display device (200, 300, 500) according to claim 24, wherein the at least one trench (280, 285) comprises: a first trench (280) arranged in the non-display area (NA); and one or more second trenches (285) arranged in the non-display area (NA) on the first side, a second side, the third side and a fourth side. The display device (200, 300, 500) according to claim 24 or 25, further comprising: a first light-blocking structure (PP1) arranged between the grounding wiring (GW) and the at least one trench (280, 285). The display device (200, 300, 500) according to one of claims 24 to 26, further comprising: a second light-blocking structure (PP2) and a high-potential current line (EVDD) arranged on an inner side of the at least one trench (280, 285). The display device (200, 300, 500) according to claim 25 or one of claims 26 or 27, which relate directly or indirectly to claim 25, further comprising: one or more second low-potential current lines (236) arranged within the one or more second trenches (285) and coupled to the cathode (233, 533). The display device (200, 300, 500) according to claim 25 or one of claims 26 to 28, which relate directly or indirectly to claim 25, wherein the first trench (280) has a width greater than that of each of the one or more second trenches (285). The display device (200, 300, 500) according to claim 25 or one of claims 26 to 29, which relate directly or indirectly to claim 25, further comprising: a plurality of dams (250) arranged between the one or the several second ditches (285).

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