INTEGRATED CIRCUIT AND MANUFACTURING PROCESS

DE102026100459A1Undetermined Publication Date: 2026-10-08TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
DE102026100459
Authority / Receiving Office
DE · DE
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-07-10
Filing Date
2026-01-05
Publication Date
2026-10-08
Patent Text Reader

Abstract

An integrated circuit device comprises: a die; an interconnect that at least partially overlaps the die; and several bumps in an area where the interconnect overlaps the die.The interconnect has at least a first conductive layer and a second conductive layer, wherein the multiple humps include a first hump and a second hump, wherein both the first and the second conductive layer have multiple signal conductors between the first hump and the second hump and multiple ground conductors between the first hump and the second hump, and all signal conductors in both the first and the second conductive layer lie between corresponding pairs of ground conductors in the corresponding conductive layer, and the pairs of ground conductors are continuously connected in the first and the second conductive layer from a first side of the multiple signal conductors to a second side of the multiple signal conductors.
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Citation Information

Patent Citations

  • US63783054B1