Method for testing the EMI value of an LPDDR chip, system, device and storage medium
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Applications
- Current Assignee / Owner
- RAYSON HI-TECH (SZ) CO LTD
- Filing Date
- 2026-01-08
- Publication Date
- 2026-07-23
Smart Images

Figure 00000000_0000_ABST
Abstract
Claims
A method for testing the EMI value of an LPDDR chip, characterized in that the method comprises: acquiring a first memory capacity of the LPDDR chip, wherein the first memory capacity characterizes the memory capacity assigned to the first rank; acquiring the second memory capacity of the LPDDR chip, wherein the second memory capacity characterizes the memory capacity assigned to the second rank; comparing the first memory capacity and the second memory capacity, each with a preset memory capacity, to obtain a first comparison result;Acquiring a first EMI value and a second EMI value according to the first comparison result, a first memory table and a second memory table, specifically comprising: determining a size ratio between the first memory capacity and the second memory capacity and the preset memory capacity according to the first comparison result, and acquiring the first EMI value and the second EMI value according to the size ratio from the first memory table and the second memory table, respectively; wherein the first memory table characterizes a relationship table between a first parameter value and a memory capacity, wherein the second memory table characterizes a relationship table between a second parameter value and a memory capacity, wherein the first EMI value characterizes the first-rank EMI value, and wherein the second EMI value characterizes the second-rank EMI value;Determining the EMI value of the LPDDR chip according to the first EMI value and the second EMI value. The method of claim 1, characterized in that the acquisition of a first EMI value and a second EMI value according to the first comparison result, a first memory table and a second memory table comprises: acquiring the first EMI value via the first memory table if the first comparison result indicates that the first memory capacity is greater than the preset memory capacity; acquiring the second EMI value via the first memory table if the first comparison result indicates that the second memory capacity is greater than the preset memory capacity; acquiring the first EMI value via the second memory table if the first comparison result indicates that the first memory capacity is less than or equal to the preset memory capacity;Capturing the first EMI value via the second memory table if the first comparison result indicates that the first memory capacity is less than or equal to the preset memory capacity. The method of claim 2, characterized in that the method also comprises: comparing the first storage capacity with the second storage capacity to obtain a second comparison result if the first comparison result indicates that both the first storage capacity and the second storage capacity are less than or equal to the preset storage capacity; acquiring the first EMI value and the second EMI value via the second storage table if the second comparison result indicates that the first storage capacity and the second storage capacity are equal; acquiring the first EMI value and the second EMI value via the first storage table if the second comparison result indicates that the first storage capacity and the second storage capacity are not equal. The method according to claim 3, characterized in that the acquisition of the first EMI value or the second EMI value via the second memory table and the acquisition of the first EMI value or the second EMI value via the second memory table comprise: acquiring the first parameter value from the first memory table according to the first memory capacity or the second memory capacity, wherein the first EMI value or the second EMI value is calculated via the first parameter value; acquiring the second parameter value from the second memory table according to the first memory capacity or the second memory capacity, wherein the first or second EMI value is calculated via the second parameter value. The method according to claim 1, characterized in that determining the EMI value of the LPDDR chip according to the first EMI value and the second EMI value comprises: acquiring a first weighting coefficient associated with the first EMI value and a second weighting coefficient associated with the second EMI value; calculating the EMI value of the LPDDR chip according to the first EMI value, the first weighting coefficient, the second EMI value and the second weighting coefficient. The method of claim 4, characterized in that acquiring the first parameter value from a first memory table according to the first memory capacity or the second memory capacity and acquiring the second parameter value from a second memory table according to the first memory capacity or the second memory capacity comprises: determining a first table range of the first memory table by converting the first memory capacity or the second memory capacity; configuring the parameter assigned to the first table range to the first parameter value, wherein the first parameter value indicates the corresponding EMI value; determining a second table range of the second memory table by converting the first memory capacity or the second memory capacity;Configure the parameter assigned to the second table range as the second parameter value, where the second parameter value specifies the corresponding EMI value. The method of claim 1, characterized in that, prior to determining the EMI value of the LPDDR chip according to the first EMI value and the second EMI value, the method also comprises: determining the operating mode of the LPDDR chip; setting the first EMI value, which is associated with the non-functioning first rank, to zero, or setting the second EMI value, which is associated with the non-functioning second rank, to zero if the operating mode specifies a single-channel mode; determining the interference coefficient between the first rank and the second rank if the operating mode specifies a dual-channel mode; correcting the first EMI value and the second EMI value according to the interference coefficient. A system for testing the EMI value of an LPDDR chip, characterized in that the system comprises: a first module used to detect the first memory capacity of the LPDDR chip, wherein the first memory capacity characterizes the memory capacity assigned to the first rank; a second module used to detect the second memory capacity of the LPDDR chip, wherein the second memory capacity characterizes the memory capacity assigned to the second rank; a third module used to compare the first memory capacity and the second memory capacity, each with a preset memory capacity, in order to obtain a first comparison result;A fourth module, used to acquire a first EMI value and a second EMI value according to the first comparison result, a first memory table, and a second memory table, specifically comprising: determining a size ratio between the first memory capacity and the second memory capacity and the preset memory capacity according to the first comparison result, and acquiring the first EMI value and the second EMI value according to the size ratio from the first memory table and the second memory table, respectively; wherein the first memory table characterizes a relationship table between a first parameter value and a memory capacity, wherein the second memory table characterizes a relationship table between a second parameter value and a memory capacity, wherein the first EMI value characterizes the first-rank EMI value, and wherein the second EMI value characterizes the second-rank EMI value;a fifth module used to determine the EMI value of the LPDDR chip according to the first EMI value and the second EMI value. Memory test device, characterized in that it comprises: at least one processor; at least one memory for storing at least one program; wherein the at least one processor implements the method according to one of claims 1 to 7 when the at least one program is executed by the at least one processor. A computer-readable storage medium that stores a processor-executable program, characterized in that the processor-executable program, when executed by the processor, is used to perform the method according to one of claims 1 to 7.