Disaggregated integrity tree with in-memory verification and batch tree update

DE102026103307A1Undetermined Publication Date: 2026-07-30NVIDIA CORP
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Patent Information

Authority / Receiving Office
DE · DE
Patent Type
Applications
Current Assignee / Owner
NVIDIA CORP
Filing Date
2026-01-27
Publication Date
2026-07-30
Patent Text Reader

Abstract

This document discloses devices, systems, and methods for disaggregated integrity tree verification with zero-overhead data processing. The system can receive a read request for a target data block and access the target data block's metadata via a data processing unit (DPU) to obtain a higher-order cryptographic value. The system can authenticate the target data block by comparing the obtained higher-order cryptographic value with a corresponding value stored in the DPU memory, thus enabling verification without disk access. For write operations, the system can store write requests in secure on-chip memory while data is being written to memory and, upon reaching a trigger condition, batch process the requests to update an integrity tree structure.This system can offer improved read performance through metadata-based validation and improved write performance through eventual consistency, while maintaining data integrity and security isolation via the DPU.
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