Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device comprising a capacitive MOS element and a MOS transistor element. The capacitive MOS element includes a first doped region formed on a major surface of a semiconductor substrate, a first insulating film formed on the major surface of the semiconductor substrate to cover the first doped region, and a first electrode facing the first doped region, with the first insulating film positioned between them. The MOS transistor element includes a second doped region formed on the major surface of the semiconductor substrate, a second insulating film formed on the major surface of the semiconductor substrate to cover the second doped region, and a second electrode facing the second doped region, with the second insulating film positioned between them.The doping concentration in the first electrode is higher than the doping concentration in the second electrode.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS The disclosure of Japanese patent application No. 2025-025212, filed on February 19, 2025, including the description, drawings and abstract, is incorporated herein by reference in its entirety. BACKGROUND The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. The technique described below is explained below. [Patent Document 1] Japanese Patent Application No. 2007-242660 Patent document 1 describes a capacitive metal oxide semiconductor (MOS) element. The capacitive MOS element of patent document 1 comprises a polysilicon electrode as one electrode, a doped region as the other electrode, and an insulating film between the polysilicon layer and the doped region. The capacitive MOS element of patent document 1 includes a high-concentration region containing a dopant with a higher concentration than the other electrode, thereby shifting the threshold voltage to lower voltages. SUMMARY In the capacitive MOS element of patent document 1, if an insulating film forms on the area with a higher concentration than the other electrode, there is a possibility that the insulating film will thicken due to accelerated oxidation. Consequently, the capacitance of the capacitive MOS element may decrease. Further tasks and novel features will be revealed in the present description and the accompanying drawings. According to one embodiment, a semiconductor device comprises a capacitive MOS element and a MOS transistor element, wherein the capacitive MOS element comprises a first doped region formed in a semiconductor substrate and arranged on a main surface of the semiconductor substrate, a first insulating film formed on the main surface of the semiconductor substrate to cover the first doped region, and a first electrode formed on the first doped region over the first insulating film; the MOS transistor element comprises a second doped region formed in the semiconductor substrate and arranged on the main surface of the semiconductor substrate, a second insulating film formed on the main surface of the semiconductor substrate to cover the second doped region, and a second electrode formed on the second doped region over the second insulating film.and the doping concentration in the first electrode is higher than the doping concentration in the second electrode. According to one embodiment, a method for manufacturing a semiconductor device containing a capacitive MOS element and a MOS transistor element comprises a step of forming a first insulating film and a second insulating film on a main surface of a semiconductor substrate, a step of forming an electrode material having a first section and a second section on the main surface of the semiconductor substrate to cover the first insulating film and the second insulating film, wherein the first section of the electrode material is located on the first insulating film and the second section of the electrode material is located on the second insulating film, a step of forming a first doping region in the semiconductor substrate by implanting a dopant into the first section of the electrode material and a section of the semiconductor substrate located beneath the first section of the electrode material,in a state in which the second section of the electrode material is covered with a mask, and a step of forming a first electrode from the first section and forming a second electrode from the second section by processing the electrode material, wherein the capacitive MOS element contains the first doping region, the first insulating film and the first electrode, and the MOS transistor element contains a second doping region formed in the semiconductor substrate, the second insulating film and the second electrode, wherein a doping concentration in the first electrode is higher than a doping concentration in the second electrode. According to the above embodiment, it is possible to provide a semiconductor device that can improve the capacitance characteristics of a capacitive MOS element, and a method for manufacturing the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view illustrating a capacitive MOS element in a semiconductor device according to a first comparative example. Fig. 2 is a graph illustrating properties of the capacitive MOS element in the semiconductor device according to the first comparative example, where the horizontal axis represents voltage and the vertical axis represents capacitance. Fig. 3 is a cross-sectional view illustrating a capacitive MOS element in a semiconductor device according to a second comparative example. Fig. 4 is a graph illustrating properties of the capacitive MOS element in the semiconductor device according to the second comparative example, where the horizontal axis represents voltage and the vertical axis represents capacitance. Fig. 5 is a cross-sectional view illustrating a capacitive MOS element in a semiconductor device according to a third comparative example.Figure 6 is a cross-sectional view illustrating the capacitive MOS element according to the first comparative example and the capacitive MOS element according to the second comparative example. Figure 7 is a schematic view illustrating the capacitive MOS element of the third comparative example. Figure 8 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. Figure 9 is a top view illustrating details of a capacitive MOS element in the semiconductor device according to the first embodiment and illustrating a major surface of a semiconductor substrate. Figure 10 is a cross-sectional view illustrating details of the capacitive MOS element in the semiconductor device according to the first embodiment and illustrating a cross-section along line AA in Figure 9.Figure 11 is a cross-sectional view illustrating a method for manufacturing the semiconductor device 1 according to the first embodiment. Figure 12 is a cross-sectional view illustrating the method for manufacturing the semiconductor device 1 according to the first embodiment. Figure 13 is a cross-sectional view illustrating the method for manufacturing the semiconductor device 1 according to the first embodiment. Figure 14 is a cross-sectional view illustrating the method for manufacturing the semiconductor device 1 according to the first embodiment. Figure 15 is a cross-sectional view illustrating the method for manufacturing the semiconductor device 1 according to the first embodiment. Figure 16 is a simulation result illustrating a capacitance of a capacitive MOS element of a fourth comparative example.Figure 17 is a simulation result illustrating the capacitance of the capacitive MOS element of the first embodiment. Figure 18 illustrates the capacitances of the capacitive MOS elements of the first embodiment and the fourth comparative example, where the horizontal axis represents a voltage and the vertical axis represents a capacitance. DETAILED DESCRIPTION For the sake of clarity, the following description and drawings have been omitted or simplified where necessary. Hatching or similar markings, even in sectional views, may be omitted from the drawings if they would otherwise make them unclear or if the boundary with a room is unambiguous. The same elements are labeled with the same reference symbols in every drawing, and redundant descriptions are omitted where necessary. Some reference symbols may be omitted to prevent the drawings from becoming too cluttered. In the present description, the fact that a semiconductor has an N-type conductivity means that only electrons are present as charge carriers, or that both electrons and holes are charge carriers, but the electron density is greater than the hole density and the electrons are the dominant charge carriers. In the present description, the fact that a semiconductor has a P-type conductivity means that only holes are present as charge carriers, or that both electrons and holes can be charge carriers, but the hole density is greater than the electron density and the holes are the dominant charge carriers. It should be noted that the N+ type and the P+ type represent an N conductivity type and a P conductivity type, respectively, exhibiting lower resistance than the N type and the P type. The P- type and the N- type represent an N conductivity type and a P conductivity type, respectively, exhibiting higher resistance than the N type and the P type. Therefore, the N type and the P type represent the N conductivity type and the P conductivity type, respectively, exhibiting resistances between those of the N+ type and the P+ type, and those of the P- type and the N- type. The same meaning is assumed hereafter unless otherwise stated. The N-type conductor can be designated as the first conductor type, and the P-type conductor can be designated as the second conductor type. Simultaneously, the N-type conductor can be designated as the second conductor type, and the P-type conductor can be designated as the first conductor type. Furthermore, a semiconductor device in which the conductor types of the respective configurations of this disclosure are reversed is also included within the scope of the technical idea of ​​this disclosure. Additionally, the resistances of the respective N+-type, N-type, and N-type semiconductor layers are examples. Unless otherwise specified, semiconductor layers may exhibit higher or lower resistances than those shown in this disclosure. The ratios of the resistances of the respective N+-type, N-type, and N-type semiconductor layers may be reversed in some cases.Similarly, the resistances of the respective P+ type, P type, and P- type semiconductor layers are given as examples. Unless otherwise stated, semiconductor layers may exhibit higher or lower resistances than those shown in this disclosure. The relative values ​​of the resistances of the respective P+ type, P type, and P- type semiconductor layers may be reversed in some cases. First, semiconductor devices are described in terms of comparative examples, from a FIRST COMPARATIVE EXAMPLE to a THIRD COMPARATIVE EXAMPLE. Then, in the section "Newly Discovered Problems by the Inventor," the problems newly discovered by the inventor relating to the semiconductor devices of the comparative examples are described. Finally, in a FIRST EMBODIMENT, a semiconductor device according to a first embodiment and a method for manufacturing the semiconductor device are described in comparison with each comparative example. In this way, the semiconductor device and the method for manufacturing the semiconductor device according to the present embodiment are clarified. It should be noted that each comparative example and the problems newly discovered by the inventor are also within the scope of the technical idea of ​​the embodiment. FIRST COMPARISON EXAMPLE Fig. 1 is a cross-sectional view illustrating a capacitive MOS element 110 in a semiconductor device according to a first comparative example. As shown in Fig. 1, the capacitive MOS element 110 of the first comparative example comprises an N-type doped region 111, an insulating film 112, an electrode 113, an N-type well region 114, an N+-type doped region 115, wiring 116, and wiring 117. The N-type doped region 111, the N-type well region 114, and the N+-type doped region 115 are formed in a semiconductor substrate 100. The N-type doped region 111 can be referred to as a channel region. For example, a direction orthogonal to a main surface 101 of the semiconductor substrate 100 is a Z-axis direction. Two directions parallel to the main surface 101 of the semiconductor substrate 100 and orthogonal to each other are an X-axis direction and a Y-axis direction. The +Z-axis direction is referred to as "upwards," and the -Z-axis direction as "downwards." It should be noted that the terms "top side" and "bottom side" are used for the clarity of the description of the MOS capacitive element 110 and similar devices and do not indicate the actual orientation of the MOS capacitive element 110 and similar devices. The N-type doping region 111 is formed on the main surface 101 of the semiconductor substrate 100. The N+-type doping region 115 is formed on the main surface 101 of the semiconductor substrate 100. A plurality of N+-type doping regions 115 can be formed. The plurality of N+-type doping regions 115 are configured to enclose the N-type doping region 111 between them. The N-type well region 114 is formed beneath the N-type doping region 111 and the N+-type doping region 115. The N-type well region 114 can be integrated with the N-type doping region 111. That is, the N-type doping region 111 can be part of the N-type well region 114. The insulating film 112 is formed on the main surface 101 of the semiconductor substrate 100. For example, the insulating film 112 is formed on the N-type doping area 111 and on the plurality of N+-type doping areas 115. Electrode 113 is formed over the N-type doping region 111 and the insulating film 112. Therefore, the insulating film 112 is formed between the N-type doping region 111 and electrode 113. Wiring 116 is connected to electrode 113. Electrode 113 contains, for example, polysilicon with N-type doping. Wiring 117 passes through the insulating film 112 and is connected to the N+-type doping region 115. The capacitive MOS element 110 can be operated by applying a voltage between wiring 116 and wiring 117. Fig. 2 is a graph illustrating the properties of the capacitive MOS element 110 in the semiconductor device according to the first comparative example, where the horizontal axis represents a voltage V and the vertical axis represents a capacitance C. As shown in Fig. 2, a change in capacitance occurs in the capacitive MOS element 110 of the first comparative example due to the formation of an inversion layer when a negative voltage and a positive voltage (±voltage) are applied. Therefore, the capacitive MOS element 110 of the first comparative example differs significantly from ideal properties. SECOND COMPARISON EXAMPLE Fig. 3 is a cross-sectional view illustrating a capacitive MOS element 210 in a semiconductor device according to a second comparative example. As shown in Fig. 3, the capacitive MOS element 210 of the second comparative example comprises an N+ type doped region 211, an insulating film 212, an electrode 213, a P type well region 214, an N+ type doped region 215, wiring 216, and wiring 217. The N+ type doped region 211, the P type well region 214, and the N+ type doped region 215 are formed in a semiconductor substrate 200. The N+ type doped region 211 can be referred to as a channel region. The N+ type doping region 211 is formed on a main surface 201 of the semiconductor substrate 200. The N+ type doping region 215 is formed on the main surface 201 of the semiconductor substrate 200. A plurality of N+ type doping regions 215 can be formed. The plurality of N+ type doping regions 215 are configured to enclose the N+ type doping region 211 between them. The P type well region 214 is formed beneath the N+ type doping region 211 and the N+ type doping region 215. The insulating film 212 is formed on the main surface 201 of the semiconductor substrate 200. Electrode 213 is formed over the doping area 211 via the insulating film 212. Therefore, the insulating film 212 is formed between the N+ type doping area 211 and electrode 213. Electrode 213 contains, for example, polysilicon with N type doping. Wiring 216 is connected to electrode 213. Wiring 217 passes through the insulating film 212 and is connected to the N+ type doping area 215. The capacitive MOS element 210 can be operated by applying a voltage between wiring 216 and wiring 217. Figure 4 is a graph illustrating the properties of the capacitive MOS element 210 in the semiconductor device according to the second comparative example, where the horizontal axis represents a voltage V and the vertical axis represents a capacitance C. As illustrated in Figure 4, in the capacitive MOS element 210 of the second comparative example, compared to the capacitive MOS element 110 of the first comparative example, the doping concentration of the N+ type doping region 211 is high, forming a high-concentration channel region. As a result, the capacitive MOS element 210 can shift its threshold voltage to lower voltages. Therefore, the capacitive MOS element 210 operates in an accumulation region. For this reason, the capacitive MOS element 210 possesses the property that the bias dependence can be reduced.The capacitive MOS element 210 of the second comparison example can approach ideal properties. THIRD COMPARISON EXAMPLE Fig. 5 is a cross-sectional view illustrating a capacitive MOS element 310 in a semiconductor device according to a third comparative example. As shown in Fig. 5, the capacitive MOS element 310 of the third comparative example comprises a P-type well region 311, an insulating film 312, an electrode 313, and an N+-type doping region 315. The P-type well region 311 and the N+-type doping region 315 are formed in a semiconductor substrate 300. The insulating film 312 is formed on a major surface 301 of the semiconductor substrate 300. For example, the insulating film 312 is formed on the P-type well region 311. The electrode 313 is formed over the P-type well region 311 and over the insulating film 312. Therefore, the insulating film 312 is formed between the P-type trough area 311 and the electrode 313. The electrode 313 contains, for example, polysilicon with N-type doping.The capacitive MOS element 310 can be operated by applying a voltage between the electrode 313 and the N+ type doping area 315. Newly Discovered Problems by the Inventor Fig. 6 is a cross-sectional view comparing the capacitive MOS element 110 according to the first comparative example and the capacitive MOS element 210 according to the second comparative example. As shown in Fig. 6, in the process of fabricating the capacitive MOS element 210 of the second comparative example, the N+ type doping region 211 is formed in the semiconductor substrate 200 by implanting a high concentration of N-type doping into the semiconductor substrate 200, and then, for example, an oxide film is formed as the insulating film 212. At this point, the thickness of the insulating film 212 can increase due to the accelerated oxidation of the semiconductor substrate 200. In this case, the insulating film 212 of the capacitive MOS element 210 of the second comparison example is thicker than the insulating film 112 of the capacitive MOS element 110 of the first comparison example.As a result, the capacity of the capacitive MOS element 210 of the second comparison example decreases. In particular, if, for example, silicon (Si) is included as semiconductor substrate 100 and semiconductor substrate 200, the N+ type doping region 211 is formed on the upper surface of the silicon, thereby increasing the thickness of the insulating film 212, for example, by a factor of 1.7 due to accelerated oxidation. When the thickness of the insulating film 212 is increased in this way, the capacitance per unit area in the capacitive MOS element 210 of the second comparative example decreases. Fig. 7 is a schematic view illustrating the capacitive MOS element 310 of the third comparative example. In Fig. 7, capacitor symbols are shown in an overlapping manner. As illustrated in Fig. 7, the electrode 313 is formed by implanting a high-concentration dopant into the previously undoped material and subsequently performing an activation temper treatment (annealing). The implantation of the high-concentration dopant into the electrode 313 can be performed simultaneously with the implantation of a dopant to form a source and drain of a MOS transistor. The lower section of the electrode 313 has a lower dopant concentration compared to the upper section of the electrode 313.Therefore, there is a case in which the activation rate of the lower section of electrode 313 decreases due to a small variation in the processing temperature during the activation tempering treatment after dopant implantation. In this case, when a voltage is applied to the capacitive MOS element 310, a depletion layer 318 can form in the lower section of electrode 313. Consequently, the capacitance decreases due to the depletion of electrode 313. First embodiment Next, a semiconductor device 1 according to the present first embodiment is described. One objective of the semiconductor device 1 of the present first embodiment is to solve the problem of forming the inversion layer of the first comparative example, the problem of accelerated oxidation of the insulating film 212 of the second comparative example, and the problem of depletion of the lower section of the electrode 313 of the third comparative example, without increasing the cost. Fig. 8 is a cross-sectional view illustrating the semiconductor device 1 according to the first embodiment. Fig. 9 is a top view illustrating details of a capacitive MOS element 10 in the semiconductor device 1 according to the first embodiment and illustrating a main surface 501 of a semiconductor substrate 500. Fig. 10 is a cross-sectional view illustrating details of the capacitive MOS element 10 in the semiconductor device 1 according to the first embodiment and illustrating a cross-section along line AA in Fig. 9. In Fig. 8, a P+ type contact area 19a for controlling the voltage of a P type well area 14 in the capacitive MOS element 10 is omitted. Fig. 10 illustrates a portion of Fig. 9. As illustrated in Figs. 8, 9 to 10, the semiconductor device 1 of the present first embodiment comprises the capacitive MOS element 10 and a MOS transistor element 20. Although only the N-type MOS transistor element 20 is illustrated in Fig. 8, the semiconductor device 1 may comprise the P-type MOS transistor element 20. The capacitive MOS element 10 comprises an N+ type doped region 11, an insulating film 12, and an electrode 13. The capacitive MOS element 10 may further comprise other elements such as the P type well region 14, an element insulating region 18, an N+ type contact region 19, the P+ type contact region 19a, and an intermediate insulating film 503. The N+ type doped region 11, the P type well region 14, the N+ type contact region 19, and the P+ type contact region 19a are formed in the semiconductor substrate 500. Therefore, the semiconductor substrate 500 comprises the N+ type doped region 11, the P type well region 14, the N+ type contact region 19, and the P+ type contact region 19a. The N+ type doping region 11 is formed on the main surface 501 of the semiconductor substrate 500. The N+ type doping region 11 contains an N type doping. The N+ type doping region 11 is formed within the P type well region 14. The insulating film 12 is formed on the main surface 501 of the semiconductor substrate 500 to cover the N+ type doping region 11. The electrode 13 is formed on the insulating film 12. Therefore, the insulating film 12 is located between the N+ type doping region 11 and the electrode 13. The P type well region 14 is formed beneath the N+ type doping region 11, the N+ type contact region 19, and the P+ type contact region 19a. The P type well region 14 can be located on a P type epitaxy wafer. The electrode 13 is positioned so that it faces the N+ type doping region 11 across the insulating film 12. The electrode 13 contains, for example, an N type dopant. The electrode 13 contains, for example, polysilicon containing an N type dopant. The electrode 13 can comprise a main body section 13a and an extension section 13b. For example, the main body section 13a is positioned over the N+ type doping region 11. The extension section 13b extends from the main body section 13a to a top surface of the element insulating region 18. As described later, an N type dopant cannot be implanted into the extension section 13b. The N type dopant is diffused into the extension section 13b by the activation tempering treatment.Therefore, depending on the activation tempering conditions, the extension section 13b may have a doping concentration lower than that of the main body section 13a. Since the N-type doping is not implanted in the extension section 13b, it is also not implanted in the element insulation region 18. This makes it possible to suppress a decrease in dielectric strength due to the implantation of a highly concentrated dopant in the element insulation region 18. It should be noted that the doping concentrations in the main body section 13a and the extension section 13b can be standardized by the activation tempering treatment. The intermediate insulating film 503 is formed on the main surface 501 to cover the electrode 13. A wire 16, passing through the intermediate insulating film 503, is connected to the extension section 13b. The wire 16 is connected to a section of the extension section 13b that is located above the element insulation area 18. The element insulation region 18 is formed to surround the N+ type doped area 11 of the capacitive MOS element 10. The element insulation region 18 can be formed on the main surface 501 of the semiconductor substrate 500 between the capacitive MOS element 10 and the MOS transistor element 20. The element insulation region 18 is formed to surround an active region in the semiconductor substrate 500. That is, the region surrounded by the element insulation region 18 in the semiconductor substrate 500 is the active region. The N+ type doped area 11 and the N+ type contact area 19 are formed in the active region. The N-type doping region 11 and the element insulation region 18 can be separated from each other. That is, the N-type doping region 11 is formed in an interval from the element insulation region 18 in the X-axis direction and the Y-axis direction within the active region. Part of the P-type trough region 14 can be formed between the N-type doping region 11 and the element insulation region 18. With such a configuration, it is possible to suppress a decrease in dielectric strength due to the implantation of a highly concentrated dopant in the element insulation region 18. It should be noted that part or all of the circumferential edge of the N-type doping region 11 can be in contact with the element insulation region 18. The N+ type contact area 19 is formed on the main surface 501 of the semiconductor substrate 500 between the N+ type doped area 11 and the element insulation area 18. The N+ type contact area 19 is connected to the N+ type doped area 11. The N+ type contact area 19 includes, for example, a section that does not overlap the electrode 13 in the top view. While the N+ type contact area 19 is formed between one end of the N+ type doped area 11 and the element insulation area 18, part of the P type well area 14 is embedded between the other end of the N+ type doped area 11 and the element insulation area 18. The N+ type contact area 19 contains an N type dopant. A wiring 17, which passes through the interlayer insulating film 503, is connected to the N+ type contact area 19. The capacitive MOS element 10 can be operated by applying a voltage between the wiring 16 and the wiring 17. The P+ type contact area 19a is formed on the main surface 501 of the semiconductor substrate 500. The P+ type contact area 19a is surrounded by the element insulation area 18. The P+ type contact area 19a and the N+ type contact area 19 are separated by the element insulation area 18. The P+ type contact area 19a is formed on the P type well area 14. A wiring 17a, which passes through the interlayer insulating film 503, is connected to the P+ type contact area 19a. The P+ type contact area 19a controls the voltage of the P type well area 14. The MOS transistor element 20 comprises a P-type doped area 21, an insulating film 22, an electrode 23, an N+-type doped area 25a, and an N+-type doped area 25b. The MOS transistor element 20 may further comprise a P-type well area 24 and an element insulation area 28. The P-type doped area 21, the N+-type doped area 25a, the N+-type doped area 25b, and the P-type well area 24 are formed in the semiconductor substrate 500. Therefore, the semiconductor substrate 500 comprises the P-type doped area 21, the N+-type doped area 25a, the N+-type doped area 25b, and the P-type well area 24. The P-type doping region 21 is formed on the main surface 501 of the semiconductor substrate 500. The P-type doping region 21 is formed in an active region surrounded by an elemental insulation region 26. The P-type doping region 21 contains a P-type doping. The P-type doping region 21 can be part of the P-type well region 24. The concentration of doping contained in P-type doping area 21 can be lower than the concentration of doping contained in N+-type doping area 11. In other words, the concentration of doping contained in N+-type doping area 11 can be higher than the concentration of doping contained in P-type doping area 21. For example, the concentration of doping contained in N+-type doping area 11 can be twice as high or more than the concentration of doping contained in P-type doping area 21. Furthermore, the concentration of doping contained in N+-type doping area 11 can be two to three times as high as the concentration of doping contained in P-type doping area 21.It should be noted that in the case of the P-type MOS transistor element 20, the ratio between the concentration of doping contained in a later described N-type doping area 21a and the concentration of doping contained in the N+-type doping area 11 is the same as the ratio between the concentration of doping contained in the P-type doping area 21 and the concentration of doping contained in the N+-type doping area 11 described above. The electrode 23 is formed on the insulating film 22. Therefore, the insulating film 22 is positioned between the P-type doping area 21 and the electrode 23. The insulating film 22 is formed on the main surface 501 of the semiconductor substrate 500 to cover the P-type doping area 21. The thickness of the insulating film 22 can be the same as the thickness of the insulating film 12. "Same thickness" in this context means the same thickness, taking into account both measurement errors in determining the thickness and manufacturing errors in the formation of the insulating film 12 and the insulating film 22. The insulating film 12 and the insulating film 22 can be formed simultaneously. Electrode 23 is positioned such that it faces the P-type doping area 21 via the insulating film 22. Electrode 23 contains, for example, N-type doping. The doping concentration in electrode 23 is lower than the doping concentration in electrode 13. In other words, the doping concentration in electrode 13 is higher than the doping concentration in electrode 23. The doping concentration in electrode 13 can be twice or more than the doping concentration in electrode 23. For example, the doping concentration in electrode 13 can be 9.00 × 10¹⁵ or more and 1.10 × 10¹⁶ or less. The doping concentration in electrode 23 can be 3.60 × 10¹⁵ or more and 4.50 × 10¹⁵ or less. Therefore, the doping concentration in electrode 13 can be two to three times the doping concentration in electrode 23.With such a configuration, depletion in the electrode 13 can be suppressed, and a decrease in capacitance due to the capacitive MOS element 10 can be suppressed. The N+ type doping region 25a and the N+ type doping region 25b are formed on the main surface 501 of the semiconductor substrate 500. The N+ type doping region 25a and the N+ type doping region 25b are configured to enclose the P type doping region 21 between them. The N+ type doping region 25a and the N+ type doping region 25b contain N type doping. The N+ type doping region 25a can be, for example, a source region. The N+ type doping region 25b can be, for example, a drain region. It should be noted that the N+ type doping region 25a can be, for example, a collector region. The N+ type doping region 25b can be, for example, an emitter region. The P-type trough area 24 is located beneath the P-type doping area 21, the N+-type doping area 25a, and the N+-type doping area 25b. The P-type trough area 24 can be arranged on a P-type epitaxy wafer. The P-type trough area 24 can be the same as the P-type trough area 14. The element isolation area 28 is formed to surround the P-type doping area 21, the N+-type doping area 25a, and the N+-type doping area 25b. The element isolation area 28 can be formed on the main surface 501 of the semiconductor substrate 500 between the capacitive MOS element 10 and the MOS transistor element 20. The element isolation area 28 is formed to surround the active region of the semiconductor substrate 500 within the MOS transistor element 20. That is, the region surrounded by the element isolation area 28 within the semiconductor substrate 500 is the active region. The P-type doping area 21, the N+-type doping area 25a, and the N+-type doping area 25b are formed within the active region. Next, a method for manufacturing the semiconductor device 1 is described. Figures 11, 12, 13, 14 to 15 are cross-sectional views illustrating a method for manufacturing the semiconductor device 1 according to the first embodiment. As illustrated in Fig. 11, the P-type well region 14, the P-type well region 24, and an N-type well region 24a are formed in the semiconductor substrate 500. The P-type well region 14 and the P-type well region 24 can be integrally formed. For example, the P-type well region 14, the P-type well region 24, and the N-type well region 24a are formed on a P-type epitaxy wafer. The P-type well region 14 is formed in a region of the semiconductor substrate 500 in which the capacitive MOS element 10 is formed. The P-type well region 24 is formed in a region of the semiconductor substrate 500 in which the N-type MOS transistor element 20 is formed. The N-type well area 24a is formed in a region of the semiconductor substrate 500 in which the P-type MOS transistor element 20 is formed. The P-type well area 24 can contain the P-type doping area 21.The N type basin area 24a can contain the N type doping area 21a. Next, as illustrated in Fig. 12, the element isolation region 18 and the element isolation region 28 are formed on the main surface 501 of the semiconductor substrate 500. The element isolation region 18 is formed to isolate the active region of the semiconductor substrate 500, in which the capacitive MOS element 10 is formed, from other regions. The element isolation region 28 is formed to isolate the active region of the semiconductor substrate 500, in which the MOS transistor element 20 is formed, from other regions. Furthermore, an insulating film 52 is formed on the main surface 501 of the semiconductor substrate 500. For example, by thermal oxidation of the main surface 501 of the silicon-containing semiconductor substrate 500, a silicon oxide film is formed as the insulating film 52 on the main surface 501. In the present first embodiment, since the N+ type doping region 11 is not formed on the main surface 501 of the semiconductor substrate 500 in the capacitive MOS element 10, the accelerated oxidation of the insulating film 52 can be suppressed. The insulating film 52 in the region of the semiconductor substrate 500 in which the capacitive MOS element 10 is formed is referred to as insulating film 12. The insulating film 52 in the region of the semiconductor substrate 500 in which the N type MOS transistor element 20 is formed is referred to as insulating film 22.The insulating film 52 in the region of the semiconductor substrate 500 in which the P-type MOS transistor element 20 is formed is referred to as insulating film 22a. The insulating film 12, the insulating film 22, and the insulating film 22a can be formed simultaneously. As described above, before an electrode material is formed on the main surface 501 of the semiconductor substrate 500, the element insulation region 18 and the element insulation region 28 are formed on the main surface 501 of the semiconductor substrate 500. Furthermore, before an electrode material is formed on the main surface 501 of the semiconductor substrate 500, the insulating film 52, including the insulating film 12, the insulating film 22, and the insulating film 22a, is formed. Next, as shown in Fig. 13, an electrode material 53 is formed on the main surface 501 of the semiconductor substrate 500 to cover the insulating film 52. The electrode material 53 can, for example, contain polysilicon. The polysilicon is preferably formed so that it contains no doping. Next, an N-type dopant is implanted into a portion of the electrode material 53. This portion of the electrode material 53 contains a section that will be formed as the electrode 13 in a later step. For example, an N-type dopant is implanted through a mask that covers the other portion of the electrode material 53 and leaves the portion (electrode 13) of the electrode material 53 exposed. The N-type dopant is not only implanted into the portion (electrode 13) of the electrode material 53, but also into the main surface 501 of the semiconductor substrate 500, which faces the portion (electrode 13) of the electrode material 53 through the electrode material 53 and the insulating film 12. Therefore, the N+-type doping region 11 is formed on the main surface 501 of the semiconductor substrate 500. The N+ type doping area 11 is formed in the P type trough area 14. In the present first embodiment, after the deposition of the electrode material 53, such as polysilicon, the implantation (gate through-hole plating) of a dopant into the channel region and the pre-doping of the electrode material 53 are carried out simultaneously. As a result, the accelerated oxidation of the insulating film 12 and the depletion of the electrode 13 can be suppressed, and the capacitance characteristics can be improved. As described above, in the present first embodiment, by implanting an N-type dopant into a portion (electrode 13) of the electrode material 53 and the main surface 501 of the semiconductor substrate 500, which faces the portion (electrode 13) of the electrode material 53 via the insulating film 52, the electrode 13 is formed in a portion of the electrode material 53, and the N+-type doping region 11 is formed. The activation tempering treatment can then be carried out. When the N+ type doping region 11 is formed, the N+ type doping region 11 and the element isolation region 18 can be separated from each other. For example, the mask covers the element isolation region 18, and an opening left in the mask can be so small that it is contained within the active area surrounded by the element isolation region 18. By introducing the N type doping with such a mask, the N+ type doping region 11 and the element isolation region 18 can be separated from each other. Next, as shown in Fig. 14, the electrode material 53 is processed into the electrode 13, the electrode 23, and an electrode 23a. For example, a mask with openings corresponding to sections of the electrode material 53 other than the electrode 13, the electrode 23, and the electrode 23a is placed on the electrode material 53, and the electrode material 53 is etched such that the sections other than the electrode 13, the electrode 23, and the electrode 23a are removed. Thus, the electrode material 53 is processed into the electrode 13, the electrode 23, and the electrode 23a. As described above, in the present first embodiment, the sections other than the electrode 13, the electrode 23, and the electrode 23a are removed from the electrode material 53 to form the electrode 13, the electrode 23, and the electrode 23a. Next, as shown in Fig. 15, the N+ type contact area 19, the N+ type doping area 25a, and the N+ type doping area 25b are formed. For example, the N type doping is implanted into the semiconductor substrate 500 by means of a mask that covers an area where the P type MOS transistor element 20 is formed and has openings into an area where the capacitive MOS element 10 and the N type MOS transistor element 20 are formed. As a result, the N+ type contact area 19, which contains N type doping, is formed in a section of the semiconductor substrate 500 between the N+ type doping area 11 and the element insulation area 18, without overlapping the electrode 13. Furthermore, the N+ type doping region 25a and the N+ type doping region 25b on the main surface 501 of the semiconductor substrate 500 are formed such that they enclose the P type doping region 21 between them.In this step, an N-type doping can be implanted into electrode 13 and electrode 23. Afterwards, the activation temper treatment can be performed. Furthermore, a P+ type doping region 25c and a P+ type doping region 25d are formed. For example, a P type dopant is implanted into the semiconductor substrate 500 by means of a mask that covers an area where the capacitive MOS element 10 and the N type MOS transistor element 20 are formed, and has openings into an area where the P type MOS transistor element 20 is formed. This forms the P+ type doping region 25c and the P+ type doping region 25d on the main surface 501 of the semiconductor substrate 500 such that they enclose the N type doping region 21a between them. In this step, a P type dopant can be implanted into the electrode 23a. After that, the activation tempering treatment can be performed. The N+ type doping region 11 is formed on the main surface 501 of the semiconductor substrate 500 such that it faces electrode 13. The P type doping region 21 is formed on the main surface 501 of the semiconductor substrate 500 such that it faces electrode 23. The N type doping region 21a is formed on the main surface 501 of the semiconductor substrate 500 such that it faces electrode 23a. The insulating film 52 between the N+ type doping area 11 and the electrode 13 is the insulating film 12. The insulating film 52 between the P type doping area 21 and the electrode 23 is the insulating film 22. The insulating film 52 between the N type doping area 21a and the electrode 23a is the insulating film 22a. In this way, the semiconductor device 1 of the present first embodiment, including the capacitive MOS element 10, the N type MOS transistor element 20, and the P type MOS transistor element 20, can be manufactured. The capacitive MOS element 10 contains the N+ type doping area 11, the insulating film 12, and the electrode 13. The N type MOS transistor element 20 contains the P type doping area 21, the insulating film 22, the electrode 23, the N+ type doping area 25a, and the N+ type doping area 25b. The P type MOS transistor element 20 contains the N type doping area 21a, the insulating film 22a, the electrode 23a, the P+ type doping area 25c, and the P+ type doping area 25d. Next, the effects of the present first embodiment are described. The capacitive MOS element 10 of the present first embodiment contains the N+ type doping region 11, which has a higher concentration of doping in a channel region compared to the capacitive MOS element 110 of the first comparative example. Therefore, the capacitive MOS element 10 of the present first embodiment can shift a threshold voltage to lower voltages and can operate in the accumulation region. This reduces the bias dependence of the capacitive MOS element 10, independent of the voltage condition. Furthermore, in the capacitive MOS element 10 of the present first embodiment, the insulating film 12 is not formed after doping with a higher concentration is implanted into the channel region. In the capacitive MOS element 10 of the present first embodiment, the insulating film 12 is formed before the N+ type doping region 11 is formed. Therefore, the capacitive MOS element 10 of the present first embodiment can suppress an increase in the thickness of the insulating film 12 due to accelerated oxidation. As a result, the capacitance characteristics of the capacitive MOS element 10 can be improved compared to the capacitive MOS element 210 of the second comparative example. Furthermore, in the present first embodiment, doping is simultaneously implanted into the section of the electrode 13 of the electrode material 53 and the N+ type doping area 11, which is arranged on the main surface 501 of the semiconductor substrate 500. As a result, compared to the capacitive MOS element 310 of the third comparative example, the accelerated oxidation of the insulating film 12 and the depletion of the electrode 13 can be suppressed, and the capacitance characteristics of the capacitive MOS element 10 can be improved. Fig. 16 is a simulation result illustrating the capacitance of a capacitive MOS element 410 of a fourth comparison example. Fig. 16 also illustrates a structure of the capacitive MOS element 410 of the fourth comparison example. As shown in Fig. 16, the capacitive MOS element 410 of the fourth comparison example comprises an N+ type doped region 411, an insulating film 412, and an electrode 413. The N+ type doped region 411 is formed on a main surface 401 of a semiconductor substrate 400. The insulating film 412 and the electrode 413 are formed on the main surface 401 of the semiconductor substrate 400. The N+ type doped region 411 is formed in an active region surrounded by an element insulating region 418.In the capacitive MOS element 410 of the fourth comparative example, the N+ type doping region 411 is formed by implanting an N-type dopant into the main surface 401 of the semiconductor substrate 400, and then the insulating film 412 is formed. Also in the capacitive MOS element 410 of the fourth comparative example, the implantation of the N-type dopant into the electrode 413 is omitted beforehand to suppress depletion of the electrode 413. In the fourth comparative example, the insulating film 412 becomes thicker due to accelerated oxidation. Furthermore, the lower section of the electrode 413 becomes depleted. Fig. 17 is a simulation result illustrating the capacitance of the capacitive MOS element 10 of the first embodiment. Fig. 17 also illustrates a structure of the capacitive MOS element 10 of the first embodiment. As illustrated in Fig. 17, the capacitive MOS element 10 of the first embodiment can suppress the accelerated oxidation of the insulating film 12. Furthermore, the capacitive MOS element 10 of the first embodiment can suppress the depletion of the lower section of the electrode 13. Fig. 18 is a graph illustrating the capacitances of the capacitive MOS element 10 of the first embodiment and the capacitive MOS element 410 of the fourth comparative example, where the horizontal axis represents a voltage V and the vertical axis represents a capacitance C. As illustrated in Fig. 18, the capacitive MOS element 10 of the present first embodiment can improve a capacitance value by 28% or more compared to the capacitive MOS element 410 of the fourth comparative example. Although the invention made by the present inventor has been specifically described with reference to the embodiment, the present invention is not limited to the embodiment mentioned above. It is self-evident that various modifications can be made, as long as they do not deviate from the essential idea of ​​the present invention. For example, suitable combinations of the configurations of the first comparative example with the fourth comparative example and the first embodiment are also within the scope of the technical idea of ​​the embodiment. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature JP 2025-025212

[0001] JP 2007-242660

[0004]

Claims

A semiconductor device comprising: a capacitive MOS element; and a MOS transistor element, wherein the capacitive MOS element comprises: a first doped region formed in a semiconductor substrate and arranged on a major surface of the semiconductor substrate; a first insulating film formed on the major surface of the semiconductor substrate to cover the first doped region; and a first electrode formed on the first doped region over the first insulating film, wherein the MOS transistor element comprises: a second doped region formed in the semiconductor substrate and arranged on the major surface of the semiconductor substrate; a second insulating film formed on the major surface of the semiconductor substrate to cover the second doped region;and a second electrode formed on the second doping area over the second insulating film, wherein a doping concentration in the first electrode is higher than a doping concentration in the second electrode. The semiconductor device according to claim 1, wherein the doping concentration in the first electrode is twice or more than the doping concentration in the second electrode. The semiconductor device according to claim 1, wherein a doping concentration in the first doping area is higher than a doping concentration in the second doping area. The semiconductor device according to claim 1, wherein the thickness of the first insulating film is the same as the thickness of the second insulating film. The semiconductor device according to claim 1, wherein the first doping region contains a doping of a first conductivity type, wherein the first electrode contains a doping of the first conductivity type, wherein the second doping region contains a doping of a second conductivity type opposite to the first conductivity type, wherein the second electrode contains a doping of the first conductivity type, wherein the capacitive MOS element further comprises a first well region of the second conductivity type formed in the semiconductor substrate, wherein the first doping region is formed in the first well region, and wherein the MOS transistor element comprises: a third doping region of the first conductivity type and a fourth doping region of the first conductivity type formed in the semiconductor substrate, arranged on the main surface of the semiconductor substrate and configured in such a way as tothat they enclose the second doping region between them; and a second well region of the second conductivity type formed in the semiconductor substrate and located below the second doping region, the third doping region, and the fourth doping region. The semiconductor device according to claim 1, further comprising an element isolation region formed in the semiconductor substrate and arranged on the main surface of the semiconductor substrate, wherein the element isolation region surrounds the first doping region in the top view. The semiconductor device according to claim 6, wherein the first doping area and the element isolation area are separated from each other. The semiconductor device according to claim 6, wherein the capacitive MOS element further comprises a contact area formed in the semiconductor substrate and arranged on the main surface of the semiconductor substrate and between the first doping area and the element insulation area, wherein the contact area contains a doping of a first conductivity type, and wherein the first doping area is electrically connected to the contact area. The semiconductor device according to claim 6, wherein the first electrode comprises: a main body section arranged above the first doping region; and an extension section extending from the main body section to a top surface of the element insulation region. The semiconductor device according to claim 9, wherein the extension section has a doping concentration that is lower than a doping concentration in the main body section. A method for manufacturing a semiconductor device, including a capacitive MOS element and a MOS transistor element, wherein the method comprises: forming a first insulating film and a second insulating film on a major surface of a semiconductor substrate; forming an electrode material on the major surface of the semiconductor substrate to cover the first insulating film and the second insulating film, wherein the electrode material has a first section and a second section; wherein the first section of the electrode material is arranged on the first insulating film and the second section of the electrode material is arranged on the second insulating film;Forming a first doping region in the semiconductor substrate by implanting a dopant into the first section of the electrode material and a section of the semiconductor substrate located beneath the first section of the electrode material, in a state where the second section of the electrode material is covered by a mask; and forming a first electrode from the first section and forming a second electrode from the second section by processing the electrode material, wherein the capacitive MOS element contains the first doping region, the first insulating film, and the first electrode, and wherein the MOS transistor element contains a second doping region arranged in the semiconductor substrate, the second insulating film, and the second electrode, and wherein a doping concentration in the first electrode is higher than a doping concentration in the second electrode. The method according to claim 11, wherein the doping concentration in the first electrode is twice or more the doping concentration in the second electrode. The method according to claim 11, wherein a doping concentration in the first doping area is higher than a doping concentration in the second doping area. The method according to claim 11, wherein the thickness of the first insulating film is the same as the thickness of the second insulating film. The method according to claim 11, further comprising: before the first insulating film and the second insulating film are formed, forming a first well region of a second conductivity type opposite to a first conductivity type and a second well region of the second conductivity type in the semiconductor substrate; and after the formation of the first electrode and the second electrode, forming a third doping region of the first conductivity type and a fourth doping region of the first conductivity type in the second well region by implanting a dopant into the first electrode, the second electrode and the semiconductor substrate, wherein the first doping region contains a dopant of the first conductivity type, wherein the first electrode contains a dopant of the first conductivity type, and wherein the second doping region contains a dopant of the second conductivity type.wherein the second electrode contains a doping of the first conductivity type, wherein the first doping region is formed in the first well region, wherein the capacitive MOS element further contains the first well region, wherein the third doping region and the fourth doping region are arranged on the main surface of the semiconductor substrate such that they enclose the second doping region between them, and wherein the MOS transistor element contains the third doping region, the fourth doping region and the second well region. The method according to claim 11, further comprising: forming an element isolation region in the semiconductor substrate and on the main surface of the semiconductor substrate prior to forming the electrode material, wherein the element isolation region surrounds the first doping region in the top view. The method according to claim 16, wherein the first doping region is formed in such a way as to be separated from the element isolation region during the formation of the first doping region. The method according to claim 15, further comprising: forming an element isolation region in the semiconductor substrate and on the main surface of the semiconductor substrate prior to the formation of the electrode material, wherein the element isolation region surrounds the first doping region, wherein a contact region is formed in the semiconductor substrate by implanting the dopant into the semiconductor substrate during the formation of the third doping region and the fourth doping region, wherein the contact region is arranged on the main surface of the semiconductor substrate and between the first doping region and the element isolation region, wherein the contact region contains a dopant of the first conductivity type, and wherein the first doping region is electrically connected to the contact region. The method according to claim 16, wherein the first electrode comprises: a main body section arranged above the first doping region; and an extension section extending from the main body section to a top surface of the element insulation region. The method according to claim 19, wherein the extension section has a doping concentration that is lower than a doping concentration in the main body section.

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