MEMORY SHIFT CIRCUIT

Abstract

An exemplary memory device comprises a repair cell in a repair column with a local repair bit line, a local input / output repair circuit (LIO repair circuit) with an input connected to the local repair bit line and an output connected to a global repair bit line, and multiple memory cells arranged in multiple first columns. The memory device further comprises an LIO memory circuit and a first global input / output circuit (GIO circuit), comprising a first multiplexer with a first input connected to the global memory bit line, a second input connected to receive the output of the LIO repair circuit, an output terminal, and a select signal terminal. The first GIO circuit further comprises a first comparator circuit.