Processor, system, method and machine-readable medium for performing a shift and exclusive-OR operation in a single instruction

Abstract

Processor, comprising: a decoder configured to recognize instructions of an instruction set comprising a single instruction, multiple data, SIMD shift, and XOR instruction; Logic for performing the SIMD shift and XOR instruction having a first source operand for specifying or storing a first value, a second source operand for specifying or storing a shift amount, and a third source operand for specifying or storing a second value, wherein, in response to the SIMD shift and XOR instruction, the first value is shifted by the shift amount and the shifted value is XORed with the second value to produce a result of the SIMD shift and XOR instruction; and Logic to perform a check to see whether a number of consecutive leading zeros in the result is equal to or greater than a prescribed number.

Description

Field of the InventionThe present disclosure relates to a processor, system, method, and machine readable medium for performing a shift and exclusive OR operation in a single instruction.Description of Related ArtSingle instruction multiple data (SIMD) instructions are useful in various applications for parallel processing of numerous data elements (packed data). Performing operations such as a shift operation and an exclusive-OR (XOR) operation in series may reduce performance.The article "Enhancing Embedded Processors with Specific Instruction Set Extensions for Network Applications" by A. Chormoviit et al., IEEE Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 5-7 September 2005, Sofia, Bulgaria discloses the extension of the instruction set of a MIPS processor for realizing network applications and a new Application Specific Instruction Set Processor (ASIP). New instructions include a "SHIFT;XOR instruction.".US 2008 / 0 301 134 A1 describes a sample-based method for removing duplicate data (deduplication) stored on memory resources. When a new dataset, e.g., a backup data stream, is received from a server, e.g., a storage system or a virtual tape library (VTL) system implementing the invention, one or more anchors within the new dataset are identified. The anchors are identified using a novel anchor detection circuit in accordance with an illustrative embodiment of the present invention. After receiving the new record, for example, by a network adapter of a VTL system, the record is created using direct memory access operations(DMA) to a memory connected to an anchor detection hardware card operatively connected to the memory system. The anchor detection hardware card may be implemented, for example, as an FPGA to quickly identify anchors within the dataset. Since the anchor detection process is supported by hardware, the load on the system's main processor is reduced, thereby enabling line speed deduplication.US 2002 / 0 152 218 A1 describes a system and method for unordinated determination of data sequences using sticky byte factorization to determine fractures in digital sequences so that common sequences can be identified. Sticky byte factorization provides an efficient method of dividing a data set into parts that generally gives near optimum sharing. This is accomplished by using a rolling hash sum and, in an exemplary embodiment disclosed herein, a threshold function to deterministically determine divisions in a data sequence. Both the rolling hash sum and the threshold function are designed to require only minimal computations. This low overhead allows for rapid partitioning of a data sequence for presentation to a factorization engine or other applications that prefer subsequent synchronization across the dataset.Sung Dae Kim [et al.]: Novel bit manipulation unit for communication digital signal processors. Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04. Vancouver, BC: IEEE, 2004. S. II3858 Vol. 2. ISBN 07803-8251X presents application specific commands and their bit manipulation unit (BMU) that efficiently support scrambling, convolutional coding, pactuing, and interleaving. The proposed DSP uses the BMU that supports parallel shift and XOR (exclusive-OR) operations as well as bit insert / extract operations for multiple data. The architecture was modeled with VHDL and synthesized using the SEC 0.18 μm standard cell biblio-thek. The gate number of the BMU is only about 1700 gates. Power comparisons show that the number of clock cycles for scrambling, convolutional coding, and interleaving can be reduced by about 40% to 80% compared to existing DSPs.US 2006 / 0 282 743 A1 describes a technique for carrying out multiplications without carry and bit mirroring operations. Embodiments include an instruction to perform a carry-out multiplication and an instruction to perform a bit mirroring operation.US 2009 / 0 158 132 A1 describes, in one aspect, a circuit for determining a modular remainder with respect to a polynomial of a message which consists of a series of segments. In another aspect, it is a circuit for accessing at least a portion of a first number having a first endian format, determining a second number based on a bit reflection and a shift of a third number having an endian format opposite the first endian format, and performing polynomial multiplication of the first number and the at least a portion of the first number.It is the object of the invention to provide an instruction with which the increase in the performance of a computer system and, in particular, parallel processing of a large number of data elements can be achieved.The object is achieved by the subject matters of the independent claims. Embodiments of the invention are set forth in the dependent claims.Brief Description of the FiguresThe present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings: FIG. 1A is a block diagram of a computer system formed with a processor including execution units to execute an instruction for a shift and XOR operation according to an embodiment of the invention; FIG. 1B is a block diagram of another exemplary computer system in accordance with an alternative embodiment of the present invention; FIG. 1C is a block diagram of yet another exemplary computer system in accordance with another alternative embodiment of the present invention; FIG. 2 is a block diagram of the microarchitecture for a processor of an embodiment including logic circuitry for performing a shift and XOR operation, in accordance with the present invention; FIG. 3A illustrates various packed data type representations in multimedia registers according to an embodiment of the present invention; FIG. 3B illustrates various packed data types, according to an alternative embodiment; FIG. 3C illustrates various representations of packed data types with and without signs in multimedia registers according to an embodiment of the present invention; FIG. 3D illustrates an embodiment of an operation coding (opcode) format; FIG. 3E illustrates an alternative operation coding (opcode) format; FIG. 3F illustrates yet another alternative operation coding (opcode) format; FIG. 4 is a block diagram of one embodiment of logic for performing an instruction in accordance with the present invention; FIG. 5 is a flow diagram of operations to be performed in connection with an embodiment.Detailed DescriptionThe following description describes embodiments of a technique for performing a shift and XOR operation in a processing device, computer system, or software program. In the following description, numerous specific details are set forth, such as processor types, microarchitectural conditions, events, activation mechanisms, and the like, in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that embodiments of the inventions may be practiced without such specific details. In addition, some well-known structures, circuits, and the like have not been shown in detail to avoid unnecessarily obscuring embodiments of the present invention.Although the following embodiments are described with reference to a processor, other embodiments are applicable to other types of integrated circuits and logic devices. The same techniques and teachings of the present invention may be easily applied to other types of circuits or semiconductor devices that may benefit from higher pipeline throughput and improved performance. The teachings of the present invention are applicable to any processor or machine that performs data manipulations. However, embodiments of the present invention are not limited to processors or machines that perform 256 bit, 128 bit, 64 bit, 32 bit, or 16 bit data operations and may be applied to any processor and machine in which manipulation of packed data is needed.Although the following examples describe handling and distribution of instructions in the context of execution units and logic circuits, other embodiments of the present invention may be achieved using software stored on a tangible medium. In one embodiment, the methods of the present invention are embodied in machine-executable instructions. The instructions may be used to cause a general purpose computer or a specialized computer programmed with the instructions to perform the steps of the present invention.Embodiments of the present invention may be provided as a computer program product or software, which may comprise a machine- or computer-readable medium comprising instructions stored thereon, which may be used to program a computer (or other electronic devices) to perform a process according to the present invention. Alternatively, the steps of the present invention could be performed by special purpose hardware components that include hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components. Such software may be stored in a memory in the system. Similarly, the code may be distributed over a network or using other computer readable media.Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), and is not limited to floppy diskettes, optical disks, compact disks, read-only memories (CDROMs), and magneto-optical disks, read-only memories (ROMs), random access memories (RMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EPROMs), magnetic or optical cards, flash memories, Internet transmission, electrical, optical, acoustical or other forms of propagating signals (e.g., carrier waves, infrared signals, digital signals, etc.), or the like. Accordingly, the computer-readable medium includes any type of media / machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer). Moreover, the present invention may also be downloaded as a computer program product. As such, the program may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client). The transfer of the program may be via an electrical, optical, acoustic, or other form of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem, network connection, or the like).A design may go through various stages from creation to simulation and fabrication. Data representing a design may represent the design in a number of ways. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and / or transistor gates may be generated at some stages of the development process. Moreover, at a stage, most designs reach a data plane representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on various mask layers for masks used for manufacturing the integrated circuit. In any representation of the design, the data may be stored in any form on a machine readable medium. The machine readable medium may be an optical or electrical wave modulated or otherwise generated to transmit such information, a memory, or a magnetic or optical memory such as a disk. Each of these media may "carry" or "display" the design or software information. When an electric carrier wave carrying or indicating the code or the design is transmitted to the extent that copying, buffering, or retransmission of the electric signal is performed, a new copy is made. Thus, a communication provider or a network provider may make copies of an article (a carrier wave) embodying techniques of the present invention.In modern processors, a number of different execution units are used to process and execute a variety of code and instructions. Not all instructions are generated the same, as some are to be executed more quickly, while others may require a tremendous number of clock cycles. The faster the throughput of instructions, the better the overall performance of the processor. It would thus be advantageous to have as many instructions as possible that execute as quickly as possible. However, there are certain instructions that are more complex and require more execution time and processor resources. For example, there are floating point instructions, load / store operations, data moves, etc.As more and more computer systems are used in Internet and multimedia applications, additional support has been introduced over time for the processor. For example, single instruction, multiple data (SIMD) integer / floating point instructions, and streaming SIMD extensions (SSE) instructions are instructions that reduce the total number of instructions required to execute a particular program task, which in turn may reduce power consumption. These instructions may increase the performance of the software by operating in parallel on multiple data elements. As a result, performance enhancements can be achieved in a wide range of applications including video, voice and image / photo processing. The implementation of SIMD instructions in microprocessors and similar types of logic circuits usually involve a number of aspects. Moreover, the complexity of SIMD operations often results in a need for additional circuitry to properly manipulate and manipulate the data.Currently, a SIMD shift and XOR instruction is not available. Without the existence of a SIMD shift and XOR instruction according to embodiments of the present invention, a large number of instructions and data registers may be required to achieve the same results in applications such as audio / video / graphics compression, editing, and manipulation.Thus, at least one shift and XOR instruction according to embodiments of the present invention may reduce code overhead and resource requirements. Embodiments of the present invention provide a way to implement a shift and XOR operation as an algorithm that makes use of SIMD-related hardware. Currently, it is difficult and awkward to perform shift and XOR operations on data in a SIMD register. Some algorithms require more instructions to arrange data for arithmetic operations than the actual number of instructions to perform these operations. By implementing embodiments of a shift and XOR operation according to embodiments of the present invention, the number of instructions required to achieve shift and XOR processing can be drastically reduced.Embodiments of the present invention include an instruction to implement a shift and XOR operation. In one embodiment, a shift and XOR operation...A shift and XOR operation may be generically represented as applied to data elements, according to one embodiment:In one embodiment, SRC1 stores a first operand having a plurality of data elements and SRC2 contains a value representing the value to be shifted by the shift and XOR instruction. In other embodiments, the shift and XOR value indicator may be stored in an immediate field.In the above flow, "DEST" and SRC" are generic labels to represent the source and destination of the corresponding data or operation. In some embodiments, they may be implemented by registers, memories, or other memory areas with different names or functions than those depicted. For example, in one embodiment, DEST1 and DEST2 may be first and second temporary storage areas (e.g., "TFMP1" and TEMP2" registers), SRC1 and SRC3 may be first and second target storage areas (e.g., "DEST1" and "DEST2" registers), etc. In other embodiments, two or more of the SRC and DEST storage areas may correspond to different data storage elements in the same storage area (e.g., a SIMD register).FIG. 1a is a block diagram of an exemplary computer system formed with a processor including execution units to execute an instruction for a shift and XOR operation, in accordance with an embodiment of the present invention. The system 100 includes a component, such as a processor 102, to use execution units including logic to perform algorithms for processing data in accordance with the present invention, such as in the embodiment described herein. The system 100 represents processing systems based on the Pentium III, Pentium IV, Xeon, Itanium, XScale, and / or StrongARM microprocessors available from Intel Corporation of Santa Barbara, California, although other systems (including PCs with other microprocessors, development workstations, set-top boxes, and the like) may also be used. In one embodiment, the sample system 100 may execute a version of the Windows operating system available from Microsoft Corporation of Redmont, Washington, although other operating systems (Unix and Linux, for example), embedded software, and / or graphical user interfaces may also be used. Thus, the embodiments of the present invention are not limited to a specific combination of hardware circuits and software.Embodiments are not limited to computer systems. Alternative embodiments of the present invention may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and portable PCs. Embedded applications may include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that performs shift and XOR operations on operands. Moreover, some architectures have been implemented to enable instructions to operate on multiple data simultaneously to improve the efficiency of multimedia applications. As data types and data volume increase, computers and their processors have been improved to manipulate data in more efficient methods.FIG. 1a is a block diagram of a computer system 100 configured with a processor 102 that includes one or more execution units 108 to perform an algorithm to shift a number of data elements and combine XORs according to an embodiment of the present invention. An embodiment may be described in the context of a single processor desktop or server system, however alternative embodiments may be included in a multiprocessor system. System 100 is an example of a hub architecture. The computer system 100 includes a processor 102 for processing data signals, the processor 102 may be a complex instruction set computer microprocessor (CISC), a reduced instruction set microprocessor (RISC), a very long instruction word microprocessor (VLIW), a processor implementing a combination of instruction sets, or any other processor device such as a digital signal processor. Processor 102 is coupled to a processor bus 110 that may transmit data signals between processor 102 and other components in system 100. The elements of system 100 perform their conventional functions well known to those skilled in the art.In one embodiment, processor 102 includes level 1 (L1) internal cache 104. Depending on the architecture, processor 102 may include a single internal cache or multiple levels of internal caches. Alternatively, in another embodiment, the cache memory may be external to the processor 102. Other embodiments may also include a combination of both internal and external caches depending on the particular implementation and need. The register file 106 may include different types of data in various registers including integer registers, floating point registers, status registers, and instruction pointer registers.Execution unit 108, which includes logic to perform integer and floating point operations, is also located in processor 102. The processor 102 also includes microcode (μcode) ROM that stores microcode for certain microinstructions. For this embodiment, execution unit 108 includes logic to handle a packed instruction set 109. In one embodiment, the packed instruction set 109 includes a packed shift and XOR instruction for performing a shift and XOR combination on a number of operands. By including the packed instruction set 109 in the instruction set of a general purpose processor 102, along with circuitry associated therewith, to execute the instruction, the operations used by many multimedia applications may be performed using packed data in a general purpose processor 102. Thus, many multimedia applications can be accelerated and executed more efficiently using the entire width of a processor data bus to perform operations on packed data. This may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations with a data element at a time.Alternative embodiments of execution unit 108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuitry. The system 100 includes a memory 120. The memory 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or another memory device. The memory 120 may store instructions and / or data represented by data signals executable by the processor 102.A system logic chip 116 is coupled to the processor bus 110 and the memory 120. The system logic chip 116 is a memory controller hub (MCH) in the illustrated embodiment. The processor 102 may communicate with the MCH 116 via a processor bus 110. The MCH 116 provides a high bandwidth storage path 118 to the memory 120 for instruction and data storage and for storage of graphics commands, data, and textures. The MCH 116 routes data signals between the processor 102, the memory 120, and other components in the system 100, and bridges the data signals between the processor bus 110, the memory 120, and the system I / O 122. In some embodiments, system logic chip 116 may provide a graphics port for coupling to a graphics controller 112. The MCH 116 is coupled to a memory 120 through a memory interface 118. The graphics card 112 is coupled to the MCH 116 via an accelerated graphics port (AGP) interconnect 114.The system 100 uses a proprietary hub interface bus 122 to couple the MCH 116 to the I / O controller hub ((CH) 130. The ICH 130 provides direct connections to some I / O devices via a local I / O bus. The local I / O bus is a high speed I / O bus for connecting peripheral devices to memory 120, chipset, and processor 102. Some examples are the audio controller, firmware hub (flash BIOS), wireless transceiver 126, data storage 124, legacy I / O controller containing user input and keyboard interfaces, serial expansion port such as a universal serial bus (USB), and network controller 134. The data storage device 124 may include a disk drive, a floppy disk drive, a CDROM device, a flash memory device, or other mass storage devices.In another embodiment of a system, an execution unit may be used to execute an algorithm with a shift and XOR instruction with a system on a chip. An embodiment of a system on a chip includes a processor and a memory. The memory for such a system is flash memory. Flash memory may be on the same chip as the processor and other system components. In addition, other logic blocks, such as a memory controller or a graphics controller, may also reside on a system on a chip.FIG. 1B illustrates a data processing system 140 implementing the principles of an embodiment of the present invention. It will be readily appreciated by those skilled in the art that the embodiments described herein may be used with alternative processing systems without departing from the scope of the invention.The computer system 140 includes a processing core 159 adapted to perform SIMD operation including a shift and XOR operation. For one embodiment, processing core 159 represents a processing unit of any type of architecture, including, but not limited to, a CISC, a RISC, or a VLIW type of architecture. The processing core 159 may also be suitable for manufacture by one or more process technologies and may be suitable for simplified manufacture when played back on a machine readable medium with sufficient detail.The processing core 159 includes an execution unit 142, a set of register files 145, and a decoder 145. The processing core 159 also includes additional circuitry (not shown) that is not necessary for understanding the present invention. The execution unit 142 is used to execute instructions received from the processing core 159. In addition to detecting typical processor instructions, execution unit 142 may also detect instructions in a packed instruction set 143 to perform operations on packed data formats. The packed instruction set 143 includes instructions to support shift and XOR operations, and may also include other packed instructions. Execution unit 142 is coupled to register file 145 through an internal bus. Register file 145 represents a storage area on processing core 159 for storing information including data. As mentioned previously, it will be understood that the storage area used to store the packed data is not critical. Execution unit 142 is coupled to decoder 144. Decoder 144 is used to decode instructions received from processing core 159 into control signals and / or microcode entry points. In response to these control signals and / or microcode entry points, execution unit 142 performs the appropriate operations.The processing core 159 is coupled to the bus 141 for communication with various other system devices, which may include, but are not limited to, synchronous dynamic random access memory (SDRAM) controller 146, static random access memory (SRAM) controller 147, burst flash memory interface 148, personal computer memory card international association (PCMCIA) / compact flash (CF) card controller 149, liquid crystal display (LCD) controller 150, random access memory (DMA) controller 151, and alternative bus master interface 152. In one embodiment, data processing system 140 may also include an I / O bridge 154 to communicate with various I / O devices via an I / O bus 153. Such I / O devices may include, for example, but are not limited to, a universal asynchronous receiver / transmitter (UART) 155, a universal serial bus (USB) 156, a bluetooth wireless UART 157, and an I / O expansion interface 158.One embodiment of data processing system 140 provides for mobile, network, and / or wireless communications, and processor core 159 is capable of performing SIMD operations including a shift and XOR operation. The processing core 159 may be programmed with various audio, video, imaging and communication algorithms including discrete transformations such as a Walsh-Hadamard transformation, a fast Fourier transformation (FFT), a discrete cosine transformation (DCT), and their corresponding inverse transformations; compression-compression techniques such as color space transformation, video encoding motion estimation or video decoding motion compensation; and modulation-demodulation (MODEM) functions such as pulse-encoded modulation (PCM). Some embodiments of the invention may also be applied to graphics applications such as three-dimensional ("3D") modeling, rendering, object collision detection, 3D object transformation and illumination, etc.Figure 1C illustrates still other alternative embodiments of a data processing system suitable for performing SIMD shift and XOR operations. According to an alternative embodiment, a data processing system 160 may include a main processor 166, a SIMD coprocessor 161, a cache memory 167, and an input / output system 168. The input / output system 168 may optionally be coupled to a wireless interface 169. The SIMD coprocessor 161 is adapted to perform SIMD operations including shift and XOR operations. The processing core 170 may be suitable for manufacture with one or more processing technologies and for presentation on a machine readable medium with sufficient detail. It may be suitable to facilitate the manufacture of all or a portion of the data processing system 160 including the processor core 170.For one embodiment, SIMD co-processor 161 includes an execution unit 162 and a set of register files 164. One embodiment of the main processor 165 includes a decoder 165 to recognize instructions of the instruction set 163 including SIMD move and XOR compute instructions for execution by the execution unit 162. For alternative embodiments, the SIMD co-processor 161 also includes at least a portion of the decoder 165B to decode instructions of the instruction set 163. Processing core 170 also includes additional circuitry (not shown) that is not necessary for understanding embodiments of the present invention.In operation, the main processor 166 executes a stream of data processing instructions that control data processing operations of a general type, including interactions with the cache memory 167 and the input / output system 168. Embedded in the stream of data processing instructions are SIMD coprocessor instructions. The decoder 165 of the main processor 166 recognizes that these SIMD co-processor instructions are of a type to be executed by an attached SIMD co-processor 161. Accordingly, the main processor 166 issues these SIMD coprocessor instructions (or controls signals representing SIMD coprocessor instructions) onto the coprocessor bus 166, from where they are received by any attached SIMD coprocessors. In this case, the SIMD coprocessor 161 will accept and execute any received SIMD coprocessor instructions destined for it.Data may be received via a wireless interface 169 for processing by the SIMD coprocessor instructions. As an example, voice communication may be received in the form of a digital signal that may be processed by the SIMD coprocessor instructions to regenerate digital audio samples representative of the voice communication. In a further example, compressed audio and / or video may be received in the form of a digital bitstream that may be processed by the SIMD coprocessor instructions to regenerate digital audio samples and / or motion video frames. In one embodiment of processing core 170, main processor 166 and a SIMD coprocessor 161 are integrated into a single processing core 170 that includes execution unit 162, a set of register files 164, and decoder 165 to recognize instructions of instruction set 163 including SIMD shift and XOR instructions.FIG. 2 is a block diagram of the microarchitecture for a processor 200 that includes logic circuitry to perform a shift and XOR instruction, in accordance with an embodiment of the present invention. For one embodiment of the shift and XOR instruction, the instruction may shift a floating point mantissa value to the right by the amount indicated by the exponent, may produce the shifted value by a value XORen, and the final result. In one embodiment, the in-order front end 201 is part of the processor 200 that fetches macro instructions to be executed and prepares them for later use in the processor pipeline. The front end 201 may include a plurality of units. In one embodiment, the instruction prefetcher 226 fetches macro instructions from memory and feeds them to an instruction decoder 228, which in turn decodes them into primitives called microinstructions or micro operations (also called micro-OP and μOps) that the machine can execute. In one embodiment, trace cache 230 takes decoded μOps and assembles them into program ordered sequences or traces in μOp queue 234 for execution. When trace cache 230 encounters a complex microinstruction, microcode ROM 232 provides the μOps needed to complete the operation.Many macro instructions are converted to a single micro-OP, while others require several μOps to complete the full operation. In one embodiment, if more than 4 μOps are needed to complete a macro instruction, decoder 228 accesses microcode ROM 232 to execute the macro instruction. For one embodiment, a packed shift and XOR instruction may be decoded into a small number of micro-ops for processing at instruction decoder 228. In another embodiment, a packed shift and XOR algorithm instruction may be stored in microcode ROM 232 if a number of μOps should be needed to perform the operation. Trace cache 230 refers to an entry point programmable logic array (PLA) to determine a more correct microinstruction pointer for reading the microcode sequences for the shift and XOR algorithm in microcode ROM 232. After microcode ROM 232 completes a micro-op sequencing for the current macro instruction, front end 201 of the machine resumes fetching micro-ops from trace cache 230.Some SIMD and other multimedia types of instructions are considered complex instructions. Most floating point related instructions are also complex instructions. When instruction decoder 228 encounters a complex macro instruction, microcode ROM 232 is accessed in the proper location to fetch the microcode sequence for that macro instruction. The various micro-ops needed to perform this macro instruction are communicated to the out-of-order execution engine 203 for execution at the appropriate integer and floating point execution units.The out-of-order execution engine 203 is where the microinstructions are prepared for execution. Out-of-order execution logic includes a number of buffers to smooth and reorder the flow of microinstructions to optimize performance as they move along the pipeline and are scheduled for execution. The allocation logic allocates the machine buffers and resources each μOp needs to execute. The register rename logic renames logic registers to entries in a register file. The allocator also allocates an entry for each μOp in one of the two μOp queues, one for memory operations and one for non-memory operations, prior to instruction schedulers: memory scheduler, fast scheduler 202, slow / general floating point scheduler 204, and simple floating point scheduler 206. The μOp schedulers 202, 204, 206 determine when a μOp is ready for execution based on the readiness of their dependent input register operand sources and the availability of the execution resources the μOps need to complete their operation. The fast scheduler 202 of this embodiment can schedule every half of the master clock cycle, while the other schedulers can schedule only once per master clock cycle. The schedulers switch for the dispatch ports to schedule μOps for execution.Register files 208, 210 are located between the schedulers 202, 204, 206 and the execution units 212, 214, 216, 218, 220, 222, 224 in the execution block 211. There is a separate register file 208, 210 for integer and floating point operations, respectively. Each register file 208, 210 of this embodiment also includes a bypass network that can bypass or forward just completed results that have not yet been written to the register file to new dependent μOps. The integer register file 208 and the floating point register file 210 are also capable of communicating data with each other. For one embodiment, the integer register file 208 is separated into two separate register files, one register file for the low order 32 data bits and a second register file for the high order 32 data bits. The floating point register file 210 of one embodiment includes 128 bits wide entries because floating point instructions typically have operands from 64 to 128 bits wide.The execution block 211 includes the execution units 212, 214, 216, 218, 220, 222, 224 in which the instructions are actually executed. This section includes register files 208, 210 which store the integer and floating point data operand values that the microinstructions require to execute. The processor 200 of this embodiment includes a number of execution units: an address generation unit (AGU) 212, AGU 214, fast ALU 216, fast ALU 218, slow ALU 220, floating point ALU 222, floating point move unit 224. For this embodiment, floating point execution blocks 222, 224 perform floating point, MMX, SIMD, and SSE operations. The floating point ALU 222 of this embodiment includes a 64 bit by 64 bit floating point divisors for performing divide, square root, and residual micro-ops. In embodiments of the present invention, any action involving a floating point value occurs at the floating point hardware. For example, conversions between the integer format and the floating point format include a floating point register file. Similarly, a floating point split operation occurs at a floating point divider. On the other hand, non-floating point numbers and integer types are treated with integer hardware resources. The simple very frequent ALU operations go to the high speed ALU execution units 216, 218. The fast ALUs 216, 218 of this embodiment may perform fast operations with an effective latency of one-half clock cycle. In one embodiment, most complex integer operations go to the slow ALU 220 because the slow ALU 220 includes integer execution hardware for a high latency type of operation, such as multiply, shift, flag logic, and branch processing. Memory load / store operations are performed by the AGUs 212, 214. For this embodiment, the integer ALUs 216, 218, 220 are described as performing integer operations on 64-bit data operands. In alternative embodiments, the ALUs 216, 218, 220 may be implemented to support a variety of data bits including 16, 32, 128, 256, etc. Similarly, floating point units 222, 224 may be implemented to support a range of operands having bits of different widths. For one embodiment, floating point units 222, 224 may operate on 128 bit wide packed data operands in conjunction with SIMD and multimedia instructions.The term "register" is used herein with reference to the in-component processor memory locations used as part of macro instructions to identify the operands. In other words, the registers referred to herein are those visible from the outside of the processor (from a programmer's perspective). However, the registers of an embodiment should not be limited in meaning to any particular type of circuit. Rather, a register of one embodiment need only be capable of storing and providing data and performing the functions described herein. The registers described herein may be implemented by circuitry in the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combination of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store 32 bit integer data. A register file of one embodiment also includes sixteen XMM and general purpose registers, eight multimedia (e.g., "EM64T" additions) multimedia SIMD packed data registers. For purposes of the following discussion, the registers are understood to be data registers designed to hold packed data, such as 64 bit wide MMX™ registers (also referred to as "mm" registers in some examples) in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. These MMX registers, available in both integer and floating point form, can operate on packed data elements associated with SIMD and SSE instructions. Similarly, 128 bit wide XMM registers related to SSE2, SSE3, SSE4 technology or technologies beyond it (commonly referred to as "SSEx" technology) may also be used to hold such packed data operands. In this embodiment, when storing packed data and integer data, the registers need not distinguish between the two types of data. In one embodiment, other registers or a combination of registers may be used to store 256 bits or more data.In the examples of the following figures, a number of data operands are described. FIG. 3A illustrates various representations of packed data types in multimedia registers, in accordance with an embodiment of the present invention. FIG. 3A illustrates data types for a packed byte 310, a packed word 320, and a packed doubleword (dword) 330 for operands having a width of 128 bits. The packed byte format 310 of this example is 128 bits long and contains 16 packed data elements. One byte is defined herein as eight bits of data. Information for each byte data element is stored in bit 7 through bit 0 for byte 0, bit 15 through bit 8 for byte 1, bit 23 through bit 16 for byte 2, and finally bit 120 through bit 127 for byte 15. Thus, all available bits in the register are used. This memory arrangement increases the storage efficiency of the processor. Likewise, when sixteen data elements are accessed, a single operation can now be performed on sixteen data elements in parallel.Generally, a data element is a single piece of data that is stored in a single register or memory location with other data elements of the same length. In packed data sequences related to SSEx technology, the number of data elements stored in an XMM register is 128 bits divided by the length in bits of a single data element. Similarly, for packed data sequences with respect to MMX and SSE technology, the number of data elements stored in an MMX register is 64 bits divided by the length in bits of a single data element. Although the data types shown in FIG. 3A are 128 bits long, embodiments of the present invention may also operate on operands having a width of 64 bits or other sizes. The packed word format 320 of this example is 128 bits long and contains eight packed word data elements. Each packed word contains 16 bits of information. The packed doubleword format 330 of FIG. 3A is 128 bits long and contains four packed doubleword data elements. Each packed doubleword data element contains 32 bits of information. A packed quadword is 128 bits long and contains two packed quadword data elements.Figure 3B illustrates alternative in-register data storage formats. Each packed data may comprise more than one independent data element. Three packed data formats are shown: packed half 341, packed single 342, and packed double 343. One embodiment of packed half 343, packed single 342 and packed double 434 contains fixed point data elements. For an alternative embodiment, one or more of packed half 341, packed single 342, and packed double 343 may contain floating point data elements. An alternative embodiment of packed half 341 is 128 bits long and contains eight 16-bit data elements. One embodiment of packed single 342 is 128 bits long and contains four 32-bit data elements. One embodiment of packed double 343 is 128 bits long and contains two 64-bit data elements. It will be appreciated that such data formats may be further extended to other register lengths, such as 96 bits, 160 bits, 192 bits, 224 bits, 256 bits, or more.FIG. 3C illustrates various packed data type representations with and without signs in multimedia registers according to an embodiment of the present invention. Unsigned packed byte representation 344 illustrates the storage of an unsigned packed byte in a SIMD register. Information for each byte data element is stored in bit seven to bit zero for byte zero, bit fifteen to bit eight for byte one, bit twenty-three to bit sixteen for byte two, and finally bit 128 to bit 127 for byte fifteen. Thus, all available bits in the register are used. This memory arrangement can increase the storage efficiency of the processor. Likewise, when sixteen data elements are accessed, an operation can now be performed on sixteen data elements in a parallel fashion. The signed packed byte representation 354 illustrates the storage of a signed packed byte. Note that the eighth bit of each byte data element is the sign indicator. Unsigned packed word representation 346 illustrates how word seven through word zero are stored in a SIMD register. The signed packed word representation 347 is similar to unsigned packed word-in register representation 346. Note that the sixteenth bit of each word data element is the sign indicator. Unsigned packed doubleword representation 348 shows how doubleword data elements are stored. The signed packed doubleword representation 349 is similar to unsigned packed doubleword in register representation 348. Note that the necessary sign bit is the thirty-second bit of each double-pole word data element.FIG. 3D is an illustration of an embodiment of an operation encoding (opcode) format 360 having 32 or more bits and register / memory operand addressing modes corresponding to a type of opcode format described in "IA-32 Intel Architecture Software Developer's Manual Volume 2: Instruction Set Reference", available from Intel Corporation, Santa Clara, CA, in the World Wide Web (WWW) at intel.com / design / litcentr. In one embodiment, a shift and XOR operation may be encoded by one or more fields 361 and 362. Up to two operand locations per instruction may be identified, including up to two source operand identifiers 364 and 365. For one embodiment of the shift and XOR instruction, the destination operand identifier 366 is the same as the source operand identifier 364, while in other embodiments they are different. For an alternative embodiment, the destination operand identifier 366 is the same as the source operand identifier 365, while in other embodiments they are different. In one embodiment of a shift and XOR instruction, one of the source operands identified by source operand identifiers 364 and 365 is overwritten by the results of the shift and XOR operations, while in other embodiments identifier 364 corresponds to a source register element and identifier 365 corresponds to a destination register element. For one embodiment of the shift and XOR instruction, operand identifiers 364 and 365 may be used to identify 32-bit or 64-bit source and destination operands.Figure 3E is an illustration of another alternative operation coding (opcode) format 370 having 40 or more bits. Opcode format 370 corresponds to opcode format 360 and includes an optional sign byte 378. The type of shift and XOR operation may be encoded by one or more of the fields 378, 371. Up to two operand locations per instruction may be identified by source operand identifiers 374 and 375 and by sign byte 378. For one embodiment of the shift and XOR instruction, sign byte 378 may be used to identify 32-bit or 64-bit source and destination operands. For one embodiment of the move and XOR instruction, the destination operand identifier 376 is the same as the source operand identifier 375, while in other embodiments they are different. In an alternative embodiment, the destination operand identifier 376 is the same as the source operand identifier 375, while in other embodiments they are different. In one embodiment, the shift and XOR's shift one of the operands identified by operand identifiers 374 and 375 to another operand identified by operand identifiers 374 and 375 is overwritten by the results of the shift and XOR's, while in other embodiments, the shift and XOR of the operands identified by identifiers 374 and 375 are written to another data element in another register. Opcode formats 360 and 370 allow for register to register addressing, memory to register, register by memory, register by register, register by immediate, register to memory, partially specified by MOD fields 363 and 373, and by optional scale index base and shift bytes.Referring to FIG. 3F, in some alternative embodiments, 64-bit single instruction multiple data (SIMD) arithmetic operations may be performed by a coprocessor data handling (CDP) instruction. An operation coding (opcode) format 380 represents such a CDP instruction with CDP opcode fields 382 and 389. The type of CDP instruction may be encoded by one or more of fields 383, 384, 387, and 388 for alternative embodiments of shift and XOR operations. Up to three operands per instruction may be specified, including up to two source operand identifiers 385 and 390 and one destination operand identifier 386. An embodiment of the coprocessor may operate on 8, 16, 32, and 64 bit values. For one embodiment, the shift and XOR operation is performed on floating point data elements. In some embodiments, a shift and XOR instruction may be conditionally executed using the selection field 381. For some shift and XOR instructions, source data sizes may be encoded by field 381. In some embodiments of the shift and XOR instruction, zero (Z), negative (N), carry (C), and overflow (V) detection may be performed on SIMD fields. For some instructions, the saturation type may be encoded by field 384.Figure 4 is a block diagram of one embodiment of logic for performing a shift and XOR operation on packed data operands in accordance with the present invention. Embodiments of the present invention may be implemented to operate on various types of operands such as those described above. For simplicity, the following discussions and examples will be given in the context of a shift and XOR instruction for processing data elements. In one embodiment, a first operand 401 is shifted by a shifter 410 by an amount specified by an input 405. One embodiment is a shift to the right. However, in other embodiments, the shifter performs a left shift operation. In some embodiments, the operand is a scalar value, while in other embodiments it is a packed data value with a number of different possible data sizes and types (e.g., floating point, integer). In one embodiment, the shift count 405 is a packed (or "vector") value, each element of which corresponds to an element of a packed operand to be shifted by the corresponding shift count element. In other embodiments, the shift count is applied to all elements of the first data operand. Moreover, in some embodiments, the shift count is indicated by a field in the instruction, such as an immediate, R / M, or other field. In other embodiments, the shift number is indicated by a register indicated by the instruction.The shifted operand is then XORed with a value 430 by logic 420, and the XORed result is stored at a target storage location (e.g., register 425). In one embodiment, the XOR value is a packed (or "vector") value, each of its elements corresponding to an element of a packed operand to be XORed with the corresponding XOR element. In other embodiments, the XOR value 430 is applicable to all elements of the first data operand. Moreover, in some embodiments, the XOR value is determined by a field in the instruction, such as an immediate, R / M, or other field. In other embodiments, the XOR value dis determined by a register indicated by the instruction.FIG. 5 illustrates the operation of a shift and XOR instruction according to an embodiment of the present invention. At operation 501, if a shift and XOR instruction is received, at operation 505, a first operand is shifted by a shift value. One embodiment is a right shift. However, in other embodiments, the shifter performs a left shift operation. In some embodiments, the operand is a scalar value, while in other embodiments it is a packed data value having a number of different possible data sizes and types (e.g., floating point, integer). In one embodiment, the shift value 405 is a packed (or "vector") value, each element of which corresponds to an element of a packed operand to be shifted by the corresponding shift value element. In other embodiments, the shift value is to be applied to all elements of the first data operand. Moreover, in some embodiments, the shift value is determined by a field in the instruction, such as an immediate, R / M, or other field. In other embodiments, the shift value is determined by a register specified by the instruction.At operation 510, the shifted value is XORed by an XOR value. In one embodiment, the XOR value 430 is a packed (or "vector") value, each element of which corresponds to an element of a packed operand that is XOR-combined by the corresponding XOR element. In other embodiments, the XOR value is to be applied to all elements of the first data operand. Moreover, in some embodiments, the XOR value is determined by a field in the instruction, such as an immediate, R / M, or other field. In other embodiments, the XOR value is determined by a register specified by the instruction.At operation 515, the shifted and XOR combined value is stored in a location. In one embodiment, the location is a scalar register. In other embodiments, the location is a packed data register. In another embodiment, the destination location is also used as a source location, such as a packed data register determined by the instruction. In other embodiments, the destination location is a different location than the source locations that store the initial operand or other values, such as the offset value or the XOR value.In one embodiment, the shift and XOR instruction is useful in various computer applications for performing data deduplication. Data deduplication aims to find common blocks of data between files to optimize disk storage and / or network bandwidth. In one embodiment, a move and XOR instruction is useful for improving performance in data deduplication operations using operations such as finding chunk boundaries using a rolling hash, hash digest (e.g., SHA1 or MD5), and compressing unique chunks (using fast Lempel-Ziv schemes).For example, a data deduplication algorithm may be illustrated by the following pseudo code: In the above algorithm, a scramble table is an array of 256 entries of random 32-bit constants and v is the rolling hash with a hash value of the last 32 bytes of the data. If a chunk boundary is found, the algorithm returns ret=1 and position p denotes the boundary of the chunk. The value z may be a constant, such as 12-15, which results in good chunk detection and may be application specific. In one embodiment, the shift and XOR instruction may assist in the above algorithm operating at a rate of approximately two cycles / byte. In other embodiments, the shift and XOR instruction helps the algorithm function even faster or slower depending on the use.At least one embodiment using the shift and XOR instruction may be illustrated by the following pseudo code: In the above algorithm, each entry of the brefl_ scramble array contains the bit reflected version of the corresponding entry in the original scramble array. In one embodiment, the above algorithm shifts v to the left rather than to the right and includes v a bit reflected version of the rolling hash. In one embodiment, the chunk boundary check is performed by checking a minimum number of leading zeros.In other embodiments, the shift and XOR instruction may be used in other useful computer operations and algorithms. Moreover, embodiments help improve the performance of many programs that extensively use move and XOR instructions.

Claims

A processor comprising: a decoder configured to recognize instructions of an instruction set comprising a single instruction multiple data, SIMD shift, and XOR instruction; Logic for performing the SIMD shift and XOR instruction with a first source operand to specify or store a first value, a second source operand to specify or store a shift amount, and a third source operand to specify or store a second value, wherein, in response to the SIMD shift and XOR instruction, the first value is shifted by the shift amount and the shifted value is XOR combined with the second value to generate a result of the SIMD shift and XOR instruction; and logic for performing a check whether a number of consecutive leading zeros is equal to or greater than a prescribed number as a result.The processor of claim 1, wherein the first value is to be moved to the left.The processor of claim 1, wherein the first value is to be shifted to the right.The processor of claim 1, wherein the first value is logically shifted.The processor of claim 1, wherein the first value is arithmetically shifted.The processor of claim 1, comprising a shift and XOR circuit.The processor of claim 1, wherein the shift and XOR instruction includes a first field for specifying the second value from an array of constants.The processor of claim 1, wherein the first value is a packed data.A system for performing data de-duplication, comprising: a first memory for storing a first SIMD instruction for performing a shift and XOR instruction; a second memory for storing a table of constants; a main processor having a decoder configured to recognize instructions of an instruction set comprising a SIMD shift and XOR instruction; a SIMD co-processor for executing the first SIMD shift and XOR instruction for performing the shift and XOR operation, wherein the main processor is configured to issue the first SIMD shift and XOR instruction onto a co-processor bus, from where it can be received by the SIMD coprocessor and the SIMD coprocessor is configured to accept and execute the received SIMD shift and XOR instruction, wherein the first SIMD shift and XOR instruction comprises a first source operand for specifying or storing a first value, a second source operand for specifying or storing a shift amount, and a third source operand for specifying or storing a second value from the table of constants in the second memory, wherein in response to the first SIMD shift and XOR instruction, the first value is shifted by the shift amount and the shifted value is XOR combined with the second value, to generate a result of the first SIMD shift and XOR instruction, and wherein the SIMD coprocessor is configured to check whether a number of consecutive leading zeros is equal to or greater than a prescribed number as a result.The system of claim 9, wherein the first value is to be moved to the left.The system of claim 9, wherein the first value is to be shifted to the right.The system of claim 9, wherein the first value is logically shifted.The system of claim 9, wherein the first value is arithmetically shifted.The system of claim 9, comprising a shift and XOR circuit.The system of claim 9, wherein the first instruction includes a first field for specifying the second value.The system of claim 9, wherein the first value is a packed date.A method comprising: performing a SIMD move and XOR instruction with a first source operand to specify or store a first value, a second source operand to specify or store a move amount, and a third source operand to specify or store a second value, wherein in response to the SIMD move and XOR instruction, the first value is moved by the move amount and the moved value is XOR combined with the second value to generate a result of the SIMD move and XOR instruction; and checking if a number of consecutive leading zeros is equal to or greater than a prescribed number as a result.The method of claim 17, wherein the first value is to be shifted to the left.The method of claim 17, wherein the first value is to be shifted to the right.The method of claim 17, wherein the first value is logically shifted.The method of claim 17, wherein the first value is arithmetically shifted.The method of claim 17, wherein a processor executing the method comprises a shift and XOR circuit.The method of claim 17, wherein the shift and XOR instruction includes a first field for storing the second value.The method of claim 9, wherein the first value is a packed data type.A machine readable medium having stored thereon a program having a SIMD move and XOR instruction having a first source operand for specifying or storing a first value, a second source operand for specifying or storing a move amount, and a third source operand for specifying or storing a second value that, when executed by a machine, causes the machine to perform a method comprising: move the first value by the move amount; and XOR combining the moved value with the second value to generate a result of the instruction; and checking whether a number of consecutive leading zeros in the result is equal to or greater than a prescribed number.The machine readable medium of claim 25, wherein the first value is to be moved to the left.The machine readable medium of claim 25, wherein the first value is to be shifted to the right.The machine readable medium of claim 25, wherein the first value is logically shifted.The machine readable medium of claim 25, wherein the first value is arithmetically shifted.The machine readable medium of claim 25, wherein the machine executing the instruction comprises a shift and XOR circuit.The machine readable medium of claim 25, wherein the instruction includes a first field for storing the second value.The machine readable medium of claim 25, wherein the first value is a packed data type.A method for data deduplicating, by a processor executing a SIMD shift and XOR instruction, comprising: responsive to the shift and XOR instruction, performing a first shift of a first value by a shift amount to generate a first shifted value and an exclusive-OR (XOR) operation between the first shifted value and a second value from an encryption table array in memory and storing the result in a first register; checking if a number of consecutive leading zeros in the result is equal to or greater than a prescribed number.The method of claim 33, wherein if the number of consecutive leading zeros is equal to or greater than the prescribed number as a result, the method further comprising: indicating that the result corresponds to a first piece.The method of claim 34, wherein the first shifted value is to be shifted leftward by one bit position in response to the shift and XOR instruction.The method of claim 34, wherein the second value from the encryption table is one of an array of 32-bit bit bit reflected constants, and the first value is to include a bit reflected version of a rolling hash of 32-bytes of data.

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