Memory operations using system temperature sensor data
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- TAHOE RES LTD
- Filing Date
- 2011-12-23
- Publication Date
- 2026-07-30
AI Technical Summary
3D stacked memory devices experience temperature differentials leading to inefficient refresh operations due to the lack of temperature sensors or inaccessible temperature data, which complicates the management of refresh cycles and power consumption.
Incorporating temperature sensors in a logic chip tightly coupled to the memory stack to estimate temperature conditions, allowing the memory controller to adjust refresh rates based on temperature gradients and reduce power consumption.
Enhances memory performance by optimizing refresh frequencies, reducing active power consumption, and enabling operation at higher temperatures through precise temperature-based management.
Smart Images
Figure 00000013_0000 
Figure 00000014_0000 
Figure 00000015_0000
Abstract
Description
TECHNICAL AREA
[0001] Embodiments of the invention generally relate to the field of electronic components and, in particular, memory operations using system temperature sensor data. BACKGROUND
[0002] To provide memory with higher density for computing operations, concepts are being developed that include storage devices with multiple tightly coupled memory elements (which can be referred to as 3D stacked memory or stacked memory). A 3D stacked memory can comprise coupled layers or units of DRAM (Dynamic RAM) memory elements, which can be called a memory stack. Stacked memory can be used to provide a large amount of main memory in a single component or unit, which can also include certain system components, such as a memory controller and a CPU (Central Processing Unit).
[0003] As 3D stacked storage devices have increased in size, temperature differences prevail within the storage stack. The inner part of a 3D storage stack is generally hotter than the outer sections, since only the outer sections are subject to cooling, and larger stacks generally result in greater temperature differences between the inner and outer sections.
[0004] The way a storage device functions changes when it heats up. In particular, storage devices at higher temperatures generally require more frequent refresh cycles. However, a low-cost storage device may not have temperature sensors or be able to provide temperature data. Without temperature monitoring, it is difficult to determine how heat is distributed within a storage device and therefore how to appropriately manage refresh cycles. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Embodiments of the invention are shown by way of example and in no way limiting in the figures of the accompanying drawings, whereby the same reference numbers refer to similar elements.
[0006] Fig. 1 represents an embodiment of a stack storage device;
[0007] Fig. Figure 2 represents an embodiment of a 3D stack storage system;
[0008] Fig. Figure 3 is an illustration of temperature sensors in an embodiment of a storage device;
[0009] Fig. Figure 4 is a flowchart illustrating an embodiment of a method for setting a memory refresh using system temperature data;
[0010] Fig. Figure 5 represents an embodiment of a logic chip that incorporates a thermal subsystem for estimating the temperature conditions of a memory;
[0011] Fig. Figure 6 is a block diagram illustrating an embodiment of a device or system that includes a stack storage device;
[0012] Fig. Figure 7 represents an embodiment of a computing system that includes a thermal subsystem for estimating the temperature conditions of a storage device; and
[0013] Fig. 8A and Fig. 8B represent embodiments of storage devices which include a thermal subsystem for estimating temperature conditions in the stacked storage device. DETAILED DESCRIPTION
[0014] In general, embodiments of the invention relate to dynamic operations in 3D stack storage using temperature data.
[0015] As used here: "3D stacked storage" (where 3D indicates three-dimensional) or "stacked storage" means main memory that comprises one or more coupled memory layers, memory units, or other memory elements. The memory can be stacked vertically or horizontally (such as side by side), or it can comprise otherwise coupled memory elements. The memory can, for example, contain the... Fig. 8A and Fig. The implementations shown in Figure 8B are included. In particular, a stack storage DRAM device or system may include a storage device that has multiple DRAM layers. A stack storage device may also include system elements within the device, the system elements being a logic chip. The logic chip may comprise a system-on-a-chip (SoC) and may include elements such as a CPU (main processor), a memory controller, and other related system elements. In some embodiments, the logic chip may be an application processor or a graphics processing unit (GPU).
[0016] DRAM behaves differently at different temperatures. In particular, DRAM chips exhibit varying retention times due to temperature, which affects the required refresh rate. Low-power DRAM chips can utilize this characteristic in a feature known as "temperature-compensated self-refresh." This feature can be used to reduce the refresh rate to the required levels, rather than refreshing the memory, to accommodate, for example, the worst-case scenarios. This feature can thus be used to reduce the standby power consumption of the memory.
[0017] A stacked storage device may contain areas that become much warmer than other areas. Determining these temperature gradients within the storage stack could be used to define the storage's refresh requirements.
[0018] However, certain memory devices, including those manufactured to lower costs, may lack internal temperature sensors, or, if temperature sensors are present, such sensors may not be accessible to a memory controller or other processing element for use in regulating the operation of a stacked memory device. For example, temperature sensors in DRAM devices may not be exposed to the outside of the DRAM except to indicate very large temperature fluctuations. DRAM vendors typically prefer not to disclose lower temperature readings because they do not want to guarantee the accuracy of their temperature sensors.In some embodiments, temperature sensors integrated into a logic chip, including a system-on-chip, are used to provide temperature information to a DRAM controller or other processing elements. The memory controller or memory elements then use this information to reduce the auto-refresh rate to more efficient levels, thereby improving performance and reducing active power consumption. In some embodiments, the logic chip is tightly coupled to the DRAM memory elements, allowing the temperature information obtained from the temperature sensors to be used to infer the temperature state of the memory elements.
[0019] In some embodiments, memory current and power optimization functions are provided in a stacked chip device, where the memory raw chip layers and the logic chip (such as a processor or SoC logic chip) reside on separate chips but are very tightly coupled. When a logic chip and a stack of DRAM raw chip layers are stacked to create a stacked memory device, such as in a wide-IO memory interconnector PoP, there is only a small temperature gradient between the memory stack and the logic chip. In some embodiments, temperature sensors present in a logic chip can be used to estimate temperature conditions in the memory raw chip layers.
[0020] In some embodiments, the estimated temperature conditions can be used to determine the performance settings for the memory, including the refresh cycle frequencies for sections of the memory stack. A logic chip can include multiple temperature sensors used to monitor the temperature at different parts of the logic chip. In some embodiments, due to thermal coupling between the memory stack and the logic chip, the logic chip's temperature sensors can also be used to estimate the temperatures of the DRAM chips. In some embodiments, a logic chip's temperature sensors provide temperature information to the DRAM controller, which can then use this information to reduce the auto-refresh frequency, thereby improving performance and reducing active power consumption.In some embodiments, a device or system can also use the temperature information to ensure sufficient refresh at rising temperatures, thus enabling the operation of a stack storage device at higher temperatures.
[0021] In some embodiments, a storage device comprises a memory stack having one or more coupled memory elements and a logic element, wherein the logic element comprises one or more temperature sensors, the one or more temperature sensors comprising a first temperature sensor in a first region of the logic element. In some embodiments, the logic element determines temperature values from the one or more temperature sensors, wherein the logic element is intended to estimate temperature conditions for the memory stack using the temperature sensor values.In some embodiments, the determination of the estimated temperature conditions for the memory stack is based at least partially on the location of each of the one or more temperature sensors, including the location of the first temperature sensor in the first region of the logic element, and a refresh rate for one or more sections of the memory stack is modified at least partially on the basis of the estimated temperature conditions for the memory stack.
[0022] In some embodiments, a method comprises collecting temperature data from one or more temperature sensors in a logic chip, wherein the logic chip is coupled to a memory stack, estimating temperature conditions of the memory stack based on the collected temperature data and the location of each of the one or more temperature sensors, determining a recommended refresh rate for each of the one or more sections of the memory stack, and, after determining that a refresh rate of a section of the memory stack differs from a recommended refresh rate, setting the refresh rate for that section of the memory stack.
[0023] Fig. Figure 1 is a representation of one embodiment of a stack storage device. In some embodiments, a stack storage device comprises 100 a memory stack comprising one or more DRAM raw chip layers 120includes and closely associated with a logic chip 110 is coupled, which can be a SoC or another system. In some embodiments, the logic chip can 110 a heat subsystem for the storage stack 120 comprising, wherein the thermal subsystem includes one or more temperature sensors for assessing temperature conditions in the memory stack 120 can be used.
[0024] In some embodiments, the logic chip 110 or the DRAM raw chip layers, the estimated temperature conditions of the memory stack 120 use to determine required refresh rates for sections of the memory stack 120to determine. In some embodiments, the logic chip or the raw DRAM chip layers can use the estimated temperature conditions to avoid performing refresh operations more frequently than necessary, and the logic can thus operate to reduce the power consumption of the memory stack. 100 to reduce. In some embodiments, a device or system can also use the estimated temperature conditions to ensure sufficient refresh rates at rising temperatures and thus enable operation of the stack storage device. 100 to enable higher temperatures.
[0025] Fig. Figure 2 represents an embodiment of a 3D stack storage device. In this representation, a 3D stack storage device comprises 200 , such as a wide I / O storage device, a logic chip system element 210 , which uses one or more DRAM memory raw chip layers 220, which are also referred to here as memory stacks, are coupled. In some embodiments, the logic chip can 210 a system-on-chip (SoC) or other similar element. The elements in this and subsequent figures are shown for illustrative purposes and are not drawn to scale. Each raw chip layer comprises one or more disks or sections and may have one or more distinct channels. Each raw chip layer may include a temperature-compensated self-refresh (TCSR) circuit to address thermal aspects, wherein the TCSR and a mode register (MR) may be part of the device's management logic, and wherein the management logic (MC) may include thermal offset bit(s) for setting the refresh rate by the TCSR. The raw chip layers and the system element may be thermally coupled.
[0026] Although Fig. 2 illustrates an implementation where the logic chip 210 below the memory stack consisting of one or more memory raw chip layers 220 Since the system is coupled, embodiments are not limited to this arrangement. For example, in some embodiments, a system element can be coupled. 210 to the memory stack 220 be arranged adjacently and can therefore be arranged side-by-side with the storage stack 220 be coupled.
[0027] In this representation, the DRAM memory raw chip layers comprise four memory raw chip layers, with these layers being a first memory raw chip layer. 230 , a second memory raw chip layer 240 , a third memory raw chip layer 250 and a fourth memory raw chip layer 260 However, embodiments are not limited to a specific number of raw memory chip layers in the memory stack. 210limited and can have a larger or smaller number of raw memory chip layers. Among other elements, the system element can 210 a memory controller 212 for the memory stack 220 include. In some embodiments, each memory raw chip layer (with the possible exception of the uppermost or outermost memory raw chip layer, such as the fourth memory raw chip layer) includes. 260 (in this representation) a plurality of silicon through-silicon vias (TSVs) 205 , to provide pathways through the silicon substrate of the memory raw chip layers.
[0028] The storage 200 can have one or more temperature gradients, where temperature gradients are vertical gradients 270 , such as cooler areas closer to cooling fins or other cooling elements, and horizontal temperature gradients 275, such as differences between a hotter inner core and cooler outer sections of the memory stack 220 , may include.
[0029] In some embodiments, the logic chip 210 one or more temperature sensors 280 include those used to assess temperature conditions in the storage stack 220 can be used, with the memory controller 212 or the memory raw chip layers 220 can use the estimated temperature conditions to determine refresh rates for sections of the memory stack 220 to determine. In some embodiments, a memory raw chip layer can be used. 220 Use the estimated temperature state to adjust the temperature values generated by temperature sensors in the memory raw chip layer.
[0030] Fig. Figure 3 shows a representation of temperature sensors in an embodiment of a storage device. In some embodiments, a storage device may 300 one or more closely associated with a logic chip 310 coupled memory chips 330 include. In some embodiments, the memory chips may not have temperature sensors, or if temperature sensors are present, they may not. 335 While data from such temperature sensors are available, they are not generally stored outside the memory chip. 330 Accessible, except in the presence of extreme temperatures. In some embodiments, the logic chip includes one or more temperature sensors. 380 and the logic chip uses such sensors to monitor thermal conditions in the memory chip 330 to assess. In some embodiments, the position of each of the temperature sensors is 380 the logic chip 310This knowledge is known and can be used to estimate temperatures in different areas of the memory chip.
[0031] Fig. Figure 4 is a flowchart illustrating one embodiment of a method for determining the memory refresh using system temperature data. In some embodiments, a device or system that includes a stacked memory may be operated 410 In some embodiments, the stack memory may include a logic chip coupled to a memory stack consisting of one or more raw memory chip layers. In some embodiments, a controller of the stack memory may process data from system temperature sensors in the logic chip. 415 collect.
[0032] In some embodiments, the controller can determine the temperature conditions of different areas of the memory stack based on the temperature data collected by the temperature sensors and the location of the temperature sensors. 420 estimate. In some embodiments, the controller can estimate a recommended refresh rate for each of several sections of the memory stack based on the estimated temperature conditions and performance characteristics. 425 of the memory stack, such as data relating to required refresh rates for memory elements at specific temperatures.
[0033] If the estimated temperature condition data for the memory stack indicates that the refresh rate for a section of the memory stack deviates from the recommended refresh rate 430 Since it differs, in some embodiments the controller can adjust the refresh rate for the section of the memory stack. 435independently. The process can then be modified by collecting temperature data from the system temperature sensors. 410 continue.
[0034] Fig. Figure 5 represents an embodiment of a logic chip that includes a thermal subsystem for estimating the temperature conditions of a memory. In some embodiments, a logic chip can 500 a storage device (such as a logic chip) 210 of the in Fig. 2 shown stack storage 200 ) a memory controller 512 to control the memory of a memory stack, wherein the logic chip 500 The logic chip is closely coupled to the memory stack, so temperatures in the logic chip are an indicator of temperatures in the memory stack. In some embodiments, the logic chip includes one or more temperature sensors. 580 , to obtain system temperature data 582to collect. In some embodiments, the logic chip can collect system temperature data. 582 use to estimate temperature conditions 584 to generate the memory. In some embodiments, the estimated temperature conditions can be 584 of the memory and the performance characteristics 590 of the storage device, including data describing required refresh rates for specific temperatures, can be used to determine refresh rates for one or more sections of the memory stack. 592 to specify. In some embodiments, the memory controller can 512 The refresh rates for sections of the memory stack are set. In some embodiments, the memory controller can provide data relating to the estimated temperature conditions to memory elements of the memory stack, enabling the memory elements to set refresh rates for themselves.
[0035] Fig. Figure 6 is a block diagram illustrating an embodiment of a device or system that includes a stack storage device. Computing device 600represents a computing device that includes a mobile computing device, such as a laptop or notebook computer, a netbook, a tablet computer (including a device that has a touchscreen without a separate keyboard, a device that has both a touchscreen and a keyboard, a device that has a fast initialization process called "Instant On," and a device that is generally connected to a network while operating, referred to as "Always Connected"), a mobile phone or smartphone, a wireless-enabled e-reader, or any other wireless mobile device. It is evident that certain components are represented generically and not all components of such a device are included. 600 are shown. The components can be connected via one or more buses or other connections. 605 Be connected. Device 600includes processor 610 , which performs the main processing operations of the device 600 executes. Processor 610 It can comprise one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing units. The processing operations performed by the processor 610 The processing operations performed include the execution of an operating platform or operating system on which applications, device functions, or both are run. These operations include I / O (input / output) operations with a human user or other devices, power management operations, and / or connecting devices. 600related to another device. The processing operations may also include operations related to audio I / O, display I / O, or both.
[0036] In one embodiment, the device includes 600 an audio subsystem 620 , which represents hardware (such as audio hardware and audio circuitry) and software components (such as drivers and codecs) associated with providing audio functionality to the computing device. Audio functionality may include a speaker output, a headphone output, or both, as well as a microphone input. Devices for such functionality may be integrated into the device 600 integrated or with device 600 be connected. In one embodiment, a user interacts with the device. 600 by providing audio commands that are processed by the processor 610 be received and processed. Display subsystem 630The display subsystem represents hardware (such as display devices) and software components (such as drivers) that provide a display, which has visual elements, tactile elements, or both, for a user to interact with the computing device. 630 displays interface 632 on, which includes the specific screen or hardware device used to provide a display to a user. In one embodiment, the display interface includes 632 one of the processor 610 Separate logic is required to perform at least some processing tasks related to the display. In one embodiment, the display subsystem includes... 630 A touchscreen device that provides both output and input for a user.
[0037] I / O controller 640Represents hardware devices and software components related to user interaction. I / O controller 640 can work to manage hardware that is part of the audio subsystem 620 , of a display subsystem 630 or both such subsystems. Furthermore, it provides I / O controllers. 640 represents a connection point for additional devices that are connected to the device 600 are connected and allow a user to interact with the device. Devices connected to the device 600 Devices that can be connected include, for example, microphones, speakers or stereo systems, video systems or other display devices, keyboards or keypads, or other I / O devices for use with specific applications, such as card readers or other devices. As mentioned above, I / O controllers can 640 with audio subsystem 620 , Display subsystem 630or interact with both such subsystems. For example, an input via a microphone or other audio device can provide input or commands for one or more applications or functions of the device. 600 Provide audio output instead of, or in addition to, the display output. Furthermore, if the display subsystem includes a touchscreen, the display device also acts as an input device, at least partially controlled by I / O controllers. 640 can be controlled. On the device 600 Additional buttons or switches may also be present for use by I / O controllers. 640 to provide managed I / O functions.
[0038] In one embodiment, the I / O controller manages 640 Devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that is integrated into the device 600The input may include elements of a direct user interaction as well as providing an environment-based input to the device to influence its operations (such as filtering noise, adjusting displays with respect to brightness detection, applying a camera flash, or other functions). In one embodiment, the device comprises 600 Power Management 650 , which manages battery power usage, battery charging, and functions related to energy-saving operation. In some embodiments, the storage subsystem includes 660 Storage devices for storing information in the device 600 The processor 610 can data from elements of the storage subsystem 660Read and write to these. Memory can include non-volatile storage devices (which have a state that does not change when power to the storage device is interrupted), volatile storage devices (which have an indeterminate state when power to the storage device is interrupted), or both. Memory 660 This may include application data, user data, music, photos, documents or other data, as well as device data (whether long-term or temporary) associated with the execution of the device's applications and functions. 600 be related, store.
[0039] In some embodiments, the storage subsystem 660 a stack storage device 662 featuring a memory stack consisting of one or more raw memory chip layers, wherein the stack storage device includes a thermal subsystem 664The device features a thermal subsystem for assessing temperature conditions within the stacked storage device using one or more system temperature sensors arranged in a logic chip tightly coupled to the storage stack. In some embodiments, the information generated by the thermal subsystem can be used to determine efficient refresh rates for the storage stack, thereby reducing the device's power consumption.
[0040] Connectivity 670 includes hardware devices (e.g., connectors and communication hardware for wireless communication, wired communication, or both) and software components (e.g., drivers, protocol stack) to make it a device 600 To enable communication with external devices. The device could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals, such as headsets, printers, or other devices. Connectivity670 can encompass several different types of connectivity. To generalize, device 600 with mobile connectivity 672 and wireless connectivity 674 Shown. Mobile network connectivity 672 This generally refers to mobile network connectivity provided by mobile network operators, such as via 4G / LTE (Long Term Evolution), GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiple Access) or variants or derivatives, or other mobile service standards. Wireless connectivity 674This refers to non-cellular wireless connectivity and can include personal networks (such as Bluetooth), local area networks (such as Wi-Fi), wide area networks (such as WiMAX), and other wireless communication technologies. The connectivity may involve one or more omnidirectional or directional antennas. 676 include.
[0041] Peripheral connections 680 This includes hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) to establish peripheral connections. It is obvious that the device 600 both a peripheral device (“on” 682 ) for other computer devices as well as peripheral devices connected to it (“of” 684 ), could exhibit. Device 600 Generally, a "dock" port can be used to connect to other computing devices for purposes such as managing (like downloading, uploading, modifying, or synchronizing) content on the device. 600. Furthermore, a dock connector can facilitate the connection of the device. 600 with certain peripheral devices that enable the device 600 to enable the control of content output to, for example, audiovisual or other systems.
[0042] In addition to a proprietary dock connector or other proprietary connection hardware, the device can 600 Connections with peripheral devices 680 via conventional or standards-based connectors. Conventional types can include a USB port (which may encompass any of a number of different hardware interfaces), DisplayPort, including Mini DisplayPort (MDP), HDMI (High Definition Multimedia Interface), FireWire, or another type.
[0043] Fig. Figure 7 presents an embodiment of a computing system that includes a thermal subsystem for estimating the temperature conditions of a storage device. The computing system may comprise a computer, a server, a game console, or another computing device. Certain conventional and generally known components that are not relevant to the present invention are not shown in this illustration. In some embodiments, the computing system comprises 700 Interconnect or crossbar unit 705 or another communication device for data transmission. The computer system 700 can one with the interconnect 705 coupled processing unit, such as one or more processors 710 , for processing information. The processors 710 They can include one or more physical processors and one or more logical processors. The interconnect 705For simplicity, it is represented as a single interconnect; however, it can represent multiple different interconnects or buses, and the component connections to such interconnects can vary. The in Fig. 7 shown interconnect 705 is a generalization that represents one or more separate physical buses, point-to-point connections, or both, connected via suitable bridges, adapters, or controllers.
[0044] In some embodiments, the computing system also includes 700 a RAM (Random Access Memory) or other dynamic memory device or element as main memory 712 for storing information and instructions issued by the processors 710The RAM memory comprises DRAM (Dynamic Random Access Memory), which requires refreshing its contents, and SRAM (Static Random Access Memory), which does not require refreshing its contents, but this increases costs. In some embodiments, the main memory may include active storage of applications, including a search engine application for use during network browsing activities by a user of the computing system. The DRAM memory may include SDRAM (Synchronous Dynamic Random Access Memory), which has a clock signal for controlling signals, and EDO-DRAM (Extended Data-Out Dynamic Random Access Memory). In some embodiments, the system's memory may include specific registers or other specialized memory.
[0045] In some embodiments, the main memory includes 712 a stack storage 714 , wherein the stack storage device is a thermal subsystem715 The device features a thermal subsystem for assessing temperature conditions within the stacked storage device using one or more system temperature sensors located in a logic chip tightly coupled to the storage stack. In some embodiments, the information generated by the thermal subsystem can be used to determine efficient refresh rates for the storage stack, thereby reducing the device's power consumption.
[0046] The computer system 700 It can also be a ROM (Read Only Memory) 716 or another static storage device for storing static information and instructions for the processors 710 include the computer system 700 can contain one or more non-volatile memory elements 718 to store specific elements.
[0047] In some embodiments, the computing system includes 700 one or more input devices 730, wherein the input devices comprise one or more devices such as a keyboard, mouse, touchpad, voice command recognition, gesture recognition or other device for providing input to a computing system.
[0048] The computer system 700 can also be accessed via the interconnect 705 with an output display 740 be coupled. In some embodiments, the display can 740 This includes a liquid crystal display (LCD) or any other display technology for showing information or content to a user. In some environments, the display may 740 It includes a touchscreen, which is also used as at least part of an input device. In some environments, the display may 740 an audio device, such as a loudspeaker, for providing audio information, or to include such a device.
[0049] One or more transmitters or receivers 745 can also be used with the Interconnect 705 be coupled. In some embodiments, the computing system can 700 one or more ports 750 include receiving or sending data. The computer system 700 It may also include one or more omnidirectional or directional antennas. 755 to receive data via radio signals.
[0050] The computer system 700 It can also be a power supply device or system 760 exhibiting a power supply, battery, solar cell, fuel cell, or other system or device for providing or generating energy. The power supply device or system 760 The supplied electricity can be directed to the elements of the computer system as needed. 700 be distributed.
[0051] Fig. 8A and Fig. Figure 8B represents embodiments of storage devices that include a thermal subsystem for estimating temperature conditions in the stacked storage device. In the Fig. The illustration provided in 8A includes a stack storage device. 800 a memory stack 815 , where the memory stack in this representation has four memory raw chip layers, a first memory raw chip layer 820 , a second memory raw chip layer 830 , a third memory raw chip layer 840 and a fourth memory raw chip layer 850 , includes. In this representation, the memory stack 815 with a logic chip or other system element 810 via a number of interconnects 870 coupled, with the logic chip being thermally coupled to the memory stack. In some embodiments, the logic chip comprises 810 a memory controller 814 and one or more temperature sensors 880In some embodiments, the memory controller estimates 814 Temperature conditions in the storage stack 815 using one or more system temperature sensors 880 one. In some embodiments, the estimated temperature conditions can be used to determine efficient refresh rates for the memory stack. 815 to determine and thereby reduce the device's power consumption.
[0052] In the Fig. The representation provided in 8B includes a stack storage device. 802 a memory stack 817 and a logic chip 812 or another one via housing substrate 875 connected system element, wherein the housing substrate is, for example, a non-silicon substrate 894 coupled silicon interlayer 892 It can be a silicon or a silicon substrate (not shown here). In this representation, the memory stack comprises 817two memory raw chip layers, a first memory raw chip layer 822 and a second memory raw chip layer 832 However, embodiments are not limited to a specific number of memory raw chip layers. In this representation, the memory stack 817 and the logic chip 812 with the substrate 875 via interconnects 872 and 874 connected, with the logic chip 812 It is thermally coupled to the memory stack. In some embodiments, the logic chip includes 812 a memory controller 816 and one or more temperature sensors 882 In some embodiments, the memory controller estimates 816 Temperature conditions in the storage stack 817 using one or more system temperature sensors 882one. In some embodiments, the estimated temperature conditions can be used to determine efficient refresh rates for the memory stack. 817 to determine.
[0053] The foregoing description includes numerous specific details for explanatory purposes, in order to facilitate a thorough understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be realized without some of these specific details. In other instances, generally known arrangements and devices are shown in the form of block diagrams. Intermediate structures may exist between the illustrated components. The components described or illustrated herein may have additional inputs or outputs that are not illustrated or described.
[0054] Different implementations can involve different processes. These processes can be executed by hardware components, or they can be embedded in a computer program or machine-executable instructions that can be used to instruct a general-purpose or specialized processor, or logic circuits programmed with the instructions, to execute the processes. Alternatively, the processes can be executed by a combination of hardware and software.
[0055] Parts of various embodiments may be provided as a computer program product, which may include a non-volatile, computer-readable storage medium on which computer program instructions are stored that can be used to program a computer (or other electronic devices) to execute a process according to certain embodiments of one or more processors.The computer-readable medium may include, but is not limited to, floppy disks, optical discs, CD-ROMs (compact disk read-only memory) and magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or other types of computer-readable medium suitable for storing electronic instructions. Furthermore, embodiments may also be downloadable as a computer program product, wherein the program can be transferred from a remote computer to a requesting computer.
[0056] Many of the methods are described in their most basic form; however, processes can be added to or removed from each of the methods, and information can be added to or removed from any of the described processes without deviating from the basic scope of the present invention. It is obvious to those skilled in the art that many further modifications and adaptations can be implemented. The specific embodiments are not intended to limit the invention but to illustrate it. The scope of the embodiments of the present invention is not determined by the specific examples listed above but only by the following claims.
[0057] When it is stated that an element "A" is coupled to or connected with element "B", element A can be directly coupled to element B or indirectly coupled via, for example, element C. If the description or claims state that a component, feature, arrangement, process, or property A "causes" a component, feature, arrangement, process, or property B, this means that "A" is at least a partial cause of "B", but that there may also be at least one other component, feature, arrangement, process, or property that assists in causing "B".If the description states that a component, feature, arrangement, process, or property “may” or “could” be included, that specific component, feature, arrangement, process, or property is not necessarily included. Similarly, if the description or claim refers to “one” element, this does not mean that only one of the described elements is present.
[0058] An embodiment is an implementation or example of the present invention. Reference in the description to “an embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, arrangement, or property described in connection with the embodiments is included in at least some, but not necessarily all, embodiments. The varying occurrence of “an embodiment” or “some embodiments” does not necessarily refer to the same embodiments.It should be self-evident that in the preceding description of exemplary embodiments of the present invention, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of simplifying the disclosure and achieving a better understanding of one or more different inventive aspects. However, this method of disclosure should not be interpreted as an intention that the claimed invention requires more features than are expressly cited in each claim. Rather, the aspects of the invention, as set forth in the following claims, are contained in fewer than all the features of a single disclosed embodiment. Thus, the claims are expressly an integral part of this description, with each claim standing independently as a separate embodiment of this invention.
Claims
[1] Storage device, comprising: a memory stack comprising one or more coupled memory elements, and a logic chip coupled to the memory stack, wherein the logic chip comprises a memory controller and one or more temperature sensors, wherein the one or more temperature sensors comprise a first temperature sensor arranged in a first region of the logic chip, wherein the memory controller obtains temperature values from the one or more temperature sensors, the logic element estimates temperature conditions for the memory stack using the temperature values, wherein the determination of the estimated temperature conditions for the memory stack is based at least partially on a position of the first temperature sensor in the first region of the logic element, and where a refresh rate for one or more sections of the memory stack is modified at least partially on the basis of the estimated temperature conditions for the memory stack. [2] Storage device according to claim 1, wherein the storage controller modifies the refresh rate for one or more sections of the storage stack at least partially on the basis of the estimated temperature conditions for the storage stack. [3] Storage device according to claim 2, wherein the storage controller modifies the refresh rate by instructing a storage element with respect to a refresh rate for the storage element. [4] Storage device according to claim 2, wherein the storage controller modifies the refresh rate by performing one or more refresh cycles for the storage element at a time when the storage element itself is not performing any refresh cycles. [5] Storage device according to claim 1, wherein the storage device provides data regarding the estimated temperature conditions for the storage stack to a storage element of the storage stack, wherein the storage element modifies the refresh rate for the storage element using the estimated temperature conditions. [6] Storage device according to claim 1, wherein the setting of the refresh rate is further based on storage performance data for the storage stack. [7] Storage device according to claim 1, wherein the logic chip is a system-on-chip (SoC). [8] Storage device according to claim 1, wherein one or more storage elements are DRAM (dynamic random-access memory) elements. [9] Storage device according to claim 1, wherein one or more storage elements do not have temperature sensors. [10] Storage device according to claim 1, wherein one or more storage elements have temperature sensors which are not accessible to the storage controller. [11] Storage device according to claim 1, wherein the one or more storage elements have temperature sensors and wherein the storage elements use the estimated temperature conditions to adjust temperature values generated by the temperature sensors of the storage elements. [12] Storage device according to claim 1, wherein the storage elements comprise one or a plurality of memory raw chip layers or a plurality of memory packages. [13] Procedures, including: Collecting temperature data from one or more temperature sensors in a logic chip, wherein the logic chip is coupled with a memory stack, Estimating the temperature conditions of the memory stack based on the collected temperature data and the location of each of the one or more temperature sensors, Determining a recommended refresh rate for each of one or more sections of the memory stack, and Setting – after determining that a refresh rate of a section of the memory stack differs from a recommended refresh rate – the refresh rate for the section of the memory stack. [14] Method according to claim 13, wherein the setting of the refresh rate comprises the setting of the refresh rate by the memory controller for one or more sections of the memory stack at least partially based on the estimated temperature conditions for the memory stack. [15] Method according to claim 14, wherein the memory controller sets the refresh rate by instructing a memory element with respect to a refresh rate for the memory element. [16] Method according to claim 14, wherein the memory controller modifies the refresh rate by performing one or more refresh cycles for the memory element at a time when the memory element itself is not performing any refresh cycles. [17] Method according to claim 13, further comprising providing, by the storage device, data relating to the estimated temperature conditions to a storage element of the storage stack, wherein the setting of the refresh rate comprises the setting by the storage element of the refresh rate for the storage element using the estimated temperature conditions. [18] Method according to claim 13, wherein the setting of the refresh rate is further based on the memory performance data for the memory stack. [19] Method according to claim 13, wherein the storage elements do not have temperature sensors. [20] Method according to claim 13, wherein the storage elements have temperature sensors which are not accessible to the storage controller. [21] Method according to claim 13, wherein the one or more storage elements have temperature sensors and wherein the method further comprises using the estimated temperature conditions by the storage elements to adjust temperature values generated by the temperature sensors of the storage elements. [22] System, encompassing: a processor for processing system data, a transmitter, a receiver or both, coupled with an omnidirectional antenna for sending data, receiving data or both, and a storage device for storing data, wherein the storage device includes a stack storage device, the stack storage device having: a memory stack comprising one or more coupled memory elements, and a logic chip coupled to the memory stack, wherein the logic chip comprises a memory controller and one or more temperature sensors, wherein the one or more temperature sensors comprise a first temperature sensor arranged in a first region of the logic chip, wherein the memory controller obtains temperature values from the one or more temperature sensors, the logic element estimates temperature conditions for the memory stack using the temperature values, wherein the determination of the estimated temperature conditions for the memory stack is based at least partially on a position of the first temperature sensor in the first region of the logic element, and where a refresh rate for one or more sections of the memory stack is modified at least partially on the basis of the estimated temperature conditions for the memory stack. [23] System according to claim 22, wherein the memory controller modifies the refresh rate for one or more sections of the memory stack at least partially on the basis of the estimated temperature conditions for the memory stack. [24] System according to claim 23, wherein the memory controller modifies the refresh rate by instructing a memory element with respect to a refresh rate for the memory element. [25] System according to claim 23, wherein the memory controller modifies the refresh rate by performing one or more refresh cycles for the memory element at a time when the memory element itself is not performing any refresh cycles. [26] System according to claim 22, wherein the storage device provides data regarding the estimated temperature conditions for the storage stack to a storage element of the storage stack, wherein the storage element modifies the refresh rate for the storage element using the estimated temperature conditions. [27] Non-volatile, computer-readable storage medium containing data stored on it which represents sequences of instructions which, when executed by a processor, cause the processor to perform operations, wherein the operations include: Collecting temperature data from one or more temperature sensors in a logic chip, wherein the logic chip is coupled with a memory stack, Estimating the temperature conditions of the memory stack based on the collected temperature data and the location of each of the one or more temperature sensors, Determining a recommended refresh rate for each of one or more sections of the memory stack, and Setting – after determining that a refresh rate of a section of the memory stack differs from a recommended refresh rate – the refresh rate for the section of the memory stack.