Semiconductor devices

Abstract

Semiconductor device (100), comprising: an epitaxial buffer layer (202); an adjacent epitaxial layer (204) arranged on the epitaxial buffer layer (202); a multitude of trench structures (111-114) extending into the adjacent epitaxial layer (204), comprising the multitude of trench structures: a first plurality (112, 114) of the plurality of trench structures, wherein each trench structure in the first plurality of trench structures comprises a gate electrode (216) in contact with gate metal (135) and insulated from source metal (125) by an intermediate oxide layer (224), wherein each trench structure in the first plurality further comprises a source electrode (214) made of polysilicon material in contact with the source metal, wherein the gate electrode (216) is separated from the adjacent epitaxial layer (204) by a gate oxide (220), wherein the source electrode (214) is separated from the adjacent epitaxial layer (204) by a shield oxide (218), and wherein each trench structure in the first plurality is adjacent to both a respective first source region (208) and a respective second source region (208); a second plurality (111, 113) of the plurality of trench structures, comprising blocked trench structures that are nested alternately with the first plurality of trench structures such that each further trench structure of the plurality of trench structures is blocked, wherein each of the blocked trench structures is adjacent to both a respective first source region (208) and a respective second source region (208), wherein each blocked trench structure of the blocked trench structures is filled with the polysilicon material, such that only a single polysilicon region (235) is formed within each blocked trench structure, wherein each single polysilicon region is in contact with the source metal and is separated from the adjacent epitaxial layer (204) by the shield oxide (238),and wherein a lower side of the individual polysilicon region and a lower side of the source electrode are essentially aligned in the same horizontal plane to each other.

Description

STATE OF THE ART

[0001] To realize an energy-efficient power conversion system, power MOSFETs (metal-oxide-semiconductor field-effect transistors) used as core switches rely on low gate charges and low on-state resistances. For example, in a DC-to-DC converter (direct current), such as a synchronous buck converter, two MOSFETs are used, one as the "high-side" MOSFET and the other as the "low-side" MOSFET. The high-side MOSFET is controlled by an external enable signal and source current to a load, while the low-side MOSFET connects or disconnects the load to ground, thus draining current from the load.

[0002] There are some specific features and requirements for each of the high-side and low-side MOSFETs. For example, while lower on-resistances are desired for the low-side MOSFET, high-speed switching characteristics with low gate charges are desirable for the high-side MOSFET.

[0003] One of the widely used metrics for MOSFET performance is FOM (Figure of Merit), defined as the gate charge multiplied by the drain-to-source resistance at the specified gate voltages. A lower value for this figure of merit translates to better performance for high-side MOSFETs.

[0004] A MOSFET that can achieve lower gate charges and thus a lower figure of merit would be both useful and beneficial as, for example, a high-side MOSFET in a DC-to-DC converter.

[0005] The document WO 2011 / 050 115 A2 discloses a semiconductor device comprising: a plurality of trench structures extending into an epitaxial layer, wherein the plurality of trench structures comprises: a first plurality of the plurality of trench structures, wherein each trench structure in the first plurality of trench structures comprises a gate electrode in contact with gate metal and insulated from source metal by an intermediate oxide layer, wherein each trench structure in the first plurality further comprises a source electrode made of polysilicon material in contact with the source metal, wherein the gate electrode is separated from the epitaxial layer by a gate oxide, wherein the source electrode is separated from the epitaxial layer by a shield oxide, and wherein each trench structure in the first plurality adjoins both a respective first source region and a respective second source region,a second plurality of the plurality of trench structures, each of the trench structures adjacent to a source region, each trench structure of the blocked trench structures being filled with the polysilicon material to form only a single polysilicon region within each trench structure, each single polysilicon region being in contact with the source metal and separated from the epitaxial layer by the shield oxide, and a lower side of the single polysilicon region and a lower side of the source electrode being aligned substantially in a same horizontal plane.

[0006] The document EP 0 717 450 A2 discloses a semiconductor device comprising: a plurality of trench structures extending into an epitaxial layer, wherein the plurality of trench structures comprises: a first plurality of the plurality of trench structures, wherein each trench structure in the first plurality of trench structures comprises a gate electrode insulated from source metal by an intermediate oxide layer, wherein each trench structure of a first plurality further comprises a source electrode in contact with the source metal, wherein the gate electrode is separated from the epitaxial layer by a gate oxide, wherein each trench structure in the first plurality is adjacent to both a respective first source region and a respective second source region, a second plurality of the plurality of trench structures comprising blocked trench structures,which are interleaved with the first plurality of trench structures in an alternating manner such that each further trench structure of the plurality of trench structures is blocked, wherein each blocked trench structure of the blocked trench structures is filled with the polysilicon material such that only a single polysilicon region is formed within each blocked trench structure, wherein each single polysilicon region is in contact with the source metal and is separated from the epitaxial layer by shield oxide.

[0007] US 2005 / 0 167 742 A1 discloses a trench filled with polysilicon and a gate trench. The gate trench and the trench are arranged alternately. Furthermore, the aforementioned document discloses a split-gate trench and a trench filled with polysilicon that is in contact with the source metal, with the two trench types being arranged alternately. SUMMARY

[0008] Embodiments according to the present invention provide efficient and novel metal / insulator / semiconductor (MIS) devices (e.g., MOSFETs) with lower gate charges and lower FOM values.

[0009] In one embodiment, a semiconductor device (e.g., a MOSFET) includes a first group of trench structures and a second group of trench structures (for simplicity, the trench structures may be referred to as trenches hereinafter). Each of the trenches in the first group includes a gate electrode in contact with gate metal and also includes a source electrode in contact with source metal and insulated from the gate electrode. Each of the trenches in the second group is blocked.

[0010] In one embodiment, a layer of source metal traverses the first group of utilized trenches and the second group of blocked trenches. In such an embodiment, each of the blocked trenches encloses a single polysilicon region. The polysilicon regions in each of the blocked trenches are substantially in the same plane as the source and gate electrodes in the utilized trenches. The polysilicon regions in each of the blocked trenches are in contact with the layer of source metal within the active core region of the semiconductor device and are also in contact with the gate metal. In contrast, in utilized trenches, the gate electrode is disposed between the source electrode and the layer of source metal and is insulated from the layer of source metal, but in contact with the gate metal.

[0011] Also, in the trenches used, the source electrode is in contact with the source metal outside the active core region, but is insulated from the source metal layer within the active core region.

[0012] The second group of blocked trenches is nested with the first group of inserted trenches. In one embodiment, the first group of inserted trenches and the second group of blocked trenches are nested in an alternating manner. That is, in one embodiment, every second trench is blocked. In other embodiments, every third trench is blocked, or every fourth trench is blocked, and so on.

[0013] As an unexpected benefit, if one half of the trenches is blocked, for example, the drain-to-source resistance increases by less than a factor of two, instead of a factor of two as expected, while the gate charge decreases by a factor of two. As a result, the value of the FOM is advantageously reduced by blocking selected trenches, as described above.

[0014] In one embodiment, the features of the semiconductor device as described above are implemented in a MOSFET. In such an embodiment, such features are implemented in a high-side MOSFET coupled to a low-side MOSFET in a DC-to-DC converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Like reference characters designate like elements throughout the drawings and the description. Fig. 1 shows a top-down view of a portion of a semiconductor device in an embodiment according to the present invention. Fig. 2 is a cross-sectional view showing elements of a semiconductor device in embodiments according to the present invention. Fig. 3 shows a top-down view of a portion of a semiconductor device in an embodiment according to the present invention. Fig.4 is a flowchart listing masks used in a method of manufacturing semiconductor devices in an embodiment according to the present invention. DETAILED DESCRIPTION

[0016] Some sections of the detailed descriptions that follow are presented in terms of procedures, logical blocks, processes, and other symbolic representations of the operation for fabricating and operating semiconductor devices. These descriptions and illustrations are the means used by those skilled in the art of semiconductor device fabrication to effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logical block, method, or the like is understood to be a self-consistent sequence of steps or instructions that leads to a desired result. The steps are those that require physical manipulations of physical quantities.It should be remembered, however, that all these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise specifically stated herein, as will become apparent from the following discussion, it should be understood that throughout this application, discussions regarding terms such as "forming," "performing," "manufacturing," "depositing," "etching," or the like refer to actions and methods for semiconductor device fabrication or operation.

[0017] Figures are not to scale, and only portions of the structures and the various layers that form such structures may be shown in the figures. Furthermore, manufacturing methods and steps may be performed in conjunction with the methods and steps discussed herein; that is, there may be a number of method steps before, between, and / or after the steps shown and described herein. Importantly, embodiments according to the present invention may be implemented in conjunction with these other (possibly conventional) structures, methods, and steps without significantly disrupting them. Generally speaking, embodiments according to the present invention may replace portions of a conventional device or method without significantly affecting peripheral structures, methods, and steps.

[0018] The term "trench," when discussed in the context of device fabrication, generally refers to an empty volume formed within a material. Such a trench may subsequently be filled with other material or materials. The term "trench," when discussed in the context of a fabricated semiconductor device, generally refers to the structure formed within the previously empty trench. A trench may also be referred to herein as a stripe. The meaning of the term "trench" in the following discussion will become clear in the context of the discussion.

[0019] Embodiments according to the present invention relate to novel structures for achieving lower gate charges and lower FOM values ​​in semiconductor devices, such as MOSFET devices, which can be used as high-side MOSFETs in, for example, DC-to-DC converters, such as synchronous buck converters.

[0020] Fig. Figure 1 is a top-down view showing certain elements of a semiconductor device 100 in one embodiment according to the present invention. Not all elements that may be included in a semiconductor device are shown in Fig. 1. Several levels are shown in Fig. 1; that is, for example, the source metal layer 125 is actually over (on top of) the stripes 111-116.

[0021] In the example of Fig.1, the device 100 includes a number of stripes (or cells 111-116) that are substantially parallel to each other in the active core region 105. The active core region 105 is the region indicated by the dashed lines in Fig. 1 is limited.

[0022] How to continue in connection with Fig. 2, each of the strips 111-116 is a trench structure. As will also be further described in connection with Fig.2, some of the stripes are blocked, while others are not. The blocked stripes are electrically and physically connected to the source metal layer 125 within the active core region 105, and are also electrically and physically connected to the gate metal layer 135 via the gate contact 137. The inserted stripes (those that are not blocked) are insulated from the source metal layer 125 within the active core region 105, but include a source electrode (see Fig. 2) which are electrically and physically connected to the source metal layer 125 via the source contact 127 outside the active core region, and also include a gate electrode (see Fig. 2) which is electrically and physically connected to the gate metal layer 135 via the gate contact 137.

[0023] Fig. 2 is a cross-sectional view (along the line AA in Fig.1) of the device 100 in an embodiment according to the present invention. Not all elements that can be included in a semiconductor device are shown in Fig. 2 shown.

[0024] Four trench structures 111-114 are shown. To simplify the discussion, the trench structures may be referred to simply as trenches in the following discussion. In the orientation of the Fig. 2, as in the alignment of the Fig. 1, trenches 111-114 are parallel to each other.

[0025] In the example of Fig. 2, device 100 includes a first epitaxial (or buffer) layer 202 and a second epitaxial layer 204. There may also be a drain region (not shown) beneath first epitaxial layer 202. Trenches 111-114 extend into second epitaxial layer 204.

[0026] A body region 206 (e.g., a p-doped region) is shown between adjacent trenches. Source regions 208 (e.g., n+-doped regions) are also shown between adjacent trenches. The source metal layer 125 extends across (traverses) the trenches 111-114. As described below, the source metal layer 125 is exposed to the electrodes in selected trenches (e.g., the trenches 112 and 114) in the active region 105 ( Fig. 1) of the device 100, but is in contact with the electrodes in other selected trenches (e.g., trenches 111 and 113) in the active core region. Accordingly, in the example of Fig. 2 trenches 111 and 113 are blocked, while trenches 112 and 114 are deployed (not blocked).

[0027] Trenches 112 and 114 may be referred to as split gates. Each of trenches 112 and 114 includes a first polysilicon region 214 (Poly-1), also referred to as a source electrode or a shield electrode. Each of trenches 112 and 114 also includes a second polysilicon region 216 (Poly-2), also referred to as a gate electrode. Source electrodes 214 are separated from adjacent epitaxial layer 204 by a shield oxide 218, and gate electrodes 216 are separated from adjacent epitaxial layer 204 by a gate oxide 220. The source electrodes 214 in the trenches 112 and 114 are insulated from the gate electrodes 216 in the trenches 112 and 114 by an intermediate oxide layer 222. In the trenches 112 and 114, the gate electrodes 216 are arranged between the source electrodes 214 and the source metal layer 125.The gate electrodes 216 are insulated from the source metal layer 125 by an interlayer isolation oxide layer 224. Referring also to FIG. Fig. 1, the source electrodes 214 in the trenches 112 and 114 are electrically and physically in contact with the source metal layer 125 via the source contact 127, and the gate electrodes 216 within the trenches 112 and 114 are electrically and physically in contact with the gate metal layer 135 via the gate contact 137 ( Fig. 1).

[0028] In the embodiment according to Fig. 2, each of the blocked trenches 111 and 113 includes a standalone polysilicon region 235 (Poly-1) connected to the source metal layer 125 and the gate metal layer 135 ( Fig.1) is in contact. The poly-1 regions 235 of the blocked trenches 111 and 113 are substantially in the same plane as the source electrodes 214 and the gate electrodes 216 in the inserted trenches. That is, in the orientation according to Fig. 2, the upper sides of the poly 1 regions 235 roughly coincide with the upper sides of the gate electrodes 216, and the lower sides of the poly 1 regions 235 roughly coincide with the lower sides of the source electrodes 214. The poly 1 regions 235 are separated from the adjacent epitaxial layer 204 by an oxide layer 238.

[0029] It is important that the poly-1 regions 235 are not isolated from the source metal layer 125; the source metal layer 125 is electrically and physically in contact with the poly-1 regions 235. Furthermore, with reference also to Fig.1, the poly-1 regions 235 in the trenches 111 and 113 are also electrically and physically in contact with the source metal layer 125 via the source contact 127 and with the gate metal layer 135 via the gate contact 137.

[0030] Thus, in the example according to Fig. 2 Half of the cells / strips / trenches are deployed (e.g., trenches 112 and 114) and half of the cells / strips / trenches are blocked (e.g., trenches 111 and 113). In other words, the deployed cells / strips / trenches are interleaved with the blocked cells / strips / trenches in an alternating manner, so that every second cell / strip / trench is blocked. This is Fig. 3, which shows a top-down view of device 100. In other embodiments, one-third (every third cell / stripe / trench blocked), one-quarter, one-fifth, and so on of the core cells / stripes may be blocked.

[0031] As mentioned above, a widely used measure of MOSFET performance is the FOM, which is defined as the gate charge multiplied by the drain-to-source resistance at specific gate voltages. A lower FOM value indicates better performance for high-side MOSFETs.

[0032] Using a core area as large as before, it can be expected that if half of the core cells / stripes / trenches are deployed and the other half of the core cells / stripes / trenches are blocked, then the gate charges would drop by half and the resistances would increase by a factor of 2. However, since there is current displacement in the drift region for high-density cell devices such as those described herein, some bias resistance from this region will be experienced. By blocking some (e.g., half) of the core cells / stripes / trenches, the carriers flowing through a side channel of the core cell / stripe will utilize the entire drift region, and thus less current displacement for carrier flow and less bias resistance from this region will be experienced.Consequently, in reality, the total drain-to-source resistances increase by a factor of less than 2 when half of the core cells / stripes / trenches are blocked.

[0033] On the other hand, the gate charges decrease proportionally according to the active core cell area. As a result of the combined effects on the drain-to-source resistance and the gate charge, a better FOM can be achieved using the approach described in the present disclosure.

[0034] This is illustrated by the results included in Table 1. "Rsp4.5V(core)" represents the resistivity between the drain and source at a gate voltage of 4.5V for a standalone core cell / strip. "Rds(on) @4.5V typical" demonstrates a final product resistance between the drain and source at a gate voltage of 4.5V in a Power PAK. ®1212 package. "Qgsp4.5V" represents the specific gate charges per unit active area at a gate voltage of 4.5V. "Qg4.5V" indicates a value of the total gate charges at a gate voltage of 4.5V. The FOM is the product of Qg4.5V and Rds(on) @4.5V typically. Embodiments according to the present invention improve FOM values ​​by approximately 32% when half of the core cells / stripes / trenches are blocked. Table 1 - Example results units State of the art Embodiment of the present disclosure Percentage change Rsp4.5V (core) mΩ·mm 2 4,43 6,22 40% Rds(on) @4.5V (typical) mΩ 2,2 2,8 28% Qgsp4.5V nC / mm 2 8,3 4,4 -47% Qg4.5V nC 24,1 12,8 -47% FOM Qg4.5*Rds4.5 53 36 -32%

[0035] Fig.4 is a flowchart 400 illustrating the sequence of masks used to form the blocked stripes / trenches and the inserted stripes / trenches in one embodiment according to the present invention. Other masks and manufacturing process steps may be used with the masks included in the following discussion. The following discussion is intended to highlight changes in the manufacturing process introduced to form the above-noted blocked trenches. Fig. 4 is also made with reference to Fig. 2 discussed.

[0036] In block 401, a trench mask is used to form empty trenches 111-114. In block 402, after Poly-1 is deposited in the trenches, a shield (source) poly etch block mask is configured so that the Poly-1 in the blocked trenches 111 and 113 is not exposed to etching, while the Poly-1 in the inserted trenches 112 and 114 is exposed to etching. Thus, the Poly-1 in the blocked trenches 111 and 113 is not etched back, but the Poly-1 in the inserted trenches 112 and 114 is etched back to form the source electrodes 214.

[0037] In block 403, an active mask is used to prevent the thick oxide layer 238 lining blocked trenches 111 and 113 from thinning to prevent poly-2 from being deposited into the blocked trenches. Trenches 112 and 114 are not protected by the active mask, so the gate oxide 220 is thinned prior to poly-2 deposition into trenches 112 and 114 to form gate electrodes 216.

[0038] In block 404, a gate poly etch block mask is used during an etch-back of the poly 2 regions. In block 405, a source implant mask is used to properly deposit source regions 208. In block 406, a body implant mask is used to properly deposit body regions 206. In blocks 407, 408, 409, and 410, poly contact, core contact, metal etch, and pad masks are used to form contacts 135 and 137 and to contact electrodes 214, 216, and 235 to the source metal and gate metal.

[0039] Thus, to form the blocked trenches 111 and 113, a shield poly etch block mask (block 402) and an active mask (block 403) are introduced or modified. Consequently, the blocked trenches can be formed without significantly disrupting the manufacturing process.

[0040] In summary, embodiments of semiconductor devices and embodiments of methods for fabricating such devices are described. Embodiments according to the invention can be used in high-density trench power MOS transistors and in the charge-balancing MOSFET family with a split-gate structure. Embodiments according to the invention can be used in high-side DC-DC converter applications.

[0041] Generally speaking, this document discloses semiconductor devices. It further discloses a semiconductor device including a first group of trench structures and a second group of trench structures. Each trench structure in the first group includes a gate electrode in contact with a gate metal and a source electrode in contact with a source metal. Each of the trench structures in the second group is blocked. The second group of blocked trench structures is interleaved with the first group of trench structures.

Claims

[1] A semiconductor device (100) comprising: an epitaxial buffer layer (202); an adjacent epitaxial layer (204) disposed on the epitaxial buffer layer (202); a plurality of trench structures (111-114) extending in the adjacent epitaxial layer (204), the plurality of trench structures comprising: a first plurality (112, 114) of the plurality of trench structures, each trench structure in the first plurality of trench structures having a gate electrode (216) in contact with gate metal (135) and insulated from source metal (125) by an intervening oxide layer (224), each trench structure in the first plurality further comprising a source electrode (214) made of polysilicon material in contact with the source metal, the gate electrode (216) being separated from the adjacent epitaxial layer (204) by a gate oxide (220), the source electrode (214) being separated from the adjacent epitaxial layer (204) by a shield oxide (218), and each trench structure in the first plurality being adjacent to both a respective first source region (208) and a respective second source region (208); a second plurality (111, 113) of the plurality of trench structures, comprising blocked trench structures that are interleaved with the first plurality of trench structures in an alternating manner such that each further trench structure of the plurality of trench structures is blocked, wherein each of the blocked trench structures adjoins both a respective first source region (208) and a respective second source region (208), wherein each blocked trench structure of the blocked trench structures is filled with the polysilicon material such that only a single polysilicon region (235) is formed within each blocked trench structure, wherein each single polysilicon region is in contact with the source metal and is separated from the adjacent epitaxial layer (204) by the shield oxide (238),and wherein a lower side of the single polysilicon region and a lower side of the source electrode are substantially aligned in a same horizontal plane., [2] A semiconductor device according to claim 1, wherein each blocked polysilicon region is in contact with the source metal at a respective upper side of each polysilicon region, and wherein each upper side coincides with the upper side of the gate electrode. [3] A semiconductor device according to any one of claims 1 or 2, comprising a layer of source metal passing through the first plurality of the plurality of trench structures and the second plurality of the plurality of trench structures, wherein the source electrode is in contact with the source metal outside an active core region of the semiconductor device, and wherein the source electrode is insulated from the layer of source metal within the active core region, and wherein the blocked trench structures are in contact with the layer of source metal within the active core region. [4] A semiconductor device according to claim 1 or 2, comprising a layer of the source metal passing through the first plurality of the plurality of trench structures and the second plurality of the plurality of trench structures, wherein the gate electrode is arranged between the source electrode and the layer of the source metal, and wherein the gate electrode is insulated from the layer of the source metal. [5] A semiconductor device according to any one of claims 1 or 2, comprising a metal oxide semiconductor field effect transistor, hereinafter referred to as MOSFET. [6] The semiconductor device of claim 5, wherein the MOSFET comprises a high-side MOSFET coupled to a low-side MOSFET in a DC-to-DC converter. [7] A semiconductor device (100) comprising: an epitaxial buffer layer (202); an adjacent epitaxial layer (204) disposed on the epitaxial buffer layer (202); a plurality of trench structures (111-114) extending in the adjacent epitaxial layer (204), the plurality of trench structures comprising: a first plurality of split-gate structures (112, 114), each split-gate structure of the first plurality of split-gate structures comprising a first electrode region (216) and also a second electrode region (214) made of polysilicon material, the first plurality of the plurality of trench structures including a first trench structure (112 or 114), the second electrode region (214) being separated from the adjacent epitaxial layer (204) by a gate oxide (220), and the first electrode region (216) being separated from the adjacent epitaxial layer (204) by a shield oxide (218); a second plurality of blocked second structures (111-113), wherein each blocked second structure of the plurality of blocked second structures comprises only a single polysilicon region (235) of the polysilicon material filling each blocked second structure, wherein each single polysilicon region is in contact with source metal (125) and is separated from the adjacent epitaxial layer (204) by a shield oxide (238), and wherein a lower side of the single polysilicon region and a lower side of the first electrode region are substantially aligned in a same horizontal plane, wherein the first plurality of split-gate structures comprises one half of the plurality of trench structures and the second plurality of blocked second structures comprises the remainder of the plurality of trench structures,wherein the second plurality of blocked second structures are interleaved with the first plurality of split-gate structures in an alternating manner such that each further one of the trench structures in the plurality of trench structures is blocked, wherein the second plurality of blocked second structures includes a blocked second trench structure (111 or 113), wherein a first source region (208) and a second source region (208) are between the first trench structure and the blocked second trench structure, wherein the first source region is adjacent to the first trench structure and the second source region is adjacent to the blocked second trench structure; and, wherein a layer of source metal is insulated from the first split-gate structures within an active region (105) of the semiconductor device and is in contact with each polysilicon region of the plurality of blocked second structures within the active region. [8] The semiconductor device of claim 7, wherein each first electrode region comprises a source electrode in contact with the source metal outside the active region, and wherein each second electrode comprises a gate electrode in contact with gate metal (135) outside the active region. [9] A semiconductor device according to claim 8, wherein each gate electrode is disposed between a corresponding source electrode and the source metal layer, and wherein the gate electrode is insulated from the source metal layer and also from the corresponding source electrode. [10] A semiconductor device according to any one of claims 7 or 9, wherein each polysilicon region is in contact with the source metal at a respective upper side of each individual polysilicon region, and wherein each upper side is coplanar with an upper side of each first electrode region.

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