Manufacturing process for a silicon carbide semiconductor device

Abstract

Method for manufacturing a silicon carbide semiconductor device with a vertical switching element of the inversion type having a trench gate structure (9), wherein the silicon carbide semiconductor device comprises: a substrate (1) of a first or second conductivity type made of silicon carbide, wherein a major surface thereof is a (0001) plane or a (000-1) plane or has an off angle with respect to the (0001) plane or the (000-1) plane; a drift layer (2) formed on the substrate (1) and consisting of silicon carbide of the first conductivity type with a lower impurity concentration than that of the substrate (1); a base region (3) formed on the drift layer (2) and made of silicon carbide of the second conductivity type; a source region (4) formed in an upper section of the base region (3) and composed of silicon carbide of the first conductivity type with a higher concentration than that of the drift layer (2); a trench (6) extending from a surface of the source area (4) through the base area (3) to a depth reaching the drift layer (2), wherein a side wall surface of this is formed in the direction of an (11-20) plane or a (1-100) plane; a gate insulation film (7) formed on an inner wall surface of the trench (6); a gate electrode (8) formed on the gate insulation film (7) in the groove (6); a source electrode (11) which is electrically connected to the source region (4) and the base region (3); and a drain electrode (12) formed on a rear surface side of the substrate (1), wherein a voltage applied to the gate electrode (8) is controlled to form an inversion-type channel region on a surface section of the base region (3) located on a side face of the trench (6), wherein a current can flow between the source electrode (8) and the drain electrode (12) through the source region (4) and the drift layer (2), the method for fabricating the silicon carbide semiconductor device comprising: Forming the trench (6) by etching; Performing sacrificial oxidation by forming and subsequently removing an oxide sacrificial film after forming the trench (6) and prior to removing damage; Performing chemical dry etching after sacrificial oxidation using a gas containing CF4 and O2 to remove any damage after the formation of the trench (6); and Formation of the gate insulation film (7) on the surface of the trench (6) without performing sacrificial oxidation after removal of the damage.

Description

TECHNICAL FIELD

[0001] The present invention relates to a manufacturing method for a silicon carbide (hereinafter referred to as "SiC") semiconductor device having a vertical switching element with a trench gate structure. STATE OF THE ART

[0002] As a SiC semiconductor device using a switching element, a vertical power MOSFET with a trench-gate structure has been proposed, in which a gate electrode is formed within a trench through an insulating film (see, for example, JP 2005-328013 A). In the vertical power MOSFET, a gate voltage is applied to a gate electrode formed within a trench through a gate insulating film to form an inversion-type channel in a p-type base region located on a trench-side surface, and a current can flow between a source electrode and a drain electrode.

[0003] The trench gate structure in a vertical power MOSFET with such a configuration is formed as follows. After a p-type base region and an n-type source region + -type on a drift layer of n - -type, a trench is formed which separates the p-type base region and the n-type source region. + -type through-hole, formed by etching. As a process for removing damage in trench etching, after performing a sacrificial oxidation process to remove a sacrificial oxide film after forming the sacrificial oxide film, a gate oxide film is formed by thermally oxidizing an inner wall surface of the trench. After forming polysilicon on a surface of the gate oxide film in the trench, a gate electrode is formed by patterning. By the above process, a trench gate structure is manufactured.

[0004] However, the present inventors found that when the trench gate structure is formed by the above method, the reliability of the gate oxide film is poor. In particular, it was confirmed that leakage current increases at the trench end.

[0005] From US 2012 0 161 154 A1 a method for producing a silicon carbide semiconductor device with a vertical inversion-type switching element having a trench gate structure is known, the silicon carbide semiconductor device comprising: a substrate (1) of a first or second conductivity type, made of silicon carbide, a main surface of which is a (0001) plane or a (000-1) plane or has an off-angle with respect to the (0001) plane or the (000-1) plane; a drift layer (2) formed on the substrate (1) and made of silicon carbide of the first conductivity type with a lower impurity concentration than that of the substrate (1); a base region (3) formed on the drift layer (2) and made of silicon carbide of the second conductivity type;a source region (4) formed in an upper portion of the base region (3) and made of silicon carbide of the first conductivity type with a higher concentration than that of the drift layer (2); a trench (6) formed from a surface of the source region (4) through the base region (3) to a depth reaching the drift layer (2), a sidewall surface of which is formed toward a (11-20) plane or a (1-100) plane; a gate insulation film (7) formed on an inner wall surface of the trench (6); a gate electrode (8) formed on the gate insulation film (7) in the trench (6); a source electrode (11) electrically connected to the source region (4) and the base region (3);and a drain electrode (12) formed on a back surface side of the substrate (1), wherein a voltage applied to the gate electrode (8) is controlled to form an inversion-type channel region at a surface portion of the base region (3) located on a side surface of the trench (6), wherein a current can flow between the source electrode (8) and the drain electrode (12) through the source region (4) and the drift layer (2), the method for manufacturing the silicon carbide semiconductor device comprising: forming the trench (6) by etching; performing sacrificial oxidation after forming the trench (6) and before removing any damage; performing chemical dry etching using a gas containing CF4 and O2 to remove any damage after forming the trench (6); and forming the gate insulation film (7) on the surface of the trench (6) without performing sacrificial oxidation after removing the damage.

[0006] US 6 096 607 A and US 7 241 694 B2 show similar prior art.

[0007] US 5,723,376 A teaches a method for manufacturing a silicon carbide (°SiC) semiconductor device with a vertical inversion-type switching element having a trench gate structure, the silicon carbide semiconductor device comprising: a substrate of a first or second conductivity type made of silicon carbide, a main surface of which is a (0001) plane or a (000-1) plane or has an off-angle with respect to the (0001) plane or the (000-1) plane; a drift layer formed on the substrate and made of silicon carbide of the first conductivity type with a lower impurity concentration than that of the substrate; a base region formed on the drift layer and made of silicon carbide of the second conductivity type; a source region formed in an upper portion of the base region and made of silicon carbide of the first conductivity type with a higher concentration than that of the drift layer;a trench formed from a surface of the source region through the base region to a depth reaching the drift layer, a sidewall surface of which is formed toward a (11-20) plane or a (1-100) plane; a gate insulating film formed on an inner wall surface of the trench; a gate electrode formed on the gate insulating film in the trench; a source electrode electrically connected to the source region and the base region;and a drain electrode formed on a back surface side of the substrate, wherein a voltage applied to the gate electrode is controlled to form an inversion-type channel region at a surface portion of the base region located on a side surface of the trench, wherein a current can flow between the source electrode and the drain electrode through the source region and the drift layer, the method of manufacturing the silicon carbide semiconductor device comprising: ; Forming the trench by etching; performing sacrificial oxidation after forming the trench and before removing any damage; removing any damage; performing etching to remove any damage after forming the trench; and forming the gate insulation film on the surface of the trench without performing sacrificial oxidation after removing any damage. SUMMARY OF THE INVENTION

[0008] An object of the present invention is to provide a SiC semiconductor device in which the occurrence of a leakage current is suppressed and which has higher reliability of the gate oxide film, and to provide a manufacturing method of a SiC semiconductor device.

[0009] A manufacturing method for a silicon carbide semiconductor device according to one aspect of the present invention is a method having the features recited in claim 1.

[0010] A silicon carbide semiconductor device according to another aspect of the present invention is a device having the features listed in claim 2, i.e., a device manufactured by the method of claim 1. Advantageous further developments are the subject of the dependent claims.

[0011] As described above, since the sidewall surface on which at least the channel region is formed is at an angle of 84° or more with respect to the (0001) plane or the (000-1) plane, leakage current can be suppressed. Therefore, a silicon carbide semiconductor device with higher gate insulation film reliability can be achieved.

[0012] In the silicon carbide semiconductor device, a voltage applied to the gate electrode is controlled to form an inversion-type channel region at a surface portion of the base region located on a side surface of the trench, and a current can flow between the source electrode and the drain electrode through the source region and the drift layer.

[0013] When the gate insulation film is formed without performing a sacrificial oxidation process, the step at the boundary between the source region and the base region in the sidewall surface of the trench is 10 nm or less. The above structure allows for the suppression of leakage current. Therefore, a silicon carbide semiconductor device can be created that can suppress leakage current and has higher reliability of the gate insulation film. SHORT DESCRIPTION OF THE DRAWING

[0014] The above and other details, aspects, and advantages of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawing: Fig. 1 is a perspective sectional view of a SIC semiconductor device according to a first embodiment of the present invention; Fig. 2A is a perspective sectional view showing in detail a process of manufacturing the SiC semiconductor device of Fig. 1 shows; Fig. 2B is a perspective sectional view showing in detail a process of manufacturing the SiC semiconductor device of Fig. 1 shows; Fig. 2C is a perspective sectional view showing in detail a process of manufacturing the SiC semiconductor device of Fig. 1 shows; Fig. 2D is a perspective sectional view showing in detail a process of manufacturing the SiC semiconductor device of Fig. 1 shows; Fig. 2E is a perspective sectional view showing in detail a process of manufacturing the SiC semiconductor device of Fig. 1 shows; Fig. 3 is a schematic diagram showing the results of the investigation of an emission image when only chemical dry etching is performed after the formation of a trench; Fig. 4 is a plan view of a vertical MOSFET with the layout of a trench gate structure used to investigate leakage current characteristics; Fig. 5 is a diagram showing results of the emission field when a gate insulation film is formed after performing a sacrificial oxidation process after the trench is formed; Fig. 6A is a plan view of the vertical MOSFET illustrating a relationship between the trench gate structure and the location of leakage occurrence; Fig. 6B is a representation of an angular relationship of a side wall surface of the trench in a section VIB-VIB in Fig. 6A; Fig. 6C is a representation of an angular relationship of a side wall surface of the trench in a section VIC-VIC in Fig. 6A; Fig. 6D is a representation of an angular relationship of a side wall surface of the trench in a section VID-VID in Fig. 6A; and Fig. 7 is a plan view of the vertical MOSFET illustrating a relationship between the trench gate structure and the position of leakage occurrence. EMBODIMENTS FOR CARRYING OUT THE INVENTION

[0015] The present inventors have extensively investigated the cause of the above problems. As a result, it has been clarified that the above problems occur due to the oxidation process performed before forming a gate oxide film. The details of the mechanism by which the above problems occur by performing a sacrificial oxidation process have not been conclusively clarified. However, it is a fact that if the sacrificial oxidation process is performed as a process immediately before forming the gate insulating film, then leakage at the trench end increases. If the gate insulating film is formed without performing the sacrificial oxidation process, or if, although the sacrificial oxidation process is performed, chemical dry etching (hereinafter referred to as "CDE") is performed afterward and then the gate insulating film is formed, an increase in leakage at the trench ends can be suppressed.

[0016] More specifically, according to Fig. 4, to examine the leakage characteristics, an oval trench gate structure J1 is formed into a plurality of stripes using a SiC substrate having an off-axis angle with respect to a (0001) plane. The oval trench gate structure J1 is of a structure in which rectilinear trench gate structures J1, each with a direction as the longitudinal direction, are paired adjacent to each other, and both ends of the respective paired trench gate structures J1 are connected to each other to form an arc shape. In order to uniform the characteristics of a long side portion of the trench gate structure J1, an off-axis direction of the SiC substrate (i.e., a direction parallel to a line in which the (0001) plane intersects a flat surface perpendicular to the plane) as viewed from the top of the SiC substrate is adjusted to the long side portion of the trench gate structure J1.

[0017] In a vertical MOSFET of the trench gate structure J1, a positive bias voltage (for example, approximately 40 V) is applied to a gate electrode, a source electrode and a drain electrode are connected to GND, and an emission image is observed to confirm the leakage characteristics. As a result, an emission image according to Fig. 5 received.

[0018] Since light is emitted at the positions of the two front edges of the trench gate structure J1 due to the emission image, it was found that the leakage increases at the two front ends of the trench gate structure J1. When the size of the light emission of the emission image is determined, it is found that one end (right end in the plane of the drawing of Fig. 5) the trench gate structure J1 is larger than the other end of it (left end in the plane of the drawing of Fig. 5) and the leakage current is larger.

[0019] To investigate the cause of the leakage current, a relationship between a shape of the trench gate structure J1 and angles formed between the respective inner wall surfaces of a trench J2 and a substrate plane direction or the (0001) plane and the positions of leakage occurrence is investigated. As a result, according to the Fig. 6A and Fig. 6B, in the long side portion of the trench gate structure J1, an angle formed between the (0001) plane and a sidewall surface of the trench J2 is 87°, since the long side portion and the off-axis direction coincide when viewed from above the SiC substrate. In contrast, according to Fig. 6C, at one (the right end in the plane of the figure) of the two arc ends of the trench gate structure J1, a sidewall surface on one inner peripheral side has an angle of 91° with respect to the (0001) plane, and a sidewall surface of another peripheral side has an angle of 83° with respect to the (0001) plane. As further shown in Fig. 6D, at the other end (left end in the plane of the figure) of the trench gate structure J1, a sidewall surface on an inner peripheral side has an angle of 83° with respect to the (0001) plane, and a sidewall surface on an outer peripheral side has an angle of 91° with respect to the (0001) plane.

[0020] Based on the results of Fig. 5, it can be estimated that a leak on the right side of the drawing plane in the figure of the trench gate structure J1 occurs in a wider area than at the left end in the drawing plane. Furthermore, if the results of the Fig. 6A to 6D are taken into account, it can be estimated that the leak occurs at the position forming an angle of 83° with respect to the (0001) plane, ie according to Fig. 7 on the outer peripheral side at the right end in the drawing plane of the trench gate structure J1 and the inner peripheral side at the left end of the drawing plane. The details of this mechanism are not yet fully understood. However, if the sacrificial oxidation process is performed as a process immediately before forming the gate oxide film, the leakage at the end of the trench J2 increases. If the gate oxide film is formed without performing the sacrificial oxidation process, the leakage at the end of the trench J2 increases. If the gate oxide film is formed without performing the sacrificial oxidation process, or even if the sacrificial oxidation process is performed, and CDE is then performed to form the gate oxide film, an increase in the leakage at the end of the trench J2 can be suppressed.

[0021] As a result, when the sacrificial oxidation process is performed immediately before formation of the gate oxide film, a leakage current is generated at a location on the sidewall surface of the trench J2 where the angle to the (0001) plane is 83° or less, and no leakage current is generated at a location where the angle exceeds 83°.

[0022] The above respective angles are obtained in an example where trench etching is performed such that the angles formed by the respective sidewall surfaces of trench J2 to a bottom surface of trench J2 become approximately 87°. The angles formed by the respective sidewall surfaces of trench J2 to the bottom surface of trench J2 can be set to 90°, but if the angles exceed 90°, there may be a disadvantage that the characteristic fluctuations of the MOSFET become large. For this reason, the above angle is set to 87° so as not to exceed 90° even if an etching error occurs. However, trench etching can be performed such that the angles formed by the respective sidewall surfaces of trench J2 to the bottom surface of trench J2 are set to 90° or another angle close to 90°.

[0023] Embodiments of the present invention will be described below with reference to the drawings. In the following respective embodiments, identical or equivalent parts are designated by the same reference numerals in the drawings. (First embodiment)

[0024] A first embodiment of the present invention will be described. In this example, a vertical switching element with a trench gate structure is exemplified by a SiC semiconductor device in which an inversion-type MOSFET is formed.

[0025] As in Fig. As shown in Figure 1, an n-channel inversion type MOSFET is formed in the SiC semiconductor device. MOSFETs having the same structure as the MOSFET in the figure are arranged adjacent to each other in a plurality of rows to form the MOSFETs of a plurality of cells. Specifically, a semiconductor substrate made of an n-channel substrate 1 is+ -type SiC, and the respective components of the MOSFET are formed over the substrate 1 of the n + -Type designed to configure the MOSFET.

[0026] The substrate 1 of the n + -type is formed from a SiC substrate having an off-angle of, for example, 4° with respect to the (0001) plane, an n-type impurity concentration, for example nitrogen, of, for example, 1.0 × 10 19 / cm 3 and has a thickness of approximately 300 µm. A drift layer 2 of n - -type SiC, for example, has an n-type impurity concentration, for example nitrogen, of, for example, 3.0 × 10 15 up to 2.0 × 10 16 / cm 3 and a thickness of approximately 10 to 15 µm and is deposited on a surface of the substrate 1 of the n + -type. Since the crystallinity of drift layer 2 depends on the n - -type equal to that of substrate 1 of n +-type, the surface of the drift layer 2 is of n - -Type also provided with an off-angle of 4° with respect to the (0001) plane.

[0027] A p-type base region is formed on a surface layer portion of the n-type drift layer 2 - -type, and a source region 4 of the n + -Type and contact layers 5 from p + -type are formed on an upper layer portion of the p-type base region 3

[0028] For example, the p-type base region 3 has a p-type impurity concentration such as boron or aluminum of 1.0 × 10 16 up to 2.0 × 10 19 / cm 3 and a thickness of approximately 2.0 µm. The source region 4 of the n + -type has an impurity concentration (surface concentration) of n-type such as nitrogen in the surface layer section of, for example, 1.0 × 10 21 / cm 3 and a thickness of 0.3 µm. Each of the contact layers 5 from the p+ -Type has a p-type impurity concentration (surface concentration) such as boron or aluminum in the surface layer portion of, for example, 1.0 × 10 21 / cm 3 and a thickness of approximately 0.3 µm. The source region 4 of the n + -type is arranged on both sides of a trench gate structure 9, which will be described later, and the contact layer 5 of the p + -type is located on one side of the source area 4 of the n + -Type opposite the trench gate structure 9.

[0029] Furthermore, a structure which has the base region of p-type and the source region 4 of n + -type, to the drift layer 2 of the n - -type and has a bottom of a certain width, so that the trench 6 is formed with a width of, for example, 0.5 to 2.0 µm and a depth of 2.0 µm or more (for example, 2.4 µm). The base region 3 of the p-type and the source region 4 of the n +-Type as described above are arranged in contact with the side surface of the trench 6.

[0030] Trench 6 is according to Fig. 1 with an x-direction as the width direction, a y-direction as the length direction and a z-direction as the depth direction, and a plurality of the trenches 6 are in Fig. 1 are arranged in a row in the x-direction, with the respective trenches 6 arranged parallel to each other. The respective trenches 6 may be formed in an oval shape, where the two front ends of the respective trenches 6 are connected to each other in an arc shape to form two adjacent paired trenches, or they may be formed in a strip shape, where the respective trenches 6 are arranged in strips.

[0031] Furthermore, the inner wall surface of the trench 6 is covered with a gate oxide film 7, and a gate electrode 8 formed on a surface of the gate oxide film 7 and made of doped poly-Si is embedded inside the trench 6. The gate oxide film 7 is formed by thermally oxidizing the inner wall surface of the trench 6, and the thickness of the gate oxide film 7 is approximately 100 nm on both sides of the side surface and the bottom of the trench. The trench gate structure 9 has the structure described above.

[0032] A source electrode 11 and a gate line (not shown) are formed over the source region 4 of the n + -Type and a surface of the contact layers 5 of p +-type and a surface of the gate electrode 8 via an interlayer insulating film 10. The source electrode 11 and the gate line are made of a plurality of metals (for example, Ni / Al), and a part of the source electrode 11 and the gate line is in contact with at least the n-type SiC (in particular, the n + -type or the n-doped gate electrode 8) is made of a metal that can make ohmic contact with the n-type SiC. A part of the source electrode 11 and the gate line in contact with at least the p-type SiC (in particular the p-type contact layer 5) + -type or the p-doped gate electrode 8) is made of a metal that can make ohmic contact with the p-type SiC. The source electrode 11 and the gate line are formed on the interlayer insulation film 10 so that they are electrically insulated from each other. The source electrode 11 comes into electrical contact with the source region 4 of the n-type+ -type and the contact layer 5 of the p + -type via contact holes formed in the interlayer insulation film 10, and the gate line is in electrical contact with the gate electrode 8.

[0033] A drain electrode 12 in electrical connection with the substrate 1 of the n + -type is on a back side of the substrate 1 of the n + -type. With the above structure, a MOSFET with the trench gate structure 9 of the inversion type of the n-channel type is formed.

[0034] In the MOSFET having the inversion-type trench gate structure 9, the inversion-type channel is not formed in the p-type base region 3 in a state before a gate voltage is applied to the gate electrode 8. Therefore, even if a positive voltage is applied to the drain electrode 12, electrons can enter the p-type base region 3 from the n-type source region 4. +-type, and no current flows between source electrode 11 and drain electrode 12.

[0035] When a desired gate voltage is applied to the gate electrode 8, the inversion-type channel is formed at a surface of the p-type base region 3, which comes into contact with the trench 6. For this reason, electrons implanted from the source electrode 11 reach the n-type drift layer 2. - -type after passing through the channel leading from source area 4 of the n + -type to the p-type base region 3. With the above structure, a current can flow between source electrode 11 and drain electrode 12.

[0036] The following describes a method for manufacturing the MOSFET with the trench gate structure according to Fig. 1 based on the Fig. 2A to 2E.

[0037] In a Fig. In the process shown in Figure 2A, the substrate 1 is removed from the n +-type SiC substrate having an off-angle with respect to the (0001) plane, wherein the n-type impurity concentration, for example nitrogen, is, for example, 1.0 × 10 19 / cm 3 and the thickness is approximately 300 µm. A drift layer 2 of n - -type SiC, for example, has an n-type impurity concentration, for example nitrogen, of, for example, 3.0 × 10 15 up to 2.0 × 10 16 / cm 3 and a thickness of approximately 15 µm and can be epitaxially grown on a surface of the substrate 1 of the n + -type to form an epitaxial substrate. Then, the p-type base region 3, which has a p-type impurity concentration such as boron or aluminum of, for example, 1.0 × 10 16 up to 2.0 × 10 19 / cm 3 and has a thickness of about 2.0 µm, on the surface layer portion of the drift layer 2 of n --Type by ion implantation of p-type impurities, such as boron or aluminum.

[0038] In a Fig. In the process shown in Figure 2B, a mask (not shown) made of, for example, a low-temperature oxide film (LTO) is formed on the p-type base region 3, and thereafter, the mask is opened in a region where the n-type source region 4 is formed. + -type is to be formed by a photolithography process. Afterwards, n-type impurities (for example nitrogen) are ion implanted.

[0039] Furthermore, after the previously used mask has been removed, another mask (not shown) is formed again, and the mask is opened in a region where the contact layer 5 of the n + -type is to be formed through the photolithography process. P-type impurities (e.g., boron or aluminum) are then ion-implanted.

[0040] Then the implanted ions are activated. The source region 4 of the n + -type, which, for example, has an n-type impurity concentration (surface concentration), for example nitrogen, of 1.0 × 10 21 / cm 3 and a thickness of approximately 0.3 µm is formed. The contact layer 5 of the p + -type, which has a p-type impurity concentration (surface concentration), for example boron or aluminum, of 1.0 × 10 21 / cm 3 and has a thickness of approximately 0.3 µm is formed. The mask is then removed.

[0041] In a Fig. 2C, after an etching mask (not shown) is applied to the p-type base region 3, the n-type source region 4, + -type and the contact layer 5 of the p +-type, the etching mask is opened in a region where the trench 6 is to be formed. Then, a trench etching process is performed using the etching mask to form the trench 6. As a result, the trench 6 is formed in which the longitudinal direction coincides with the off-axis direction.

[0042] At this time, the trench 6 is formed in the direction of the (11-20) plane or the (1-100) plane so that each of the sidewall surfaces of the trench 6 substantially forms the (11-20) plane or the (1-100) plane, and a trench etching condition is set so that the angle formed by the sidewall surface with respect to the bottom surface of the trench 6 is, for example, 87°. For this reason, when the respective trenches 6 are formed in an oval shape in which the two front ends of the respective trenches 6 are connected to each other, in the front end of one trench 6, the angle formed between the (0001) plane and the sidewall surface of the outer peripheral side becomes 83°, and the angle formed between the (0001) plane and the sidewall surface of the inner peripheral side becomes 91° (see Fig. 6C). Further, in the front end of another trench 6, the angle between the (0001) plane and the outer peripheral sidewall surface becomes 91°, and the angle between the (0001) plane and the inner peripheral sidewall surface becomes 83°. After that, the etching mask is removed.

[0043] In a Fig. In the process shown in Figure 2D, the gate oxide film 7 is formed by deposition and without performing the sacrificial oxidation process, after the formation of the trench 6, the damage removal process is performed by CDE using a gas containing, for example, CF4 and O2. If a sacrificial oxidation is performed in this situation, an accelerated oxidation is performed because the source region 4 is separated from the n-type. +-type has a higher impurity concentration than the p-type base region 3. However, since the sacrificial oxidation process is not carried out, accelerated oxidation does not occur. For this reason, the step at the interface between the n-type source region 4 and the p-type base region 3 is + -type and the p-type base region 3 in the sidewall area of ​​the trench 6 10nm small or smaller.

[0044] In a Fig. In the process shown in Fig. 2E, a polysilicon layer doped with n-type impurities of approximately 440 nm is formed on the surface of the gate oxide film 7 at a temperature of 600°C, for example, and thereafter, an etch-back process or the like is performed to thereby leave the gate oxide film 7 and the gate electrode 8 within the trench 6.

[0045] Furthermore, after the interlayer insulating film 10 has been formed, the interlayer insulating film 10 is patterned to form the contact holes in communication with the source region 4 of the n + -type and the contact layer 5 of the p + -type. Furthermore, the contact opening connected to the gate electrode 8 is formed in a different cross section. Subsequently, after an electrode material film is formed to be embedded within the contact openings, the electrode material is patterned to form the source electrode 11 and the gate line. Thereafter, although not shown, the drain electrode 12 is formed on a back surface of the n-type substrate 1. + -Type to control the MOSFET according to Fig. 1 to be completed.

[0046] As described above, in this embodiment, the gate oxide film 7 is formed without performing the sacrificial oxidation process after the formation of the trench 6. Therefore, the SiC semiconductor device can be manufactured without being affected by the sacrificial oxidation process, which suppresses the partial generation of leakage current in the trench gate structure 9 and imparts higher reliability to the gate oxide film 7. Furthermore, in the case of thus forming the trench gate structure 9 without performing the sacrificial oxidation process, the barrier height θB on all inner wall surfaces of the trench 6 becomes 2.7 eV, and the barrier height φB that can suppress the occurrence of leakage current at both ends of the trench 6 can be obtained.

[0047] The leakage characteristics when only CDE is performed and the sacrificial oxidation process is not performed after the trench 6 has been formed are examined for illustrative purposes by evaluating the emission image while gradually increasing the gate voltage with the source electrode 11 and the drain electrode 12 connected to GND. Specifically, the trench gate structure 9 is used to perform the examination as shown in Fig. 4. As a result, according to Fig.3 confirm that the leakage current is generated when the gate voltage increases to a certain value, and that the leakage current is generated over the entire area of ​​the trench gate structure 9. The gate voltage at which the leakage current occurs is larger than in a case where the gate oxide film 7 is formed immediately after the sacrificial oxidation process. For this reason, the generation of the leakage current can be limited to only the two ends of the trench 6, and it can be seen that a uniform breakdown voltage is obtained over the entire area of ​​the trench 6. (Other embodiments)

[0048] In the above embodiment, the substrate 1 is of the n +-type, a SiC substrate is used whose main surface has an off-angle with respect to the (0001) plane. Alternatively, a SiC substrate can be used whose main surface has an off-angle with respect to the (000-1) plane. As an example, the case is described where the off-angle is 4°. Alternatively, a different angle can be used, for example, 2°. Furthermore, as the substrate 1 of the n + -Type, a SiC substrate can be used which has a (0001) plane or the (000-1) plane as the main surface.

[0049] That is, when the gate oxide film 7 is formed within the trench 6 after performing the sacrificial oxidation process, the angle formed by the sidewall surface where the channel region is formed in the sidewall surface of the trench 6 with respect to the (0001) plane (or the (000-1) plane) becomes 83° or less, and the leakage current increases. In contrast, it can be confirmed that the generation of leakage current can be suppressed when the angle of the sidewall surface of the trench 6 is set to 84° or greater, and preferably when the angle is set to 87°, and the generation of leakage current can be further suppressed.

[0050] Therefore, if the sacrificial oxidation process is not performed, the generation of a leakage current can be suppressed even if the angle with respect to the (0001) plane (or the (000-1) plane) becomes 83° or smaller, regardless of the off-angle. Even if the sacrificial oxidation process is performed, if, in the sidewall surface of the trench 6, at least the sidewall surface where the channel region is formed has an angle of 84° or larger, the generation of a leakage current can be suppressed. For this reason, the formation of the gate oxide film 7 without performing the sacrificial oxidation process is effective in a case where, in the sidewall surface of the trench 6, at least the sidewall surface where the channel region is formed has an angle of less than 84° with respect to the (0001) plane (or the (000-1) plane).Even when the sacrificial oxidation process is performed, if in the sidewall surface of the trench 6 at least the sidewall surface on which the channel region is formed has an angle of 84° or more, the generation of the leakage current can be suppressed. As a result, the trench 6 can be formed for this angle. In particular, in the case of using a SiC substrate with an off-angle of 4°, the angle of the sidewall surface on which a channel region is formed with respect to the bottom surface of the trench 6 can be set to 88° or more. Also, in the case of using a SiC substrate with an off-angle of 2°, the angle of the sidewall surface on which a channel region is formed with respect to the bottom surface of the trench 6 can be set to 86° or more. In the case of using a SiC substrate with an off-angle of 0°, i.e.a plane of the (0001) plane or (000-1) plane as the main surface, the angle of at least the side wall surface on which the channel region is formed with respect to the bottom surface of the trench 6 can be set to 84° or more.

[0051] In addition, even if the sacrificial oxidation process is performed, if the gate oxide film 7 is not formed immediately afterward, but the gate oxide film 7 is formed after the damage removal process performed by CDE, the generation of leakage current can be suppressed. For this reason, even if the sacrificial oxidation process is performed, the process of forming the gate oxide film 7 is prevented from being performed immediately after the sacrificial oxidation process, and as a result, the generation of leakage current can be suppressed.

[0052] In the above embodiment, the trench gate structure 9 is laid out with one direction as the longitudinal direction. However, this only shows an example of the trench gate structure 9, and the trench gate structure 9 can be designed in a rectangular or hexagonal layout. Also in this case, if the angle formed by the sidewall surface of the trench 6 with respect to the (0001) plane or (000-1) plane is smaller than 84°, the sacrificial oxidation process is not performed, or the sacrificial oxidation process is not performed immediately before the formation of the gate insulation film 7, if such a process is performed. As a result, the leakage current suppression effects can be obtained.Furthermore, the leakage current suppression effects are obtained when, in the sidewall surface of the trench 6, at least the sidewall surface on which the channel region is formed has an angle of 84° or more with respect to the (0001) plane or the (000-1) plane, even if the sacrificial oxidation process is performed.

[0053] In the above embodiment, the n-channel type MOSFET is described as an example in which the first conductivity type is n-type and the second conductivity type is p-type. Alternatively, the present invention can be applied to a p-channel type MOSFET in which the conductivity type of the respective constituent elements is reversed. Furthermore, in the above description, a trench gate structure MOSFET was described as an example, but the present invention can also be applied to an IGBT having the same trench gate structure. The IGBT changes the conductivity type of the substrate 1 from n-type to p-type in the embodiment, and the other structures and manufacturing method are identical to the above embodiment.

[0054] In the above embodiment, an example in which the present invention is applied was described. However, the configuration can be appropriately changed. For example, in the above embodiment, the gate oxide film 7 obtained by depositing the oxide film is shown as an example of a gate insulation film. Alternatively, the gate oxide film 7 may be formed by thermal oxidation or it may include a nitride film. When the gate oxide film 7 is formed by thermal oxidation, accelerated oxidation of the source region 4 of the n + -type. However, it has been confirmed that if the sacrificial oxidation process is not performed immediately before the formation of the gate oxide film 7, the leakage current suppression effect is obtained. For this reason, the gate oxide film 8 can be formed by thermal oxidation. In this case, however, the step at the interface between the source region 4 and the n +-type and the p-type base region 3 is not 10 nm or smaller, but is slightly larger than 10 nm in the sidewall area of ​​the trench 6.

[0055] When specifying the crystal orientation, the dash (-) should actually be placed above the desired number; however, due to limitations in computer applications, the dash is placed before the desired number in this specification. In this specification, when stating that the process of forming the gate oxide film 7 is not performed immediately after the sacrificial oxidation process or that the sacrificial oxidation process is not performed immediately before the gate oxide film 7, terms such as "immediately after" or "immediately before" are used. In this specification, "immediately after" and "immediately before" do not mean solely in terms of time, but mean that no other process is inserted between the respective processes.For this reason, “immediately after the sacrificial oxidation process” means that the process of forming the gate oxide film 7 follows the sacrificial oxidation process without any other process intervening, but the case that the damage removal process by CDE occurs in between is excluded.

Claims

[1] A method of manufacturing a silicon carbide semiconductor device having a vertical inversion type switching element with a trench gate structure (9), the silicon carbide semiconductor device comprising: a substrate (1) of a first or second conductivity type made of silicon carbide, a main surface of which is a (0001) plane or a (000-1) plane or has an off-angle with respect to the (0001) plane or the (000-1) plane; a drift layer (2) formed on the substrate (1) and made of silicon carbide of the first conductivity type with a lower impurity concentration than that of the substrate (1); a base region (3) formed on the drift layer (2) and made of silicon carbide of the second conductivity type; a source region (4) formed in an upper portion of the base region (3) and made of silicon carbide of the first conductivity type with a higher concentration than that of the drift layer (2); a trench (6) formed from a surface of the source region (4) through the base region (3) to a depth reaching the drift layer (2), a sidewall surface of which is formed in the direction of a (11-20) plane or a (1-100) plane; a gate insulation film (7) formed on an inner wall surface of the trench (6); a gate electrode (8) formed on the gate insulation film (7) in the trench (6); a source electrode (11) electrically connected to the source region (4) and the base region (3); and a drain electrode (12) formed on a rear surface side of the substrate (1), wherein a voltage applied to the gate electrode (8) is controlled to form an inversion-type channel region at a surface portion of the base region (3) located on a side surface of the trench (6), wherein a current can flow between the source electrode (8) and the drain electrode (12) through the source region (4) and the drift layer (2), the method for manufacturing the silicon carbide semiconductor device comprising: Forming the trench (6) by etching; performing a sacrificial oxidation by forming and then removing a sacrificial oxide film after forming the trench (6) and before removing any damage; performing a chemical dry etching after the sacrificial oxidation using a gas containing CF4 and O2 to remove any damage after formation of the trench (6); and Forming the gate insulation film (7) on the surface of the trench (6) without performing sacrificial oxidation after removing the damage.

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