Conversion of thin silicon transistors to silicon germanium and associated device

Abstract

Procedure that includes the following: Providing (1102) a semiconductor substrate comprising a channel body of a transistor device arranged on the semiconductor substrate, wherein the channel body comprises silicon; Forming (1106) a sheathing layer comprising germanium on the channel body; Forming (1108) a cover layer on the encapsulation layer; and Tempering (1110) of the channel body to cause the germanium to diffuse into the channel body, wherein the formation (1108) of the cover layer on the cladding layer is carried out prior to the tempering of the channel body and the tempering of the channel body with the cover layer arranged on the cladding layer is carried out.

Description

Area

[0001] Embodiments of the present disclosure relate generally to the field of integrated circuits, and more particularly to techniques and configurations associated with converting thin transistor elements from silicon (Si) to silicon germanium (SiGe). background

[0002] The mobility of charge carriers in transistor devices with silicon channel materials can be increased by introducing germanium into the silicon channel. However, current methods for providing germanium into the silicon channel can be costly or difficult due to shrinking transistor features associated with creating smaller transistor devices for greater performance and / or providing smaller die for smaller chip implementations, such as for use in mobile computing devices.

[0003] US 2011 / 0 193 178 A1 describes an integrated circuit structure comprising a substrate and a germanium-containing semiconductor fin above the substrate. The germanium-containing semiconductor fin has an upper portion with a first width and a neck region below the upper portion and with a second width that is smaller than the first width.

[0004] US 2012 / 0 309 173 A1 describes the formation of an insulated nanowire, wherein the insulation structure adjacent to the nanowire provides a substantially planar surface for the formation of microelectronic structures thereon.

[0005] US 2009 / 0 090 934 A1 describes a method for manufacturing a field-effect transistor, which comprises forming a mask of an insulating film on a Si-containing semiconductor layer formed on a semiconductor substrate, forming the semiconductor layer into a mesa structure by performing etching using the mask, wherein the mesa structure extends in a direction parallel to an upper surface of the semiconductor substrate, narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, wherein the two sidewalls extend in the direction and face each other, forming a gate insulating film covering the mesa structure with flattened sidewalls, forming a gate electrode covering the gate insulating film, and forming source and drain regions at portions of the mesa structure.wherein the sections are arranged on two sides of the gate electrode.,

[0006] US 2010 / 0 164 102 A1 describes a method and apparatus for providing a wafer containing silicon, the method comprising etching trenches into the wafer to form silicon fins, filling silicon oxide into the trenches, planarizing the silicon oxide, recessing the silicon oxide to a first thickness to form exposed silicon pedestals from the silicon fins, depositing SiGe over the exposed silicon pedestal, recessing the silicon oxide to a second thickness; undercutting the exposed silicon pedestals to form constricted silicon pedestals, thermally oxidizing and annealing the SiGe, and forming germanium nanowires.

[0007] The invention is defined in the independent claims. Embodiments of the invention are described in the dependent claims. Brief description of the drawings

[0008] Embodiments will be readily understood from the following detailed description when taken in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings. Fig. 1 schematically illustrates an example chip in wafer form and in singulated form in accordance with some embodiments. Fig. 2 schematically illustrates a perspective view of a transistor device in accordance with some embodiments. Fig. 3a-f schematically illustrate a cross-sectional side view of a transistor element after various manufacturing operations in accordance with some embodiments. Fig. 4a-d schematically illustrate a cross-sectional side view of a transistor element after other various manufacturing operations in accordance with some embodiments. Fig. 5 schematically illustrates a cross-sectional side view of a rib structure in accordance with some embodiments. Fig. 6 schematically illustrates a cross-sectional side view of a fin structure on a semiconductor substrate after converting a portion of the fin structure from Si to SiGe in accordance with some embodiments. Fig. 7 schematically illustrates a cross-sectional side view of another fin structure on a semiconductor substrate after converting a portion of the fin structure from Si to SiGe in accordance with some embodiments. Fig. 8 schematically illustrates a diagram depicting a composition profile of Ge through a transistor element in accordance with some embodiments. Fig. 9 schematically illustrates a cross-sectional side view of a transistor element including one or more nanowire structures, in accordance with some embodiments. Fig. 10 schematically illustrates a top view of a chip including n-type and p-type transistor elements, in accordance with some embodiments. Fig. 11 schematically illustrates a flowchart for a method of converting a transistor element from Si to SiGe in accordance with some embodiments. Fig. 12 schematically illustrates a flowchart for another method of converting a transistor element from Si to SiGe in accordance with some embodiments. Fig. 13 schematically illustrates an example system that may include a transistor element having at least a portion converted from Si to SiGe in accordance with techniques described herein, in accordance with some embodiments. Detailed description

[0009] Embodiments of the present disclosure provide techniques and configurations related to the conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). The thin transistor elements may include, for example, channel bodies of transistor devices of an integrated circuit (IC) chip. In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, wherein like reference characters designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the scope of the present disclosure.Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0010] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0011] The description may use perspective descriptions such as top / bottom, side, over / under, and the like. Such descriptions are used merely to facilitate discussion and are not intended to limit the application of embodiments described herein to any particular orientation.

[0012] The description may use the phrases "in one embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

[0013] The term "coupled with," along with its derivatives, may be used here. "Coupled" can mean one or more of the following. "Coupled" can mean that two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements are indirectly in contact with each other, yet still cooperate or interact with each other, and can mean that one or more other elements are coupled or connected between the elements that are said to be coupled. The term "directly coupled" can mean that two or more elements are in direct contact.

[0014] In various embodiments, the phrase "a first feature formed, applied, or otherwise disposed on a second feature" may mean that the first feature is formed, applied, or disposed over the second feature, and at least a portion of the first feature may be in direct contact (e.g., in direct physical and / or electrical contact) or indirect contact (e.g., by having one or more features between the first feature and the second feature) with at least a portion of the second feature.

[0015] As used herein, the term “module” may refer to, be a part of, or include an application-specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) executing one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality.

[0016] Fig. 1 schematically illustrates an example chip 101 in wafer form 10 and in singulated form 100 in accordance with some embodiments. In some embodiments, chip 101 may be one of a plurality of chips (e.g., chips 101, 101a, 101b) formed on a wafer 11 made of semiconductor material. The plurality of chips may be formed on a surface of wafer 11. Each of the chips may be a repeating unit of a semiconductor product including a plurality of transistors.

[0017] The transistors may be formed using transistor elements 104 as described herein, such as fin structures, nanowires, or planar structures that may be used to form channel bodies of the transistors. Although the transistor elements 104 are depicted in rows that form a substantial portion of the chip 101 in Fig. 1, the subject matter is not limited in this respect, and any other suitable configuration of the transistor elements 104 may be used according to various embodiments.

[0018] After a manufacturing process of the semiconductor product is completed, the wafer 11 may undergo a singulation process in which each of the chips (e.g., chip 101) is separated from one another to provide discrete "die" pieces of the semiconductor product. The wafer 11 may have any of a variety of sizes. In some embodiments, the wafer 11 has a diameter ranging from about 25.4 mm to about 450 mm. In other embodiments, the wafer 11 may have other sizes and / or other shapes. According to various embodiments, the transistor elements 104 may be arranged on a semiconductor substrate in wafer form 10 or singulated form 100. Transistor elements 104 described herein may be integrated into a chip 101 for logic or memory, or combinations thereof.

[0019] Fig. 2 schematically illustrates a perspective view of a transistor device 200 in accordance with some embodiments. In some embodiments, the transistor device 200 includes a semiconductor substrate 202, a fin structure 204 including a portion made of SiGe alloy (hereinafter "SiGe portion 204a") and a portion made of Si (hereinafter "Si portion 204b"), electrically insulating material 206, a gate 208 including a gate dielectric 208a and a gate electrode 208b, which are coupled as can be seen.

[0020] The transistor device 200 may, in various embodiments, represent a transistor or a portion of a transistor. For example, the fin structure 204 may extend along a surface of the semiconductor substrate 202 (e.g., through the material of the gate 208). A source and a drain (not shown) may be formed on the portions 210a and 210b of the fin structure 204 separated by the gate 208 to provide a source and drain for mobile charge carriers (e.g., holes or electrons) that may flow through the channel body 204c formed from the fin structure 204. The gate 208 may, for example, be configured to control the flow of the mobile charge carriers through the channel body 204c by applying a threshold voltage to the gate electrode 208b.

[0021] The channel body 204c may include a portion of the fin structure 204 formed from Si of the semiconductor substrate 202. In some embodiments, the channel body 204c may include portions of the SiGe portion 204a of the fin structure 204 and may be disposed in a gate region between the source and drain.

[0022] The semiconductor substrate 202 may be made of Si in some embodiments. For example, the semiconductor substrate 202 may include n-type or p-type (100) barrier-oriented Si, where the crystal directions of the semiconductor substrate 202 are symbolized by the convention (xyz), where x, y, and z represent respective crystallographic planes in three dimensions that are perpendicular to each other. For example, the semiconductor substrate 202 may include material of a (100) direction truncated in a range between about 2 degrees to about 8 degrees toward a (110) direction. Other truncation orientations or a semiconductor substrate 202 without a truncation orientation may be used. Truncation may eliminate antiphase boundaries. The semiconductor substrate 202 may have a high resistivity between about 1 Ω-cm to about 50 kΩ-cm. In other embodiments, the semiconductor substrate 202 may include other materials.In some embodiments, semiconductor substrate 202 is part of a singulated die of a wafer. In one embodiment, the semiconductor substrate is a p-type substrate.

[0023] According to various embodiments, the SiGe portion 204a of the fin structure 204 may be formed by converting a transistor element, such as the fin structure 204, from Si to SiGe using techniques described herein. In the depicted embodiment, only a portion (e.g., the SiGe portion 204a) of the fin structure 204 is converted from Si to SiGe. The Si portion 204b of the fin structure 204 may, in some embodiments, be comprised of a defect-free single crystal. In other embodiments, most or all of the transistor element (e.g., the fin structure 204) may be converted from Si to SiGe.

[0024] Transistor device 200 may be p-type or n-type. Channel body 204c formed using SiGe portion 204a may provide greater mobility of mobile charge carriers for the p-type. For example, increasing a concentration of germanium (Ge) in channel body 204c may increase the mobility of electrons or holes due to the nature of the material. A second mechanism further increases the mobility of holes in the p-channel (e.g., the channel of the PMOS device) by providing compression to channel body 204c. Compression of SiGe portion 204a will reduce the mobility of electrons for the n-channel (e.g., the channel of the NMOS device). Thus, increasing the concentration of Ge in the n-channel may result in little to no mobility improvement for electrodes. In one embodiment, the transistor device 200 is p-type (e.g., a PMOS device).The PMOS device may have a p-channel that is n-type doped, and the NMOS device may have an n-channel that is p-type doped.

[0025] The electrically insulating material 206 may be deposited on the semiconductor substrate 202 and may be adjacent to the fin structure 204, as can be seen. The electrically insulating material 206 may include any suitable trench isolation (STI) material. In some embodiments, the electrically insulating material 206 may include dielectric materials known to be applicable in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon oxide, carbon-doped oxide (CDO), silicon nitride, organic polymers such as octafluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilanes such as silsesquioxane, siloxane, or organosilane glass.

[0026] The gate dielectric 208a may be formed on a channel body 204c and may be made of a material such as silicon dioxide (SiO2) or a high-k material. Examples of high-k materials that may be used to form the gate dielectric 208a include, but are not limited to, hafnium oxide, hafnium silicon oxide, lathanium oxide, lathanium aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric 208a to improve its quality when using a high-k material.In some embodiments, the gate dielectric 208a may include a replacement oxide, which is subsequently removed in a process flow according to known techniques together with a replacement gate electrode and replaced by a high-k gate dielectric and a metal gate.

[0027] The gate electrode 208b may be formed on the gate dielectric 208a and may consist of at least one p-type work function metal or one n-type work function metal, depending on whether the transistor is to be a PMOS (e.g., p-type) or NMOS (e.g., n-type) transistor. In some embodiments, the gate electrode 208b may consist of two or more metal layers, wherein at least one metal layer is a work function metal layer and at least one metal layer is a fill metal layer. In some embodiments, the gate electrode 208b is a polysilicon gate electrode. In other embodiments, the gate electrode 208b is a replacement polysilicon gate electrode that is subsequently removed in a process flow according to known techniques and replaced with a metal gate electrode.

[0028] For a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. A p-type metal layer can enable the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that can be used for the gate electrode 208b include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An n-type metal layer can enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.

[0029] In some embodiments, a pair of spacers (not shown) may bracket the gate 208. For example, the spacers may be disposed on opposite surfaces of the gate electrode 208b. The spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming spacers may generally include deposition and etching processes and / or other known techniques.

[0030] The transistor device 200 of Fig. Figure 2 depicts a tri-gate transistor configuration. In other embodiments, similar principles and techniques described herein for converting a transistor element from Si to SiGe may be used for other transistor configurations, including, for example, planar, dual-gate, all-around (AAG) (also referred to as "gate all around"), wire (e.g., nanowire), and other suitable transistor configurations.

[0031] Fig. 3a-f schematically illustrate a cross-sectional side view of a transistor element (e.g., a fin structure) after various manufacturing operations in accordance with some embodiments. Structures, techniques, and configurations associated with the Fig. 3a-f can be achieved with analogous structures, techniques and configurations used in conjunction with Fig. 2, and vice versa.

[0032] Referring to Fig. 3a depicts a transistor element 300a after applying and patterning a mask material 312 on the semiconductor substrate 302. In some embodiments, the mask material 312 may be a hard mask, such as silicon oxide. In some embodiments, the mask material 312 may be a photodefinable material. Patterning may include lithography and / or etching processes in some embodiments.

[0033] Referring to Fig. 3b depicts a transistor element 300b after removing the semiconductor substrate 302 to form one or more fin structures 304 (e.g., hereinafter "fin structures 304"). The mask material 312 may protect portions of the semiconductor substrate 302 from a removal process, such as an anisotropic etching process, that removes material of the semiconductor substrate 302. The removal process may form trenches in areas of the removed material of the semiconductor substrate 302 and form the fin structures 304 in areas protected by the mask material 312.

[0034] Referring to Fig. 3c depicts a transistor element 300c after applying an electrically insulating material 306 to the semiconductor substrate 302. The hard mask 312 may be removed by etching processes, and the electrically insulating material 306 may be applied to surfaces of the semiconductor substrate 302 and the fin structures 304. The electrically insulating material 306 may be removed using, for example, an etching process to expose an end portion of the fin structures 304 while still covering a base portion of the fin structure 304, as can be seen.

[0035] Fig. 3d-f depict a transistor element after actions in accordance with a first technique for converting Si to SiGe (e.g., the method 1100 of Fig. 11). With reference to Fig. 3d depicts a transistor element 300d after deposition of Ge to form a cladding layer 314 comprised of Ge on the fin structures 304, as can be seen.

[0036] The deposition of Ge may be selective for the electrically insulating material 306. That is, in some embodiments, the Ge may be selectively deposited on the fin structures 304, but not on the electrically insulating material 306 to form the cladding layer 314. In some embodiments, the deposition of Ge on the fin structures 304 may be uniform, as shown in Fig. 3d, or be faceted (e.g. as in connection with Fig. 4b). In some embodiments, the cladding layer 314 may be crystalline, including, for example, single-crystal or polycrystalline configurations. In other embodiments, the cladding layer 314 may preferably be amorphous (e.g., by amorphous deposition) to provide a uniform profile as shown.

[0037] Selective deposition of Ge to provide an amorphous configuration of the cladding layer 314 may be performed according to a variety of suitable techniques, including, for example, gas source molecular beam epitaxy (GS-MBE), chemical vapor deposition (CVD), or rapid thermal CVD (RT-CVD). A high molecular weight precursor such as Digermane may be used for such selective deposition at temperatures between approximately 300°C and 400°C. Digermane may be used for selective deposition at pressures ranging from about 2.66 kPa to about 11.99 kPa. Germane may be used for selective deposition at low pressures ranging from about 2.6 Pa to about 66.6 Pa and may require higher process temperatures greater than 350°C. In other embodiments, the deposition of Ge may be non-selective for the electrically insulating material 306.

[0038] Selective deposition of Ge to provide a crystalline configuration of the cladding layer 314 may, in some embodiments, be performed using German, and the deposition temperature may be up to 500°C. In some embodiments, Ge in crystalline form may generally facet along (111) planes.

[0039] The fin structures 304 may be thin transistor elements. In some embodiments, a fin structure may have a thickness T1, as can be seen. The thickness T1 may, for example, be in the range of 5 to 25 nm. In one embodiment, the thickness T1 is about 10 nm. In embodiments where the Ge deposition is uniform, the cladding layer 314 may have a thickness, T2, as can be seen. The thickness T2 may, for example, be in the range of 0.5 to 6 nm. In one embodiment, the thickness T2 is about 4 nm. The thicknesses T1 and T2 may have different values ​​in other embodiments.

[0040] The Ge of cladding layer 314 can be deposited with or without dopants according to various embodiments. In some embodiments, cladding layer 314 consists entirely of Ge. In other embodiments, cladding layer 314 consists of Ge lightly doped with an n-type dopant, such as phosphorus (P) or arsenic (As), to provide barriers to source / drain reverse current leakage in PMOS transistors. Other suitable dopants may be used in other embodiments.

[0041] Referring to Fig. 3e depicts a transistor element 300e after applying a cap layer 316 to the cladding layer 314, as can be seen. The cap layer 316 may maintain the shape and compositional integrity of the cladding layer 314 before and during annealing. For example, in some embodiments, if annealing is performed without the cap layer 316, the cladding layer 314 may flow at temperatures well below the melting point of Ge and agglomerate in spaces between the fin structures 304, resulting in SiGe structures with uneven, inconsistent, or inappropriate Ge concentrations.

[0042] The capping layer 316 may provide structural stability of the transistor element 300e during annealing. For example, the capping layer 316 may be made of a material that structurally withstands annealing, prevents contamination of the cladding layer 314 during annealing, and can be removed after annealing. According to various embodiments, the capping layer 316 may include, for example, silicon nitride, silicon oxide, titanium nitride, and similar materials. In some embodiments, the capping layer 316 may have a thickness of 2 nanometers (nm) or greater. The capping layer 316 may be applied to substantially fill the space between the fin structures 304 in some embodiments. The capping layer 316 may include other materials or thicknesses in other embodiments.

[0043] Referring to Fig. 3f depicts a transistor element 300f after annealing the fin structures 304. Annealing may cause Ge to diffuse into Si of the fin structures 304 and form a structure comprising SiGe alloy (hereinafter, "SiGe portion 304a"). In some embodiments, after annealing, a portion of the fin structures 304 is made of Si and may be referred to as Si portion 304b.

[0044] After annealing, the cap layer 316 may be removed using a suitable technique, including, for example, an etching process. The etching process may include, for example, wet-etch fluorine chemistry (e.g., hydrofluoric acid) to remove a cap layer 316 consisting of oxide. In other embodiments, the etching process may include phosphoric acid chemistry selective for oxide to remove nitride without substantially removing electrically insulating material 306 consisting of oxide.

[0045] In some embodiments, the annealing is performed at temperatures greater than 700°C, such as 800°C, in an inert environment, such as nitrogen. The annealing time may be selected to provide a desired composition profile of Ge in the Si of the fin structures 304. For example, in some embodiments, the annealing time may be selected to completely or substantially completely convert the Si of the fin structures 304 encapsulated by the cladding layer 314 to SiGe. In one embodiment, a thin transistor element (e.g., fin structures 304) may be completely converted from Si to SiGe by annealing at 800°C for about one hour.

[0046] In other embodiments, the annealing time may be selected to partially convert the Si of the fin structures 304 encapsulated by the cladding layer 314 to SiGe. For example, the annealing time may be less than one hour (e.g., from seconds to fifteen minutes) at 800°C to partially convert the Si of a thin transistor element to SiGe. An anneal that partially converts the Si to SiGe may provide a Ge-rich surface on the fin structures 304 relative to a central portion of the fin structures 304. Example composition profiles of Ge in the fin structures 304 for different annealing times are described in connection with Fig. 8. Annealing is not limited to the example time and temperature presented here and may include other suitable temperatures and annealing times in other embodiments. For example, an annealing time may range from seconds to days, depending on a selected temperature and the desired composition of SiGe in the thin transistor element.

[0047] A thickness, T3, of the SiGe portion 304a of the fin structures 304 may be greater than the thickness T1 of the Si portion 304b. In some embodiments, the thickness T3 is approximately equivalent to the thickness T1 plus twice the thickness T2 of the cladding layer 314, as shown in Fig. 3d. Similar principles may apply to other structures, such as nanowires.

[0048] Fig. 4a-d depict a transistor element after actions in accordance with a second technique for converting Si to SiGe (e.g., the method 1200 of Fig. 12). Structures, techniques and configurations associated with the Fig. 4a-d can be used with analogous structures, techniques and configurations used in conjunction with Fig. 2, and vice versa. For example, although the SiGe deposition of the Fig. 4a-d for a crystalline configuration (e.g. faceted), in some embodiments, the SiGe deposition of the Fig. 4a-d preferably be uniform by amorphous or otherwise adapted application to achieve a cladding layer profile as in connection with Fig. To be provided as described and / or illustrated in 3d-f.

[0049] Referring to Fig. 4a depicts a transistor element 400a after forming fin structures 404 in a semiconductor substrate 402 and applying electrically insulating material 406 to the semiconductor substrate 402 between individual fin structures of the fin structures 404, as can be seen. According to various embodiments, the transistor element 400a may be formed according to techniques that may be used in connection with the Fig. 3a-c.

[0050] Referring to Fig. 4b depicts a transistor element 400b after depositing SiGe to form a cladding layer 414 made of SiGe on the fin structures 404, as can be seen. According to various embodiments, the Si 1-x Ge xdeposited to form the cladding layer 414 may have a composition where x is a value between 0.15 and 0.7, representing a ratio of Ge to Si. In some embodiments, x is a value between 0.2 and 0.5.

[0051] Similar to the first technique, the deposition of the SiGe according to the second technique may involve a crystalline (e.g., single crystal, polycrystalline) configuration of a faceted cladding layer 414 (e.g., as shown in Fig. 4b) or amorphous configuration of a uniform cladding layer 414. The deposition of the cladding layer 414 may be selective or non-selective for the electrically insulating material 406 and / or may include undoped SiGe or SiGe doped with an n-type dopant such as P or As, similar to that described in connection with the first technique. The SiGe may be deposited on all fin structures 404 or only on selected fins (e.g., by masking), as desired, to enable unique p-channel and n-channel compositions and / or to create multiple different concentration levels in multiple different fin structures 404.

[0052] Referring to Fig. 4c depicts a transistor element 400c after annealing the fin structures 404. Annealing may cause Ge of the SiGe cladding layer 414 to diffuse into the Si of the fin structures 404, forming a structure comprising SiGe alloy (hereinafter, "SiGe portion 404a"). In some embodiments, after annealing, a portion of the fin structures 404 is made of Si and may be referred to as Si portion 404b.

[0053] In some embodiments, annealing is performed in an oxidizing environment and forms an oxide layer 418 containing silicon oxide and, to a much lesser extent, germanium oxide. The oxidizing environment may contain, for example, oxygen, moisture, and / or nitrous oxide. Annealing in the oxidizing environment may accelerate the mixing of Si and Ge relative to annealing in an inert environment.

[0054] The annealing conditions can be adjusted by adjusting the annealing temperature and / or annealing time to provide an oxidation rate and diffusion rate for mixing Si and Ge compatible with a desired thickness of the resulting structures (e.g., fin structures 404). In some embodiments, the annealing conditions can include temperatures ranging, for example, from 700°C to 1200°C, for annealing times from seconds to hours to days, depending on the selected temperature and the desired composition of Ge in the SiGe portion 404a.

[0055] According to various embodiments, following annealing in an oxidizing environment, some of the Si of the fin structures 404 may be converted into oxide 418 (e.g., silicon dioxide), and the average composition of Ge in the Si-Ge portion 404a may be close to or equal to the composition of Ge in the deposited cladding layer 414 consisting of SiGe. By depositing a cladding layer (e.g., the cladding layer 414) with sufficient thickness to provide sufficient Ge for diffusion, the second SiGe cladding technique may provide a thickness that is greater than the thickness T3 of Fig. 3f. The oxide 418 can be used to reduce a fin width (e.g., by an etching process used in conjunction with Fig. 4d) to increase the electrostatic control of the channel.

[0056] Referring to Fig. 4d is a transistor element 400d after removing the oxide 418 from Fig. 4c. The oxide 418 may be removed using any suitable process, including, for example, an etching process using hydrofluoric acid. In cases where the electrically insulating material includes an oxide, the electrically insulating material 406 may be easily removed during the oxide 418 removal process.

[0057] The first technique and the second technique, which in conjunction with the Fig. 3d-f and Fig. 4a-d may be modified in some embodiments to convert Si of the Si portion 404b to SiGe. For example, in some embodiments, the electrically insulating material used in the Fig. 3c and Fig. 4a may not be applied before the annealing has been performed. That is, in some embodiments, the deposition of the cladding layer (e.g., 314 or 414) and the annealing may take place before the deposition of the electrically insulating material (e.g., 306 or 406) to provide a fin structure (e.g., including the Si portions 304b and 404b) that is fully converted from Si to SiGe.

[0058] Fig. 5 schematically illustrates a cross-sectional side view of a rib structure 504 in accordance with some embodiments. The rib structure 504 may be combined with rib structures used in conjunction with the Fig. 1-4 are identical, and vice versa.

[0059] The fin structure 504 may be formed from the material of the semiconductor substrate 502, as described herein. In some embodiments, a profile of the fin structure 504 may include a base portion 504c adjacent to the semiconductor substrate 502, a middle portion 504d, and an end portion 504e, with the middle portion 504d disposed between the base portion 504c and the end portion 504e, as can be seen. Prior to converting Si of the fin structure 504 to SiGe, the base portion 504c may have a thickness greater than a thickness of the middle portion 504d, and the middle portion 504d may have a thickness greater than a thickness of the end portion 504e, as can be seen.

[0060] Features of the fin structure 504 may include arcuate, curved profiles consistent with the patterning processes used to form the fin structure, as can be seen. The profile of the fin structure 504 may, in other embodiments, have other shapes or configurations consistent with known semiconductor manufacturing techniques.

[0061] Fig. 6 schematically illustrates a cross-sectional side view of a fin structure 604 on a semiconductor substrate 602 after converting a portion (e.g., the SiGe portion 604a) of the fin structure 604 from Si to SiGe in accordance with some embodiments. The fin structure 604 may include a SiGe portion 604a and a Si portion 604b. The fin structure 604 may be compatible with embodiments described in connection with the Fig. 1-4 are identical, and vice versa.

[0062] In some embodiments, a profile of the fin structure 604 may include a base portion 604c adjacent to the semiconductor substrate 602, a middle portion 604d, and a SiGe portion 604a, with the middle portion 604d being disposed between the base portion 604c and the SiGe portion 604a, as can be seen. The SiGe portion 604a may, in some embodiments, be configured to provide a channel body of a transistor device. After converting Si of the fin structure 604 to SiGe to provide the SiGe portion 604a, the base portion 604c may have a thickness greater than a thickness of the middle portion 604d, and the SiGe portion 604a may have a thickness greater than a thickness of the middle portion 604d (e.g., at 604f), as can be seen.

[0063] Features of the fin structure 604 may include arcuate, curved profiles consistent with the patterning processes used to form the fin structure, as can be seen. The profile of the fin structure 604, in other embodiments, may have other shapes or configurations consistent with known semiconductor manufacturing techniques. In some embodiments, the fin structure 604 may have a mushroom-shaped profile, as can be seen. In some embodiments, the electrically insulating material 606 may be removed further in a region between the fin structures than in a region directly adjacent to the fin structures 604, as can be seen. The line AB represents a cross-section through the fin structure 604 and is further associated with Fig. 8 described.

[0064] Fig. 7 schematically illustrates a cross-sectional side view of another fin structure 704 on a semiconductor substrate 702 after converting a portion (e.g., the SiGe portion 704a) of the fin structure 704 from Si to SiGe in accordance with some embodiments. The fin structure 704 may include a SiGe portion 704a and a Si portion 704b. The fin structure 704 may be compatible with embodiments described in connection with the Fig. 1-4 are identical, and vice versa.

[0065] In some embodiments, a profile of the fin structure 704 may include a base portion 704c adjacent to the semiconductor substrate 702, a middle portion 704d, and a SiGe portion 704a, where the middle portion 704d is disposed between the base portion 704c and the SiGe portion 704a, as can be seen. The SiGe portion 704a may, in some embodiments, be configured to provide a channel body of a transistor device. After converting Si of the fin structure 704 to SiGe to provide the SiGe portion 704a, the base portion 704c may have a thickness greater than a thickness of the middle portion 704d and the SiGe portion 704a, as can be seen. The SiGe portion 704a may be removed, for example, using an etch process to provide the SiGe portion 704a as depicted.

[0066] Features of the fin structure 704 may include arcuate, curved profiles consistent with the patterning processes used to form the fin structure, as can be seen. The profile of the fin structure 704, in other embodiments, may have other shapes or configurations consistent with known semiconductor manufacturing techniques. In some embodiments, the fin structure 704 may have a profile similar to the profile of the fin structure 504 of Fig. 5, as can be seen. In some embodiments, the electrically insulating material 706 may be removed further in a region between the rib structures than directly adjacent to the rib structures 704, as can be seen.

[0067] Fig. 8 schematically illustrates a diagram 800 depicting a composition profile of Ge through a transistor element in accordance with some embodiments. For example, the diagram 800 may depict a composition profile of Ge along line AB of the fin structure 604 of Fig. 6 for annealing times increasing from T0 to T1 to T2 to T3.

[0068] A composition of Ge is plotted on a vertical axis for different positions along the line AB of the rib structure 604 of Fig. 6. The time T0 may represent an annealing time of 0, which corresponds to a time after the application of the cladding layer and before annealing. For example, the time T0 may represent a cross-section through the cladding layer 314 and a rib structure 304, as shown in Fig. 3d. As can be seen, at time T0, moving along the time T0 curve from position A to position B from a leftmost portion of the diagram 800, the concentration of Ge starts very high (e.g., at or near 100% Ge) and drops dramatically to a very low concentration of Ge (e.g., at or near 0% Ge) after crossing the interface between the cladding layer 314, which is composed of Ge, and the rib structure 304, which is composed of Si.

[0069] At time T1 (e.g., 15 minutes at 800°C), the concentration of Ge in the cladding layer 314 decreases as the Ge diffuses into the fin structure (e.g., 304 or 604) to form SiGe. As can be seen, the concentration of Ge in the center (e.g., the midpoint between A and B) of the fin structure increases as SiGe is formed by annealing.

[0070] At time T2 (e.g., 30 minutes at 800 °C), the concentration of Ge in the cladding layer 314 continues to decrease, and the concentration of Ge in the center of the fin structure continues to increase relative to the concentration of Ge at time T1.

[0071] At time T3 (e.g., 45 minutes at 800°C), the Ge concentration in the cladding layer 314 continues to decrease, and the Ge concentration in the center of the fin structure continues to increase to provide a nearly linear Ge concentration (e.g., in the form of SiGe) throughout the fin structure. In some embodiments, the Ge concentration is substantially constant from an outer surface of the fin structure to the center of the fin structure.

[0072] In some embodiments, the composition profiles of Ge at times T1-T3 represent uniform distributions of Ge from an outer surface of the fin structure to the center of the fin structure, consistent with the diffusion of Ge by annealing a cladding layer comprising Ge on a channel body material consisting of Si to form SiGe. The composition profile of Ge at time T0 may not be a uniform distribution of Ge because Ge is found only in the cladding layer and not at all within the fin structure. According to various embodiments, the transistor elements described herein (e.g., fin structures) may include channel bodies having Ge composition profiles as described in connection with diagram 800.

[0073] Fig. 9 schematically illustrates a cross-sectional side view of a transistor element 900 including one or more nanowire structures (hereinafter "nanowire structures 904") in accordance with some embodiments. According to various embodiments, the nanowire structures 904 may be consistent with embodiments described in connection with other transistor elements, for example, including fin structures as described herein.

[0074] In some embodiments, the nanowire structures 904 are formed by converting Si from nanowires consisting of Si to SiGe to provide a SiGe portion 904a according to annealing techniques described herein (e.g., the first and / or second techniques). The nanowire structures 904 may, in some embodiments, have a composition profile of Ge throughout the nanowire structures 904, as described in connection with Fig. 8 is described.

[0075] In some embodiments, the nanowire structures 904 are formed in a region where material of a fin structure has been removed. For example, a Si portion 904b of the fin structure is depicted to show a relative position of the nanowire structures 904 to the fin structure in some embodiments. When the transistor element 900 is in operation, mobile charge carriers can be transferred through the nanowire structures 904 into the plane of the drawing. Fig. 9 between a source and a drain (not shown). The nanowire structure 904 may be formed according to any suitable technique. Electrically insulating material 906 may be disposed on the semiconductor substrate 902, and a gate electrode 908b may be disposed on the electrically insulating material 906. A gate dielectric 908a may, in some embodiments, be formed to surround the nanowire structures 904 to provide an AAG configuration. The semiconductor substrate 902, the electrically insulating material 906, the gate dielectric 908a, and the gate electrode 908b may be consistent with embodiments described in connection with similarly numbered features of Fig. 2 (e.g. 202, 206, 208a and 208b).

[0076] Fig. 10 schematically illustrates a top view of a chip 101 including n-type and p-type transistor elements, in accordance with some embodiments. For example, in some embodiments, a first region 1020 on the chip 101 may include one or more n-type transistor elements (e.g., channel body 1004a), and a second region 1030 on the chip 101 may include one or more p-type transistor elements (e.g., channel body 1004b).

[0077] The channel bodies 1004a and 1004b may, for example, represent fin structures and / or nanowire structures described herein. A concentration of Ge in the n-type transistor elements may be different than a concentration of Ge in the p-type transistor elements. In some embodiments, the p-type transistor elements have a higher concentration of Ge than the n-type transistor elements. For example, in some embodiments, Si of the p-type transistor elements may be converted to SiGe according to techniques described herein, and Si of the n-type transistor elements may be masked so that a cladding layer comprising Ge that is deposited on the p-type transistor elements is not deposited on the n-type elements.

[0078] The configuration of channel bodies 1004a and 1004b and regions 1020 and 1030 of chip 101 is merely one example configuration among many for the sake of discussion. Channel bodies 1004a and 1004b and regions 1020 and 1030 may, in other embodiments, include a wide variety of other suitable configurations. For example, channel bodies 1004a and 1004b may not traverse a substantial portion of chip 101, as depicted in some embodiments. In some embodiments, each channel body or group of channel bodies may have an opposite polarity (e.g., n-type or p-type) as an adjacent channel body or group of channel bodies to provide an alternating arrangement of n-channel and p-channel bodies.

[0079] Fig. 11 schematically illustrates a flowchart for a method 1100 for implementing a transistor element (e.g., the fin structure 304 of the Fig. 3b-f) from Si to SiGe in accordance with some embodiments. The method 1100 may be used with embodiments associated with the first technique of Fig. 3d-f are described, and vice versa.

[0080] At 1102, the method 1100 may include providing a semiconductor substrate (e.g., the semiconductor substrate 302 of Fig. 3a). In some embodiments, the semiconductor substrate may be a wafer (e.g., wafer 11 of Fig. 1) are included.

[0081] At 1104, the method 1100 may include forming a channel body (e.g., the rib structure 304 of Fig. 3B) a transistor device on the semiconductor substrate, wherein the channel body is made of Si. For example, the fin structures can be formed according to techniques associated with Fig. 3B. In other embodiments, the channel body may include other suitable configurations, including planar structures or nanowire structures formed according to known techniques. In some embodiments, providing the semiconductor substrate 1102 may include providing the semiconductor substrate having the channel body of the transistor device disposed on the semiconductor substrate.

[0082] At 1106, the method 1100 may include forming a cladding layer (e.g., the cladding layer 314 of Fig. 3d), consisting essentially of Ge (e.g., 70% to 100% Ge), may be included on the channel body. In some embodiments, the channel body is a first channel body of a fin structure. A second channel body of another fin structure (e.g., formed at 1104) may, in some embodiments, be arranged on the semiconductor substrate. Electrically insulating material may be deposited on the semiconductor substrate between the first channel body and the second channel body prior to forming the cladding layer. In such an embodiment, forming the cladding layer may include selectively depositing material of the cladding layer to form a cladding layer on the first channel body and the second channel body, but not on the electrically insulating material.In other embodiments, the electrically insulating material may be deposited on the semiconductor substrate between the first channel body and the second channel body after annealing the channel body to form SiGe.

[0083] According to various embodiments, the first channel body and the second channel body may be channel bodies made up of a plurality of p-channel bodies. A plurality of n-channel bodies (e.g., formed at 1104) may be arranged on the semiconductor substrate. In some embodiments, forming the cladding layer at 1106 includes applying the cladding layer material to the plurality of p-channel bodies without applying the cladding layer material to the plurality of n-channel bodies. For example, a masking process may be used to protect the n-channel bodies from the application of the cladding layer.

[0084] Forming the cladding layer at 1106 may, in some embodiments, include depositing Ge to form a uniform cladding layer consisting of Ge in an amorphous configuration on the channel body. In other embodiments, forming the cladding layer at 1106 may include depositing Ge to form a faceted cladding layer consisting of Ge in a single-crystal or polycrystalline configuration on the channel body.

[0085] In some embodiments, the material of the deposited cladding layer may be doped with an n-type dopant. In other embodiments, the material of the deposited cladding layer may be undoped.

[0086] At 1108, the method 1100 may include forming a cover layer (e.g., cover layer 316 of Fig. 3e) on the cladding layer. In some embodiments, forming the capping layer includes depositing a nitride or oxide material on the cladding layer to prevent Ge from flowing during annealing of the channel body.

[0087] At 1110, method 1100 may include annealing the channel body to cause the Ge to diffuse into the channel body. In some embodiments, annealing the channel body may be performed in an inert environment, such as nitrogen. The annealing may, in some embodiments, form SiGe from the Si of the channel body and the deposited cladding layer. The annealing may, in some embodiments, be performed with the capping layer in place. In some embodiments, the annealing may be performed at a temperature greater than 700°C. The annealing time may be determined according to the methods described herein (e.g., in Fig. 8) to provide a desired composition profile of Ge in the channel body. In some embodiments, annealing the channel body may provide a channel body composed primarily or entirely of SiGe.

[0088] At 1112, method 1100 may include removing the cap layer. The cap layer may be removed, for example, using an etching process.

[0089] At 1114, the method 1100 may include forming a gate on the channel body. For example, in some embodiments, forming the gate may include depositing a gate dielectric material and gate electrode material to form a respective gate dielectric (e.g., gate dielectrics 208a or 908a of the Fig. 2 or 9) and a gate electrode (gate electrodes 208a or 908b of the Fig. 2 or 9).

[0090] Fig. 12 schematically illustrates a flowchart for another method 1200 for implementing a transistor element (e.g., the fin structure 404 of the Fig. 4a-d) from Si to SiGe in accordance with some embodiments. The method 1200 may be used with embodiments associated with the second technique of Fig. 4a-d, and vice versa.

[0091] At 1202, method 1200 may include providing a semiconductor substrate, and at 1204, method 1200 may include forming a channel body of a transistor device on the semiconductor substrate, wherein the channel body is made of Si. In some embodiments, the techniques at 1202 and 1204 may be consistent with embodiments described in connection with 1102 and 1104 of method 1100 of Fig. 11 are described.

[0092] At 1206, method 1200 may include forming a cladding layer comprised of SiGe on the channel body. In some embodiments, forming the cladding layer may include depositing Si 1-x Ge x where x is a value between 0.15 and 0.7 representing a ratio of Ge to Si.

[0093] In some embodiments, the channel body is a first channel body of a fin structure. A second channel body of another fin structure (e.g., formed at 1204) may be disposed on the semiconductor substrate. Electrically insulating material may, in some embodiments, be deposited on the semiconductor substrate between the first channel body and the second channel body prior to forming the cladding layer. In such an embodiment, forming the cladding layer may include selectively depositing material of the cladding layer to form a cladding layer on the first channel body and the second channel body, but not the electrically insulating material. In other embodiments, the electrically insulating material may be deposited on the semiconductor substrate between the first channel body and the second channel body after annealing the channel body to form SiGe.

[0094] According to various embodiments, the first channel body and the second channel body may be channel bodies made up of a plurality of p-channel bodies. A plurality of n-channel bodies (e.g., formed at 1204) may be arranged on the semiconductor substrate. In some embodiments, forming the cladding layer at 1206 includes applying the cladding layer material to the plurality of p-channel bodies without applying the cladding layer material to the plurality of n-channel bodies. For example, a masking process may be used to protect the n-channel bodies from the application of the cladding layer.

[0095] Forming the cladding layer at 1206 may, in some embodiments, include depositing SiGe to form a uniform cladding layer consisting of SiGe in an amorphous configuration on the channel body. In other embodiments, forming the cladding layer at 1206 may include depositing SiGe to form a faceted cladding layer consisting of SiGe in a single-crystal or polycrystalline configuration on the channel body.

[0096] In some embodiments, the material of the deposited cladding layer may be doped with an n-type dopant. In other embodiments, the material of the deposited cladding layer may be undoped.

[0097] At 1208, method 1200 may include annealing the channel body in an oxidizing environment to cause the Ge of the cladding layer to diffuse into the channel body. The oxidizing environment may include, for example, oxygen, moisture, and / or nitrous oxide in some embodiments. In some embodiments, annealing the channel body in an oxidizing environment may accelerate the mixing of Si and Ge relative to an inert environment. Annealing the channel body in an oxidizing environment may form an oxide layer (e.g., SiO2) on the SiGe.

[0098] The annealing may form SiGe from the Si of the channel body. In some embodiments, the annealing may be performed at a temperature greater than 700°C. The annealing time may be determined according to the methods described herein (e.g., in Fig. 8) to provide a desired composition profile of Ge in the channel body. In some embodiments, annealing the channel body may provide a channel body composed primarily or entirely of SiGe.

[0099] At 1210, method 1200 may include removing an oxide layer from the SiGe. The oxide may be removed, for example, using an etching process.

[0100] At 1212, method 1200 may include forming a gate on the channel body. Forming the gate at 1212 may be consistent with embodiments described in connection with forming the gate at 1114 of method 1100 of Fig. 11 are described.

[0101] Various operations are described sequentially as multiple discrete operations in a manner most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted to imply that these operations are necessarily order-dependent. Embodiments of the present disclosure may be implemented in a system using any suitable hardware and / or software to be configured as desired. Fig. 13 schematically illustrates an example system that may include a transistor element having at least a portion converted from Si to SiGe in accordance with techniques described herein, in accordance with some embodiments. Computing device 1300 may include a printed circuit board, such as a motherboard 1302. Motherboard 1302 may include a number of components, including, but not limited to, a processor 1304 and at least one communications die 1306. Processor 1304 may be physically and electrically coupled to motherboard 1302. In some implementations, the at least one communications die 1306 may also be physically and electrically coupled to motherboard 1302. In further implementations, communications die 1306 may be part of processor 1304.

[0102] Depending on its application, computing device 1300 may include other components that may or may not be physically and electrically coupled to motherboard 1302. These other components may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display device, a touchscreen display device, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GSM) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such asa hard disk drive, a compact disk (CD), a digital versatile disk (DVD), and so on).

[0103] The communications die 1306 may enable wireless communications for transferring data to and from the computing device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data by using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not contain wires, although this may be the case in some embodiments. The communications die 1306 may implement any of a number of wireless standards or protocols, including the Institute for Electrical and Electronic Engineers (IEEE) standards, Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.11).16-2005 Amendment), Long Term Evolution Project (LTE Project), along with any modifications, updates, and / or revisions (e.g., Enhanced LTE Project, Ultra Mobile Broadband (UMB) Project (also referred to as "3GPP2"), etc.). IEEE 802.16-compliant BWA networks are commonly referred to as WiMAX networks, an acronym that stands for "Worldwide Interoperability for Microwave Access," which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The 1306 communications single chip can operate in accordance with a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.The communications single chip 1306 may operate in accordance with enhanced data for GSM evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or evolved UTRAN (E-UTRAN). The communications single chip 1306 may operate in accordance with code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless (DECT), evolution data optimized (EV-DO), derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond. In other embodiments, the communications single chip 1306 may operate in accordance with other wireless protocols.

[0104] Computing device 1300 may include multiple communication chips 1306. For example, a first communication chip 1306 may be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 1306 may be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.

[0105] The processor 1304 of the computing device 1300 may comprise a chip (e.g., the chip 101 of Fig. 1) that includes thin transistor elements made of SiGe and formed according to techniques described herein. For example, the chip 101 of Fig. 1 in a package assembly mounted on the motherboard 1302. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memories to transform that electronic data into other electronic data that can be stored in registers and / or memories.

[0106] The communication single chip 1306 may also include a chip (e.g., chip 101 of Fig. 1) comprising thin transistor elements made of SiGe formed according to the techniques described herein. In further implementations, another component (e.g., a memory device or other integrated circuit device) incorporated into the computing device 1300 may include a chip (e.g., the chip 101 of Fig.1) comprising thin transistor elements made of SiGe formed according to techniques described herein.

[0107] In various implementations, computing device 1300 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment device controller, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1300 may be any other electronic device that processes data.

Claims

[1] Procedure comprising: Providing (1102) a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon; forming (1106) a cladding layer comprising germanium on the channel body; forming (1108) a cover layer on the cladding layer; and Annealing (1110) the channel body to cause the germanium to diffuse into the channel body, wherein forming (1108) the capping layer on the cladding layer is performed prior to annealing the channel body and annealing the channel body with the capping layer disposed on the cladding layer. [2] The method of claim 1, wherein the germanium comprises from 70% to 100% of the cladding layer material. [3] The method of claim 2, wherein forming (1108) the capping layer comprises depositing a nitride or oxide material on the cladding layer to prevent the flow of germanium during annealing of the channel body. [4] A method according to any one of claims 2-3, further comprising: Removing the top layer; and Forming (1114) a gate of the transistor on the channel body. [5] Method according to any one of claims 1-3, wherein: the channel body of the transistor is a first channel body of a fin structure; the semiconductor substrate comprises a second channel body of a further rib structure arranged on the semiconductor substrate, and electrically insulating material arranged on the semiconductor substrate between the first channel body and the second channel body; and forming (1106) the cladding layer comprises selectively applying cladding layer material to form a cladding layer on the first channel body and the second channel body, but not on the electrically insulating material. [6] The method of claim 5, wherein: the first channel body and the second channel body are channel bodies made up of a plurality of p-channel bodies; the semiconductor substrate has a plurality of n-channel bodies arranged on the semiconductor substrate; and forming (1106) the cladding layer comprises applying the cladding layer material to the plurality of p-channel bodies without applying the cladding layer material to the plurality of n-channel bodies. [7] The method of any of claims 1-3, wherein forming (1106) the cladding layer comprises depositing germanium to form a uniform cladding layer consisting of germanium in an amorphous configuration on the channel body. [8] The method of claim 7, wherein: the channel body is made of single-crystal silicon; and the annealing (1110) of the channel body is carried out in an inert environment and forms silicon-germanium alloy, SiGe alloy, from the deposited germanium and the silicon of the channel body. [9] The method of any of claims 1-3, wherein forming (1106) the cladding layer comprises depositing germanium to form a faceted cladding layer comprised of germanium in a single crystal or polycrystalline configuration on the channel body. [10] The method of claim 1, wherein: the formation (1106) of the cladding layer the application of silicon germanium, Si 1-x Ge x , to form a cladding layer consisting of silicon germanium on the channel body; and x is a value in the range of 0.15 to 0.7 representing a ratio of germanium to silicon. [11] The method of claim 10, wherein depositing the silicon germanium comprises depositing silicon germanium to form a uniform or faceted layer comprised of silicon germanium in a single crystal, polycrystalline, or amorphous configuration on the channel body. [12] The method of any one of claims 10-11, wherein the annealing (1110) of the channel body is carried out in an oxidizing environment and forms an oxide layer on the silicon germanium, the method further comprising: removing (1112) the oxide layer from the silicon-germanium; and Forming (1114) a gate of the transistor on the channel body. [13] A method according to any one of claims 1-3, wherein: the annealing (1110) of the channel body provides a channel body that consists primarily or entirely of silicon-germanium alloy, SiGe alloy; and the tempering (1110) of the channel body is carried out at a temperature greater than 700 °C. [14] Device comprising: a semiconductor substrate (302) made of silicon; and a channel body of a transistor device disposed on the semiconductor substrate (302), the channel body comprising a silicon-germanium alloy, SiGe alloy, the channel body containing a uniform distribution of germanium from an outer surface of the channel body to a center of the channel body consistent with diffusion of the germanium by annealing a cladding layer (314) containing germanium on a channel body material consisting of silicon to form the SiGe alloy, wherein the channel body has a thickness that is twice the thickness of the cladding layer (314) plus a thickness of the channel body material consisting of silicon; and the channel body has a faceted crystalline profile or a profile consistent with the uniform application of the cladding layer (314). [15] The device of claim 14, wherein a concentration of germanium in the channel body is substantially constant or decreases from the outer surface of the channel body to the center of the channel body. [16] Device according to one of claims 14-15, wherein: the transistor device is a dual-gate, tri-gate, or all-around gate transistor device; and the channel body contains a part of a rib structure (304) formed from silicon of the semiconductor substrate (302) or a part of a nanowire structure. [17] Apparatus according to claim 16, wherein: the channel body contains a part of the rib structure (304); the rib structure (304) has a base portion adjacent to the semiconductor substrate (302), an end portion, and a middle portion disposed between the base portion and the end portion; the base portion has a thickness that is greater than a thickness of the middle portion; and the channel body has a thickness that is greater than a thickness of the central section. [18] The device of any of claims 14-15, wherein the channel body is a first channel body of a first transistor, the device further comprising: a second channel body disposed on the semiconductor substrate (302); and electrically insulating material (306) disposed on the semiconductor substrate (302) between the first channel body and the second channel body, wherein the first channel body and the second channel body are channel bodies of a plurality of p-channel bodies, the device further comprising: a plurality of n-channel bodies disposed on the semiconductor substrate (302), wherein the plurality of n-channel bodies have a concentration of germanium that is different from a concentration of germanium in the plurality of p-channel bodies. [19] Apparatus according to any one of claims 14-15, further comprising: a gate oxide formed on the channel body; and a gate electrode coupled to the channel body and configured to control the flow of charge carriers in the channel body. [20] System comprising: a circuit board; and a semiconductor chip coupled to the circuit board, the semiconductor chip including: a semiconductor substrate (302) formed of silicon, and a channel body of a transistor device disposed on the semiconductor substrate (302), the channel body comprising a silicon-germanium alloy, SiGe alloy, the channel body containing a uniform distribution of germanium from an outer surface of the channel body to a center of the channel body consistent with diffusion of the germanium by annealing a cladding layer (314) containing the germanium on a channel body material consisting of silicon to form the SiGe alloy, wherein the channel body has a thickness that is twice the thickness of the cladding layer (314) plus a thickness of the channel body material consisting of silicon; and the channel body has a faceted crystalline profile or a profile consistent with the uniform deposition of the cladding layer (314). [21] The system of claim 20, wherein: the channel body includes a portion of a rib structure (304) formed from silicon of the semiconductor substrate (302); the rib structure (304) has a base portion adjacent to the semiconductor substrate (302), an end portion, and a middle portion disposed between the base portion and the end portion; the base portion has a thickness that is greater than a thickness of the middle portion; and the channel body has a thickness that is greater than a thickness of the central section. [22] The system of any one of claims 20-21, wherein the system is one of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant, a PDA, an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment device controller, a digital camera, a portable music player, or a digital video recorder.

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