Leakage reduction structures for nanowire transistors

Abstract

The microelectronics structure includes: a microelectronics substrate (110); at least one nanowire transistor (100) formed on the microelectronic substrate (110) and a plurality of channel nanowires (140) n ) between a source structure (120) and a drain structure (130), wherein in cross-section around the plurality of channel nanowires (140 n ) around a dielectric gate material (192) is formed; a highly doped sublayer (180) formed between the microelectronic substrate (110) and the source and drain structure (120, 130) of the at least one nanowire transistor (100).

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to the field of nanowire microelectronic devices, and more particularly to a nanowire structure having sublayers between a microelectronic substrate and nanowire transistors formed thereon to substantially reduce or eliminate leakage in NMOS and PMOS structures. BACKGROUND

[0002] Higher performance, lower costs, greater miniaturization of integrated circuit components, and higher packaging density of integrated circuits are current goals of the microelectronics industry for the manufacture of microelectronic devices. As these goals are achieved, the size of microelectronic devices decreases, meaning they become smaller, increasing the need for optimal performance from every component of an integrated circuit.

[0003] By way of example, reference is made to the disclosure content in the documents US 2012 / 0 056 275 A1 and DE 10 2005 015 418 A1.

[0004] Maintaining mobility enhancement and short-channel control while shrinking the dimensions of microelectronic devices past the 15 nanometer (nm) nodes presents a challenge in microelectronic device fabrication. Nanowires can be used to fabricate microelectronic devices that offer improved short-channel control. For example, silicon-germanium (Si x Ge 1-x ) nanowire channel structures (where x < 0.5) provide mobility enhancement at a considerable Eg, which is suitable for use in many known products that require higher voltage operation. Furthermore, silicon-germanium (Si x Ge 1-x) Nanowire channels (where x > 0.5) exhibit mobility enhanced at lower Egs (suitable, for example, for low-voltage products in the mobile / handheld field).

[0005] Many different techniques have been tried for fabricating and dimensioning a nanowire-based device. However, there is still a need for improvements in the areas of transistor leakage and gate capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings. It is to be understood that the accompanying drawings illustrate only some embodiments of the present disclosure and are therefore not to be construed as limiting its scope. The disclosure is described with additional specificity and detail with the aid of the accompanying drawings so that the advantages of the present disclosure will be more fully appreciated. In the drawings: Fig. 1 an oblique view of a nanowire transistor. Fig. 2 is a cross-sectional side view of the attachment of an NMOS nanowire transistor and a PMOS nanowire transistor, generally along line 2-2 of Fig. 1 considered. Fig. 3 - Fig. 6 cross-sectional side views of a process for forming highly doped underlayers on a microelectronic substrate according to an embodiment of the present description. Fig. 7 - Fig. 9 cross-sectional side views of a process for forming highly doped sublayers on a microelectronic substrate according to another embodiment of the present description. Fig. 10 is a cross-sectional side view of a stacked layer formed on highly doped sublayers according to an embodiment of the present description. Fig. 11 is a cross-sectional side view of a process for forming a low-doped sublayer on the highly doped sublayers according to an embodiment of the present description. Fig. 12 a cross-sectional side view of a stacked layer deposited on the low-doped sublayer of Fig. 11, according to an embodiment of the present description. Fig. 13 - Fig. 22 Oblique views of a process for forming a nanowire transistor according to an embodiment of the present description. Fig. 23 is a flow diagram of a process for manufacturing a microelectronic device according to an embodiment of the present description. Fig. 24 a computing device according to an implementation of the present description. DESCRIPTION OF EMBODIMENTS

[0007] The invention is defined in the independent patent claims. Further developments are the subject of the dependent patent claims.

[0008] In the following detailed description, reference is made to the accompanying drawings that illustrate specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, while different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter.References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation contemplated by the present specification. Therefore, the phrase "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Further, it should be understood that the location or arrangement of individual elements in each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter.The following detailed description should therefore not be taken in a limiting sense, and the scope of the subject matter will be defined only by the appended claims, as properly construed, and the full scope of equivalents to which the appended claims are entitled. In the drawings, like reference characters refer to the same or substantially the same elements or functionality throughout the different views, and the elements shown herein are not necessarily to scale; rather, individual elements may be exaggerated or reduced in size to better understand the elements in the context of the present description.

[0009] Fig. 1 shows one embodiment of a microelectronic structure, such as a nanowire device structure. As illustrated, a nanowire transistor 100 may be formed on a microelectronic substrate 110. The nanowire transistor 100 may include a source structure 120 and a drain structure 130 spaced from the source structure 120. A plurality of undoped channel nanowires (illustrated as elements 1401, 1402, and 1403, collectively referred to herein as "nanowires 140 n “) may extend between the source structure 120 and the drain structure 130, wherein the nanowires 140 n vertically (e.g., in the z-direction) and spaced apart from each other. A gate structure 150 can connect the nanowires 140 nsurrounded by spacers 160 on opposite sides thereof. As illustrated, an interlayer dielectric material 170 may substantially surround the source structure 120 and the drain structure 130. The materials used and the processes performed to form the nanowire transistor 100 are discussed below.

[0010] As in Fig. 2, the nanowire transistor 100 can be Fig. 1 as an N-metal oxide semiconductor device or NMOS nanowire device with the reference symbol “100 NMO s” or as a P-metal oxide semiconductor device or PMOS nanowire device with the reference symbol “100 PMOS ", as is known to those skilled in the art. It is understood that the NMOS nanowire transistor 100 NMOS and the PMOS nanowire transistor 100 PMOSmay be formed on the same microelectronic substrate 110 and connected in a single circuit collectively known as a complementary metal oxide semiconductor device, referred to as "CMOS." During operation of either the PMOS nanowire transistors 100 PMOS or the NMOS nanowire transistors 100 NMOS Leakage and high gate capacitance may occur at a lower part of the gate structure 150, ie, in the region of the gate structure 150 adjacent to the microelectronic substrate 110, which is represented by a circle L.

[0011] Embodiments of the present description relate to nanowire devices having a highly doped underlayer formed between the nanowire transistors and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer can reduce or substantially eliminate leakage and high gate capacitance that may occur at a lower portion of a gate structure of the nanowire transistors. Since the formation of the highly doped underlayer can lead to gate-induced drain leakage at an interface between source and drain structures of the nanowire transistors, a thin layer of undoped or lightly doped material can be formed between the highly doped underlayer and the nanowire transistors to reduce or substantially eliminate such gate-induced drain leakage.

[0012] Fig. 3-6 show an embodiment of the fabrication of highly doped sublayers according to an embodiment of the present description. As in Fig. 3, the microelectronic substrate 110 may be provided or formed from any suitable material. In one embodiment, the microelectronic substrate 110 may be a bulk substrate formed from a single crystal of a material that may include, but is not limited to, silicon, germanium, silicon-germanium, or a III-V compound semiconductor material. In further embodiments, the microelectronic substrate 110 may comprise a silicon-on-insulator (SOI) substrate, wherein a top insulator layer formed from a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride is disposed on the bulk substrate.Alternatively, the microelectronic substrate 110 may be formed directly from a bulk substrate and local oxidation is used to form electrically insulating portions instead of the upper insulator layer described above.

[0013] As in Fig. 3, a portion of the microelectronic substrate 110 on which at least one PMOS nanowire transistor may be formed (see element 100 PMOS from Fig. 2), may be masked with a suitable first masking material 102, which includes, but is not limited to, photoresist materials such as polymethyl methacrylate, polymethyl glutarimide, phenol-formaldehyde resin, and the like. The unmasked portion of the microelectronic substrate 110 on which NMOS nanowire transistors may be formed (see element 100 NMOS from Fig. 2), may be coated with at least one P-dopant comprising, but not limited to, phosphorus, arsenic and antimony, indicated by arrows 112 in Fig. 3, to form a highly P-doped underlayer 114, as shown in Fig. 4. As also shown in Fig. 4, the first masking material 102 of Fig. 3. As in Fig. 5, a portion of the microelectronic substrate 110 on which at least one NMOS nanowire transistor (see element 100 NMOS from Fig. 2) may be masked with a suitable second masking material 104, such as that described with reference to the first masking material 102. The unmasked portion of the microelectronic substrate 110 on which PMOS nanowire transistors (see element 100 PMOS from Fig. 2) may be formed with at least one N-dopant comprising, but not limited to, boron, aluminum and gallium, which is indicated by arrows 116 in Fig. 5, to form a highly N-doped sublayer 118, as shown in Fig. 6. As also shown in Fig. 6, the second masking material 104 of Fig. 5. The removal of the first masking material 102 and the second masking material 104 can be achieved by any known technique, including, but not limited to, chemical stripping and ashing (plasma in fluorine or oxygen).

[0014] In a further embodiment of the present description, which is Fig. 7, a portion of the microelectronic substrate 110 on which at least one PMOS nanowire transistor is formed (see element 100 PMOS from Fig. 2), be masked with a suitable masking material 102. The unmasked portion of the microelectronic substrate 110 on which NMOS transistors are formed (see element 100 NMOS from Fig. 2), may have a highly P-doped sublayer 114 formed thereon. The highly P-doped sublayer 114 may be deposited epitaxially on the microelectronic substrate 110, such as by chemical vapor deposition, as also shown in Fig. 7. The highly P-doped sublayer 114 may be a monocrystalline film, such as silicon, with the microelectronics substrate 110 serving as a seed crystal and the highly P-doped sublayer 114 adopting the lattice structure and orientation of the microelectronics substrate 110. It will be appreciated by those skilled in the art that any combination of epitaxial growth / implantation / counter-doping / highly doped diffusion films may be used to dope the highly P-doped sublayer 114 to the desired level.

[0015] As in Fig. 8, the first masking material 102 of Fig. 7. As further stated in Fig. 8, a portion of the microelectronic substrate 110 on which at least one NMOS nanowire transistor is formed (see element 100 NMOS from Fig. 2), be masked with a suitable second masking material 104, such as that described with reference to the first masking material 102. The unmasked portion of the microelectronic substrate 110 on which PMOS transistors are formed (see element 100 PMOS from Fig. 2), may have a highly N-doped sublayer 118 formed thereon in substantially the same manner as that described with respect to the highly P-doped sublayer 114. As shown in Fig. 9, the second masking material 104 of Fig. 8 be removed.

[0016] It will be appreciated that damage that occurs during the formation of the highly P-doped sublayer 114 and / or the highly N-doped sublayer 118 may be repaired by annealing prior to further processing so that subsequent growth of material does not introduce defects from the highly P-doped sublayer 114 and / or the highly N-doped sublayer 118.

[0017] For the purposes of this application, the term “highly doped” may be defined as at least the amount of dopant required to increase the threshold voltage at a lower part (e.g., a region closest to the microelectronic substrate 110) of the gate structure 150 (see Fig. 1) is required so that leakage during operation of the nanowire transistor 100 (see Fig. 1) is prevented. It is known to those skilled in the art that the amount of dopant required depends on a variety of factors, including, but not limited to, the type of dopant used (i.e., P-type or N-type), the dopant used, the materials used (e.g., gate material, microelectronic substrate material, etc.), the voltage of the nanowire transistor, and the like.

[0018] In an embodiment described in Fig. 10, a first silicon material layer 1421 may be formed on the highly P-doped sublayer 114 and the highly N-doped sublayer 118, such as by epitaxial growth as is known in the art, and a first silicon-germanium material layer 1141 may be formed, such as by epitaxial growth on the first silicon material layer 1421. This layering may be continued up to a desired number of alternating silicon material layers (as layers 1421, 1422, and 1423 - collectively 142 n - shown) and silicon-germanium material layers (as layers 1441,1442 and 1443 - collectively 144 n - shown) are repeated, forming a resulting layered stack 146. In another embodiment, the order of layering may be reversed, with alternating layers of silicon material 144" and silicon-germanium material 142 nare each formed on the microelectronic substrate 110.

[0019] In another embodiment, since the formation of the highly P-doped sublayer 114 and the highly N-doped sublayer 118 may result in gate-induced leakage at an interface between the source structures 120 and / or the drain structures 130 of the NMOS nanowire transistors 100 NMOS and PMOS nanowire transistors 100 PMOS and their respective portion of the highly doped sublayer (ie, highly P-doped sublayer 114 and highly N-doped sublayer 118), a thin layer of undoped or low-doped material may be selectively formed on the highly P-doped sublayer 114 and the highly N-doped sublayer 118 to form a source / drain leakage barrier layer 122, as shown in Fig. 11. For the purposes of this application, the term "lightly doped material" may be defined to include a material layer having a lower dopant concentration than that of the highly P-doped sublayer 114 or the highly N-doped sublayer 118. In one embodiment, the source / drain leakage barrier layer 122 may be an undoped silicon-containing layer epitaxially grown on the P-doped sublayer 114 and the highly N-doped sublayer 118. In another embodiment, the source / drain leakage barrier layer 122 may be lightly doped with the dopant over which the portion of the source / drain leakage barrier layer 122 is formed.In other words, the source / drain leakage barrier layer 122 may be lightly doped with a P-type dopant in the portion above the highly P-doped sublayer 114 and / or may be lightly doped with an N-type dopant in the portion above the highly N-doped sublayer 118. In one embodiment, a thickness T of the source / drain leakage barrier layer 122 may be between approximately 0.5 and 5.0 nanometers.

[0020] After forming the source / drain leakage barrier layer 122, the layered stack 146 described above with reference to Fig. 10 has been discussed, be trained on this, as in Fig. 12 is shown.

[0021] Fig. 13-22 show a method of forming a nanowire transistor starting with the layered stack 146 of Fig. 10 and Fig. 12, as in Fig. 13. For brevity and clarity, the formation of a single nanowire transistor is illustrated and further illustrates an element 180 (hereinafter "underlayer 180") as either the highly P-doped underlayer 114 / highly N-doped underlayer 118 with the optionally provided source / drain leakage barrier layer 122 or the highly P-doped underlayer 114 / highly N-doped underlayer 118 without the optionally provided source / drain leakage barrier layer 122.

[0022] The layered stack 146 of silicon-germanium / silicon / silicon-germanium / silicon may be patterned using known patterning / etching techniques to form at least one fin structure 182. For example, the layered stack 146 (see Fig. 13) during a trench etching process, such as during a shallow trench isolation (STI) process, wherein trenches 184 may be formed through the underlayer 180 and into the microelectronics substrate 110 during the formation of the ridge structure 182. It is known to those skilled in the art that a plurality of substantially parallel ridge structures 182 are generally formed simultaneously. A dielectric material 186, such as silicon dioxide, may be formed or deposited in the trenches 184 proximate the microelectronics substrate 110, as shown in Fig. 14 to electrically isolate the fin structures 182.

[0023] As in Fig. 15, spacers 160 may be formed on and over the rib structures 182 and may be arranged substantially orthogonally relative to the rib structures 182. In one embodiment, the spacers 160 may comprise any material selected during subsequent processing of the rib structure 182 materials, as will be discussed. As further shown in Fig. 15, a sacrificial gate electrode material 152 may be formed within / between the spacers 160 and may be formed around portions of the fin structures 182 located between the spacers 160. In one embodiment, the sacrificial gate electrode material 152 may be formed around portions of the fin structure 182, and the spacers 160 may be formed on both sides of the sacrificial gate electrode material 152. The sacrificial gate electrode material 152 may comprise polysilicon, as will be discussed. As shown in Fig. As shown in Figure 16, a portion of each fin structure 182 (outside of the gate electrode material 152 and the spacers 160) may be removed to expose the underlayer 180. The portions of each fin structure 182 may be removed using any process known in the art, including, but not limited to, a dry etching process.

[0024] As in Fig. 17, silicon or silicon germanium source structures 120 and silicon or silicon germanium drain structures 130 may be formed on opposite sides of the fin structures 182 on the underlayer 180, such as by an epitaxial growth technique, and may be coupled to the portions of the fin structures 182 disposed between the spacers 160. In one embodiment, the source structure 120 or the drain structure 130 may be n-doped silicon for an NMOS device or may be p-doped silicon / silicon germanium for a PMOS device, depending on the device type for the particular application. Doping may be introduced into the epitaxial process by means of an implant, by plasma doping, by solid-state source doping, or by other methods known in the art.

[0025] As in Fig. 18, the dielectric interlayer 170 may be formed on the microelectronic substrate 100 over the source structures 120, the drain structures 130, the sacrificial gate electrode material 152, and the spacers 160, wherein the dielectric interlayer 170 may be planarized, such as by chemical mechanical polishing, to expose the sacrificial gate material 152. As shown in Fig. 19, the sacrificial gate electrode material 152 may then be removed from between the spacer materials 160, such as by means of an etching process. As shown in Fig. 20, the silicon material layers 1421, 1422 and 1423 (see Fig. 19) selectively from the rib structure 182 (see Fig. 19) between the silicon-germanium material layers 1441, 1442 and 1443 (see Fig. 19) to form silicon-germanium channel nanowires / nanoribbons (represented as elements 1401, 1402 and 1403, collectively referred to here as “channel nanowires 140 n “) located between the source structure 120 (see Fig. 17) and the drain structure 130, wherein the channel nanowires 140 n vertically aligned (e.g., in the z-direction) and spaced apart from each other. In one embodiment, the silicon material layers 1421, 1422, and 1423 may be etched using a wet etchant that selectively removes the silicon material layers 1421, 1422, and 1423 while leaving the silicon-germanium material layers 1441, 1442, and 1443 unetched. The wet etchant may include, but is not limited to, aqueous hydroxide chemicals, including ammonium hydroxide and potassium hydroxide.

[0026] In another embodiment, the silicon-germanium may be removed instead of the silicon. The silicon-germanium material layers 142 n can be selectively separated from the rib structure between the silicon material layers 144 n removed. Thus, the resulting channel nanowires 140 n , which in Fig. 20 may be formed of silicon. In one embodiment, the silicon germanium may be selectively etched with a wet etchant that selectively removes the silicon germanium while the silicon is not etched with the wet etchant, which includes, but is not limited to, a carboxylic acid / nitric acid / hydrofluoric acid solution and citric acid / nitric acid / hydrofluoric acid solutions. In some embodiments of the invention, the same silicon / silicon germanium stack is used to form both transistors with silicon channel nanowires and transistors with silicon germanium channel nanowires. In another embodiment of the invention, the layering order of the silicon / silicon germanium stack may alternate depending on whether silicon channel nanowires or silicon germanium channel nanowires are formed.

[0027] In one embodiment, both silicon and silicon-germanium channel nanowires 140 n be present on the same wafer, in the same die, or on the same circuit, for example, as NMOS-Si and PMOS-SiGe in an inverter structure. In one embodiment, for NMOS-Si and PMOS-SiGe in the same circuit, the Si channel thickness (SiGe interlayer) and the SiGe channel thickness (Si interlayer) can be mutually selected to increase the circuit performance and / or the circuit minimum operating voltage. In one embodiment, the number of nanowires on different devices in the same circuit can be varied by an etch process to increase the circuit performance and / or the circuit minimum operating voltage.

[0028] As in Fig. 21 (cross section along line 21-21 of Fig. 20), a gate dielectric material 192 may be formed to surround the channel nanowires 1401, 1402, and 1403 between the spacers 160. In one embodiment, the gate dielectric material 192 may comprise a high-k gate electrode material, where the dielectric constant may have a value greater than about 4. In another embodiment, the gate dielectric material 192 may be conformally formed around the nanowire structures 1401, 1402, and 1403.

[0029] As in Fig. 22, a gate electrode material 154 may then be formed around the nanowire structures 1401, 1402, and 1403 to form the gate electrode 150 and thereby form a nanowire transistor 100. The gate electrode material may comprise any suitable conductive material, including, but not limited to, pure metal and alloys of titanium, tungsten, tantalum, aluminum, including nitrides such as tantalum nitride and titanium nitride, and further including alloys with rare earth elements such as erbium and dysprosium, or noble metals such as platinum. It is understood that processing not shown may be performed, such as, for example, B. Forming trench contacts to the source structure 120 and the drain structure 130. In one embodiment, standard CMOS processing may further be performed on the microelectronic substrate 110 to fabricate a CMOS device according to embodiments described herein.It is known to those skilled in the art that the highly P-doped sublayer 114 and the highly N-doped sublayer 118 (see . Fig. 22) should be positioned at least between their respective gate electrodes 150 and the microelectronics substrate 110. As is further known to those skilled in the art, the source / drain leakage barrier layer 122, if used, should be positioned between the microelectronics substrate 110 and the respective source structure 120 and / or drain structure 130.

[0030] As is known to those skilled in the art, the highly P-doped sublayer 114 and / or the highly N-doped sublayer 118 may be formed by a conventional retrograde junction implant after the silicon material layers 102 n and the silicon-germanium material layers 104 nHowever, in such a process, a significant amount of dopant remains in the silicon material layers 102 n and silicon-germanium material layers 104 n , and thus, completely undoped nanowire channels cannot be formed. The presence of dopant in the nanowire channels can reduce carrier mobility and increase random dopant variation, as is well known to those skilled in the art.

[0031] Fig. 23 is a flow diagram of a process 200 for fabricating a nanowire transistor structure according to an embodiment of the present description. As set forth in block 210, a microelectronic substrate may be formed. A highly doped sublayer may be formed in or on the microelectronic substrate, as set forth in block 220. As set forth in block 230, an optional source / drain leakage barrier layer may be formed on the highly doped sublayer. A nanowire transistor may be formed on the highly doped sublayer and adjacent to the source / drain leakage barrier layer, if present, as set forth in block 240.

[0032] Fig. 24 shows a computing device 300 according to one implementation of the present description. Computing device 300 includes a circuit board 302. Circuit board 302 may include a number of components, including, but not limited to, a processor 304 and at least one communication chip 306. Processor 304 is physically and electrically coupled to circuit board 302. In some implementations, at least one communication chip 306 is also physically and electrically coupled to circuit board 302. In other implementations, communication chip 306 is part of processor 304.

[0033] Depending on the applications, computing device 300 may include additional components that may or may not be physically and electrically coupled to circuit board 302. These additional components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a compact disk (CD), a digital multi-purpose disk (DVD), and so on).

[0034] The transmission chip 306 enables wireless transmissions for the communication of data to and from the computing device 300. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, transmission channels, etc., that can transmit data using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not contain wires, although in some embodiments they may not. The transmission chip 306 can implement any number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol referred to as 3G, 4G, 5G, and beyond. Computing device 300 may include a plurality of transmission chips 306. For example, a first transmission chip 306 may be dedicated to shorter-range wireless transmissions, such as Wi-Fi and Bluetooth, and a second transmission chip 306 may be dedicated to longer-range transmissions, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0035] The processor 304 of the computing device 300 includes an integrated circuit die packaged within the processor 304. In some implementations of the present description, the integrated circuit die of the processor includes one or more devices, such as nanowire transistors, constructed according to implementations of the present description. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0036] The transfer chip 306 also includes an integrated circuit die within the transfer chip 306. According to another implementation of the present description, the integrated circuit die of the transfer chip includes one or more devices, such as nanowire transistors, constructed according to implementations of the present description.

[0037] In further implementations, another component included in computing device 300 may include an integrated circuit die having one or more devices, such as nanowire transistors, constructed according to implementations of the present description.

[0038] In various implementations, computing device 300 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment device controller, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 300 may be any other electronic device that processes data.

[0039] It is understood that the subject matter of the present description does not necessarily apply to the Fig. 1-24. The subject matter may be applied to other microelectronic device and assembly applications, as well as to suitable transistor applications, as will be known to those skilled in the art.

[0040] The following examples relate to further embodiments, wherein Example 1 is a microelectronic structure comprising a microelectronic substrate; at least one nanowire transistor formed on the microelectronic substrate; and a highly doped underlayer formed between the microelectronic substrate and the at least one nanowire transistor.

[0041] In Example 2, the article of Example 1 can optionally comprise the highly doped underlayer comprising a dopant layer implanted into the microelectronic substrate.

[0042] In Example 3, the article of Example 1 can optionally comprise the highly doped underlayer comprising a highly doped material layer formed in the microelectronic substrate.

[0043] In Example 4, the subject matter of Example 3 can optionally comprise the highly doped material layer comprising a highly doped epitaxial silicon layer.

[0044] In Example 5, the subject matter of any of Examples 1 to 4 can optionally comprise the highly doped underlayer comprising a highly P-doped underlayer, and wherein the at least one nanowire transistor comprises at least one NMOS nanowire transistor.

[0045] In Example 6, the subject matter of any of Examples 1 to 4 can optionally comprise the highly doped underlayer comprising a highly N-doped underlayer, and wherein the at least one nanowire transistor comprises at least one PMOS nanowire transistor.

[0046] In Example 7, the subject matter of any of Examples 1 to 4 can optionally comprise a portion of the highly doped sublayer comprising a highly P-doped sublayer portion, wherein the at least one nanowire transistor comprises at least one NMOS nanowire transistor formed thereon, and a portion of the highly doped sublayer comprising a highly N-doped sublayer portion, wherein the at least one nanowire transistor comprises at least one PMOS nanowire transistor formed thereon.

[0047] In Example 8, the subject matter of any of Examples 1 to 7 can optionally include a source / drain leakage barrier layer between the highly doped underlayer and the nanowire transistor.

[0048] In Example 9, the subject matter of Example 8 can optionally include the source / drain leakage barrier layer having a thickness between about 0.5 and 5.0 nanometers.

[0049] In Example 10, the subject matter of any of Examples 8 or 9 can optionally include the source / drain leakage barrier layer comprising an undoped material layer.

[0050] In Example 11, the subject matter of Example 10 can optionally comprise the undoped material layer comprising an epitaxial silicon layer.

[0051] Example 12 is the subject matter of Example 8 or 9, wherein the source / drain leakage barrier layer comprises a low-doped material layer.

[0052] Example 13 is a method of forming a microelectronic structure comprising forming a microelectronic substrate; forming at least one nanowire transistor on the microelectronic substrate; and forming a highly doped underlayer formed between the microelectronic substrate and the at least one nanowire transistor.

[0053] In Example 14, the subject matter of Example 13 can optionally include forming the highly doped underlayer comprising implanting a dopant into the microelectronic substrate.

[0054] In Example 15, the subject matter of Example 13 can optionally include forming the highly doped underlayer, which comprises forming a highly doped material layer on the microelectronic substrate.

[0055] In Example 16, the subject matter of Example 15 can optionally include forming the highly doped underlayer, which includes forming a highly doped epitaxial silicon layer.

[0056] In Example 17, the subject matter of any of Examples 13 to 16 can optionally comprise forming the highly doped underlayer, comprising forming a highly P-doped underlayer, and wherein forming the at least one nanowire transistor comprises forming at least one NMOS nanowire transistor.

[0057] In Example 18, the subject matter of any of Examples 13 to 16 can optionally comprise forming the highly doped underlayer, comprising forming a highly N-doped underlayer, and wherein forming the at least one nanowire transistor comprises forming at least one PMOS nanowire transistor.

[0058] In Example 19, the subject matter of any of Examples 13 to 16 can optionally comprise forming the highly doped sublayer, comprising forming a portion of the highly doped sublayer as a highly P-doped sublayer, wherein the at least one nanowire transistor comprises at least one NMOS nanowire transistor formed thereon, and forming a portion of the highly doped sublayer as a highly N-doped sublayer portion, wherein the at least one nanowire transistor comprises at least one PMOS nanowire transistor formed thereon.

[0059] In Example 20, the subject matter of any of Examples 13 to 16 can optionally comprise forming a highly doped underlayer comprising forming a first mask over a portion of the microelectronics substrate; ion implanting one of a P-type or an N-type dopant into an unmasked portion of the microelectronics substrate; removing the first mask; forming a second mask over the ion-implanted portion of the microelectronics substrate; ion implanting the other of the P-type or the N-type dopant into an unmasked portion of the microelectronics substrate; and removing the second mask.

[0060] In Example 21, the subject matter of any of Examples 13 to 16 can optionally comprise forming the highly doped underlayer, comprising forming a first mask over a portion of the microelectronics substrate; forming a material layer having one of a P-type or an N-type dopant therein on an unmasked portion of the microelectronics substrate; removing the first mask; forming a second mask over the ion-implanted portion of the microelectronics substrate; forming a material layer having the other of the P-type or the N-type dopant therein on an unmasked portion of the microelectronics substrate; and removing the second mask.

[0061] In Example 22, the subject matter of any of Examples 13 to 21 can optionally further comprise forming a source / drain leakage barrier layer between the highly doped underlayer and the nanowire transistor.

[0062] In Example 23, the subject matter of Example 22 can optionally include forming the source / drain leakage barrier layer, which comprises forming the source / drain leakage barrier layer with a thickness between about 0.5 and 5.0 nanometers.

[0063] In Example 24, the subject matter of any of Examples 22 to 23 can optionally comprise forming the source / drain leakage barrier layer comprising forming an undoped material layer.

[0064] In Example 25, the subject matter of Example 24 can optionally include forming the undoped material layer, which includes forming an epitaxial silicon layer.

[0065] In Example 26, the subject matter of any of Examples 22 to 23 can optionally comprise the undoped material layer comprising a low-doped material layer.

[0066] In Example 27, a computing system may include a circuit board having at least one component; wherein the at least one component includes at least one microelectronic structure having a microelectronic substrate; at least one nanowire transistor formed on the microelectronic substrate; and a highly doped underlayer formed between the microelectronic substrate and the at least one nanowire transistor.

[0067] In Example 28, the subject matter of Example 27 can optionally further comprise a source / drain leakage barrier layer between the highly doped underlayer and the nanowire transistor.

[0068] In Example 29, the subject matter of Example 27 can optionally include the source / drain leakage barrier layer comprising an undoped material layer.

[0069] In Example 30, the subject matter of Example 28 can optionally include the source / drain leakage barrier layer comprising a low-doped material layer.

[0070] Having thus described the embodiments of the present specification in detail, it is to be understood that the present specification, as defined by the appended claims, is not limited to the specific details set forth in the foregoing description, since numerous obvious variations thereof may be made without departing from the spirit or scope thereof.

Claims

[1] Microelectronic structure that includes: a microelectronic substrate (110); at least one nanowire transistor (100) formed on the microelectronic substrate (110) and comprising a plurality of channel nanowires (140 n ) between a source structure (120) and a drain structure (130), wherein in cross section around the plurality of channel nanowires (140 n ) a dielectric gate material (192) is formed around it; a highly doped underlayer (180) formed between the microelectronic substrate (110) and the source and drain structure (120, 130) of the at least one nanowire transistor (100). [2] The microelectronic structure of claim 1, wherein the highly doped underlayer (180) comprises a dopant layer implanted into the microelectronic substrate (110). [3] The microelectronic structure of claim 1, wherein the highly doped underlayer (180) comprises a highly doped material layer formed on the microelectronic substrate (110). [4] The microelectronic structure of claim 3, wherein the highly doped material layer comprises a highly doped epitaxial silicon layer. [5] The microelectronic structure of claim 1, wherein the highly doped underlayer (180) comprises a highly P-doped underlayer (114) and wherein the at least one nanowire transistor (100) comprises at least one NMOS nanowire transistor. [6] The microelectronic structure of claim 1, wherein the highly doped sublayer (180) comprises a highly N-doped sublayer (118) and wherein the at least one nanowire transistor comprises at least one PMOS nanowire transistor. [7] The microelectronic structure of claim 1, wherein a portion of the highly doped sublayer (180) comprises a highly P-doped sublayer portion, wherein the at least one nanowire transistor comprises at least one NMOS nanowire transistor formed thereon, and wherein a portion of the highly doped sublayer comprises a highly N-doped sublayer portion, wherein the at least one nanowire transistor comprises at least one PMOS nanowire transistor formed thereon. [8] The microelectronic structure of any one of claims 1 to 7, further comprising a source / drain leakage barrier layer (122) between the highly doped underlayer (180) and the nanowire transistor (100). [9] The microelectronic structure of claim 8, wherein the source / drain leakage barrier layer (122) has a thickness between about 0.5 and 5.0 nanometers. [10] The microelectronic structure of claim 8, wherein the source / drain leakage barrier layer (122) comprises an undoped material layer. [11] The microelectronic structure of claim 10, wherein the undoped material layer comprises an epitaxial silicon layer. [12] The microelectronic structure of claim 8, wherein the source / drain leakage barrier layer (122) comprises a low-doped material layer. [13] A method of forming a microelectronic structure, comprising: Forming a microelectronic substrate (110); Forming at least one nanowire transistor (100) on the microelectronic substrate having a plurality of channel nanowires (140 n ) between a source structure (120) and a drain structure (130), wherein in cross section around the plurality of channel nanowires (140 n ) around which a dielectric gate material (192) is formed; and Forming a highly doped underlayer (180) formed between the microelectronic substrate (110) and the source and drain structure (120, 130) of the at least one nanowire transistor (100). [14] The method of claim 13, wherein forming the highly doped underlayer (180) comprises implanting a dopant into the microelectronic substrate (110). [15] The method of claim 13, wherein forming the highly doped sublayer (180) comprises forming a highly doped material layer on the microelectronic substrate. [16] The method of claim 15, wherein forming the highly doped material layer comprises forming a highly doped epitaxial silicon layer. [17] The method of claim 13, wherein forming the highly doped sublayer (180) comprises forming a highly P-doped sublayer (114) and wherein forming the at least one nanowire transistor comprises forming at least one NMOS nanowire transistor. [18] The method of claim 13, wherein forming the highly doped sublayer (180) comprises forming a highly N-doped sublayer (118) and wherein forming the at least one nanowire transistor comprises forming at least one PMOS nanowire transistor. [19] The method of claim 13, wherein forming the highly doped sublayer (180) comprises forming a portion of the highly doped sublayer as a highly P-doped sublayer, wherein the at least one nanowire transistor (100) comprises at least one NMOS nanowire transistor formed thereon, and forming a portion of the highly doped sublayer (180) as a highly N-doped sublayer portion, wherein the at least one nanowire transistor (100) comprises at least one PMOS nanowire transistor formed thereon. [20] The method of claim 13, wherein forming the highly doped underlayer (180) comprises: Forming a first mask over a portion of the microelectronic substrate (110); ion implanting one of a P-type or an N-type dopant into an unmasked portion of the microelectronic substrate (110); Removing the first mask; Forming a second mask over the ion-implanted portion of the microelectronic substrate (110); ion implanting the other of the P-type or N-type dopant into an unmasked portion of the microelectronic substrate (110); and Removing the second mask. [21] The method of claim 13, wherein forming the highly doped underlayer (180) comprises: Forming a first mask over a portion of the microelectronic substrate (110); Forming a material layer having one of a P-type and an N-type dopant therein on an unmasked portion of the microelectronic substrate (110); Removing the first mask; Forming a second mask over the ion-implanted portion of the microelectronic substrate (110); forming a material layer having the other of the P-type or N-type dopant therein on an unmasked portion of the microelectronic substrate (110); and Removing the second mask. [22] The method of any one of claims 13 to 21, further comprising forming a source / drain leakage barrier layer (122) between the highly doped underlayer (180) and the nanowire transistor (100). [23] The method of claim 22, wherein forming the source / drain leakage barrier layer (122) comprises forming the source / drain leakage barrier layer with a thickness between approximately 0.5 and 5.0 nanometers. [24] The method of claim 22, wherein forming the source / drain leakage barrier layer (122) comprises forming an undoped material layer. [25] The method of claim 22, wherein the undoped material layer comprises a low-doped material layer.

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